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3fee3ac61f
* Add RISC-V demo for the spike simulator. * Figuring out what the header checker wants. * Fix more headers. * Ignore htif.c and htif.h for header checks. These files are already stamped with BSD-3-Clause, which I'm not allowed to remove. There are numerous other files with the same license in FreeRTOS, so I assume this is fine. * Use proxy syscalls for RV32. Looks like spike won't be changed to make htif character writes work propery for RV32. This is now an even closer copy of the version in opensbi, which is arguably strictly better. * Support RV64 builds to use with spike. OpenOCD does not currently support debugging 64-bit FreeRTOS, but now that I have a target to test hopefully that will be remedied shortly. * Tweak rv32 instructions. This way you can have separate cross-tools installations that can coexist side by side. Co-authored-by: Joseph Julicher <jjulicher@mac.com>
33 lines
789 B
INI
33 lines
789 B
INI
adapter_khz 10000
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interface remote_bitbang
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remote_bitbang_host localhost
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remote_bitbang_port 9824
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos auto
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#target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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# Expose an unimplemented CSR so we can test non-existent register access
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# behavior.
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riscv expose_csrs 2288
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riscv expose_custom 1,12345-12348
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init
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set challenge [riscv authdata_read]
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riscv authdata_write [expr $challenge + 1]
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halt
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reg mstatus 0
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arm semihosting enable
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