mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
a07f649bd5
* Armv8-M: Formatting changes Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com> * Armv8-M: Add support for interrupt priority check FreeRTOS provides `FromISR` system calls which can be called directly from interrupt service routines. It is crucial that the priority of these ISRs is set to same or lower value (numerically higher) than that of `configMAX_SYSCALL_INTERRUPT_PRIORITY`. For more information refer to https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. Add a check to trigger an assert when an ISR with priority higher (numerically lower) than `configMAX_SYSCALL_INTERRUPT_PRIORITY` calls `FromISR` system calls if `configASSERT` macro is defined. In addition, add a config option `configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` to disable interrupt priority check while running on QEMU. Based on the discussion https://gitlab.com/qemu-project/qemu/-/issues/1122, The interrupt priority bits in QEMU do not match the real hardware. Therefore the assert that checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. The config option `configQEMU_DISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the `FreeRTOSConfig.h` for QEMU targets. Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com> * Use SHPR2 for calculating interrupt priority bits This removes the dependency on the secure software to mark the interrupt as non-secure. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> --------- Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com> Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
331 lines
12 KiB
C
331 lines
12 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTMACROCOMMON_H
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#define PORTMACROCOMMON_H
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/*------------------------------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the given hardware
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* and compiler.
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*
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* These settings should not be altered.
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*------------------------------------------------------------------------------
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*/
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#ifndef configENABLE_FPU
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#error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
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#endif /* configENABLE_FPU */
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#ifndef configENABLE_MPU
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#error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
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#endif /* configENABLE_MPU */
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#ifndef configENABLE_TRUSTZONE
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#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
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#endif /* configENABLE_TRUSTZONE */
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/*-----------------------------------------------------------*/
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/**
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* @brief Type definitions.
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*/
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#else
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#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
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#endif
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/*-----------------------------------------------------------*/
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/**
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* Architecture specifics.
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*/
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portNOP()
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#define portINLINE __inline
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#ifndef portFORCE_INLINE
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#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
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#endif
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#define portHAS_STACK_OVERFLOW_CHECKING 1
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/*-----------------------------------------------------------*/
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/**
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* @brief Extern declarations.
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*/
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extern BaseType_t xPortIsInsideInterrupt( void );
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extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
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extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
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extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
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extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
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extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
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#if ( configENABLE_TRUSTZONE == 1 )
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extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
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extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
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#endif /* configENABLE_TRUSTZONE */
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#if ( configENABLE_MPU == 1 )
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extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
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extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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/**
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* @brief MPU specific constants.
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*/
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#if ( configENABLE_MPU == 1 )
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#define portUSING_MPU_WRAPPERS 1
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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#else
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#define portPRIVILEGE_BIT ( 0x0UL )
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#endif /* configENABLE_MPU */
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/* MPU settings that can be overriden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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/* Define to 8 for backward compatibility. */
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#define configTOTAL_MPU_REGIONS ( 8UL )
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#endif
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/* MPU regions. */
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#define portPRIVILEGED_FLASH_REGION ( 0UL )
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#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
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#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
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#define portPRIVILEGED_RAM_REGION ( 3UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 5UL )
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#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
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#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
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#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
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/* Device memory attributes used in MPU_MAIR registers.
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*
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* 8-bit values encoded as follows:
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* Bit[7:4] - 0000 - Device Memory
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* Bit[3:2] - 00 --> Device-nGnRnE
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* 01 --> Device-nGnRE
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* 10 --> Device-nGRE
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* 11 --> Device-GRE
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* Bit[1:0] - 00, Reserved.
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*/
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#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
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#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
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#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
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#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
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/* Normal memory attributes used in MPU_MAIR registers. */
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#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
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#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
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/* Attributes used in MPU_RBAR registers. */
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#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
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#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
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#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
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#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
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#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
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#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
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/*-----------------------------------------------------------*/
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/**
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* @brief Settings to define an MPU region.
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*/
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typedef struct MPURegionSettings
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{
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uint32_t ulRBAR; /**< RBAR for the region. */
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uint32_t ulRLAR; /**< RLAR for the region. */
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} MPURegionSettings_t;
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/**
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* @brief MPU settings as stored in the TCB.
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*/
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typedef struct MPU_SETTINGS
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{
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uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
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MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
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} xMPU_SETTINGS;
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/*-----------------------------------------------------------*/
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/**
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* @brief Validate priority of ISRs that are allowed to call FreeRTOS
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* system calls.
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*/
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#ifdef configASSERT
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#if ( portHAS_BASEPRI == 1 )
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void vPortValidateInterruptPriority( void );
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#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
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#endif
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#endif
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/**
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* @brief SVC numbers.
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*/
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#define portSVC_ALLOCATE_SECURE_CONTEXT 0
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#define portSVC_FREE_SECURE_CONTEXT 1
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#define portSVC_START_SCHEDULER 2
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#define portSVC_RAISE_PRIVILEGE 3
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/*-----------------------------------------------------------*/
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/**
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* @brief Scheduler utilities.
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*/
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#define portYIELD() vPortYield()
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
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while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/**
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* @brief Critical section management.
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*/
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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/*-----------------------------------------------------------*/
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/**
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* @brief Tickless idle/low power functionality.
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*/
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#ifndef portSUPPRESS_TICKS_AND_SLEEP
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extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
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#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
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#endif
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/*-----------------------------------------------------------*/
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/**
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* @brief Task function macros as described on the FreeRTOS.org WEB site.
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*/
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
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/*-----------------------------------------------------------*/
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#if ( configENABLE_TRUSTZONE == 1 )
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/**
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* @brief Allocate a secure context for the task.
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*
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* Tasks are not created with a secure context. Any task that is going to call
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* secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
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* secure context before it calls any secure function.
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*
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* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
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*/
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#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
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/**
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* @brief Called when a task is deleted to delete the task's secure context,
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* if it has one.
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*
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* @param[in] pxTCB The TCB of the task being deleted.
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*/
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#define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
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#endif /* configENABLE_TRUSTZONE */
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/*-----------------------------------------------------------*/
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#if ( configENABLE_MPU == 1 )
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/**
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* @brief Checks whether or not the processor is privileged.
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*
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* @return 1 if the processor is already privileged, 0 otherwise.
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*/
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#define portIS_PRIVILEGED() xIsPrivileged()
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/**
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* @brief Raise an SVC request to raise privilege.
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*
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* The SVC handler checks that the SVC was raised from a system call and only
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* then it raises the privilege. If this is called from any other place,
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* the privilege is not raised.
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*/
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#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
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/**
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* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
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* register.
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*/
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#define portRESET_PRIVILEGE() vResetPrivilege()
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#else
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#define portIS_PRIVILEGED()
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#define portRAISE_PRIVILEGE()
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#define portRESET_PRIVILEGE()
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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/**
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* @brief Barriers.
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*/
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#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
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/*-----------------------------------------------------------*/
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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#endif
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/* *INDENT-ON* */
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#endif /* PORTMACROCOMMON_H */
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