mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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989bc332b2
* Add XMOS XCore ports Some minor modifications are also made to the kernel to support the XCore compiler's automatic stack size calculation. * Update kernel to support SMP The XMOS XCore ports are also updated to support SMP. * Fix compiler warnings in xcore ports The port set and clear interrupt mask from ISR macros were removed from the ports so that the default macros found in FreeRTOS.h are used instead. The default macros do not result in warnings when they are used. * Remove inline function from timers.h Inline function converted to macro. This should now build when optimizations are off and inlining is disabled. * Fix compiler warnings in xcore ports and tasks.c * fixed documentation for ulTaskNotifyTake() and ulTaskNotifyTakeIndexed() * spelling fixes for tasks.c Co-authored-by: Michael Bruno <mikeb@xmos.com>
106 lines
4.7 KiB
C
106 lines
4.7 KiB
C
/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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/* Standard includes. */
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#include <stdint.h>
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/* Secure init includes. */
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#include "secure_init.h"
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/* Secure port macros. */
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#include "secure_port_macros.h"
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/**
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* @brief Constants required to manipulate the SCB.
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*/
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#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
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#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
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#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
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#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
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#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
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/**
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* @brief Constants required to manipulate the FPU.
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*/
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#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
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#define secureinitFPCCR_LSPENS_POS ( 29UL )
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#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
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#define secureinitFPCCR_TS_POS ( 26UL )
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#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
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#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
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#define secureinitNSACR_CP10_POS ( 10UL )
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#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
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#define secureinitNSACR_CP11_POS ( 11UL )
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#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
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{
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uint32_t ulIPSR;
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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*( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
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( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
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( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
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}
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}
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
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{
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uint32_t ulIPSR;
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
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* permitted. CP11 should be programmed to the same value as CP10. */
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*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
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/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
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* that we can enable/disable lazy stacking in port.c file. */
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*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
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/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
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* registers (S16-S31) are also pushed to stack on exception entry and
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* restored on exception return. */
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*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
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}
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}
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/*-----------------------------------------------------------*/
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