mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-05-22 13:09:04 -04:00
989bc332b2
* Add XMOS XCore ports Some minor modifications are also made to the kernel to support the XCore compiler's automatic stack size calculation. * Update kernel to support SMP The XMOS XCore ports are also updated to support SMP. * Fix compiler warnings in xcore ports The port set and clear interrupt mask from ISR macros were removed from the ports so that the default macros found in FreeRTOS.h are used instead. The default macros do not result in warnings when they are used. * Remove inline function from timers.h Inline function converted to macro. This should now build when optimizations are off and inlining is disabled. * Fix compiler warnings in xcore ports and tasks.c * fixed documentation for ulTaskNotifyTake() and ulTaskNotifyTakeIndexed() * spelling fixes for tasks.c Co-authored-by: Michael Bruno <mikeb@xmos.com>
378 lines
18 KiB
ArmAsm
378 lines
18 KiB
ArmAsm
/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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EXTERN pxCurrentTCB
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EXTERN xSecureContext
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EXTERN vTaskSwitchContext
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EXTERN vPortSVCHandler_C
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EXTERN SecureContext_SaveContext
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EXTERN SecureContext_LoadContext
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PUBLIC xIsPrivileged
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PUBLIC vResetPrivilege
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PUBLIC vPortAllocateSecureContext
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PUBLIC vRestoreContextOfFirstTask
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PUBLIC vRaisePrivilege
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PUBLIC vStartFirstTask
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PUBLIC ulSetInterruptMask
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PUBLIC vClearInterruptMask
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PUBLIC PendSV_Handler
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PUBLIC SVC_Handler
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PUBLIC vPortFreeSecureContext
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#if ( configENABLE_FPU == 1 )
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#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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#endif
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/*-----------------------------------------------------------*/
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/*---------------- Unprivileged Functions -------------------*/
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/*-----------------------------------------------------------*/
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SECTION .text:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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xIsPrivileged:
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mrs r0, control /* r0 = CONTROL. */
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movs r1, #1 /* r1 = 1. */
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tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
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beq running_privileged /* If the result of previous AND operation was 0, branch. */
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movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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bx lr /* Return. */
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running_privileged:
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movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vResetPrivilege:
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mrs r0, control /* r0 = CONTROL. */
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movs r1, #1 /* r1 = 1. */
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orrs r0, r1 /* r0 = r0 | r1. */
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msr control, r0 /* CONTROL = r0. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vPortAllocateSecureContext:
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svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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/*----------------- Privileged Functions --------------------*/
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/*-----------------------------------------------------------*/
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SECTION privileged_functions:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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vRestoreContextOfFirstTask:
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r3, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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#if ( configENABLE_MPU == 1 )
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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movs r5, #1 /* r5 = 1. */
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bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r4, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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movs r5, #4 /* r5 = 4. */
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str r5, [r2] /* Program RNR = 4. */
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ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */
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movs r5, #5 /* r5 = 5. */
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str r5, [r2] /* Program RNR = 5. */
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ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */
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movs r5, #6 /* r5 = 6. */
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str r5, [r2] /* Program RNR = 6. */
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ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */
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movs r5, #7 /* r5 = 7. */
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str r5, [r2] /* Program RNR = 7. */
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ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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movs r5, #1 /* r5 = 1. */
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orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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#if ( configENABLE_MPU == 1 )
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ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
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ldr r5, =xSecureContext
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str r1, [r5] /* Set xSecureContext to this task's value for the same. */
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msr psplim, r2 /* Set this task's PSPLIM value. */
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msr control, r3 /* Set this task's CONTROL value. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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bx r4 /* Finally, branch to EXC_RETURN. */
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#else /* configENABLE_MPU */
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ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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ldr r4, =xSecureContext
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str r1, [r4] /* Set xSecureContext to this task's value for the same. */
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msr psplim, r2 /* Set this task's PSPLIM value. */
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movs r1, #2 /* r1 = 2. */
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msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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bx r3 /* Finally, branch to EXC_RETURN. */
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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vRaisePrivilege:
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mrs r0, control /* Read the CONTROL register. */
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movs r1, #1 /* r1 = 1. */
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bics r0, r1 /* Clear the bit 0. */
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msr control, r0 /* Write back the new CONTROL value. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vStartFirstTask:
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ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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msr msp, r0 /* Set the MSP back to the start of the stack. */
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cpsie i /* Globally enable interrupts. */
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dsb
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isb
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svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
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/*-----------------------------------------------------------*/
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ulSetInterruptMask:
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mrs r0, PRIMASK
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cpsid i
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bx lr
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/*-----------------------------------------------------------*/
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vClearInterruptMask:
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msr PRIMASK, r0
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bx lr
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/*-----------------------------------------------------------*/
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PendSV_Handler:
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mrs r1, psp /* Read PSP in r1. */
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ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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cbz r0, save_ns_context /* No secure context to save. */
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push {r0-r2, r14}
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bl SecureContext_SaveContext
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pop {r0-r3} /* LR is now in r3. */
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mov lr, r3 /* LR = r3. */
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lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r2, [r3] /* Read pxCurrentTCB. */
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#if ( configENABLE_MPU == 1 )
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subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mrs r3, control /* r3 = CONTROL. */
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mov r4, lr /* r4 = LR/EXC_RETURN. */
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stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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#else /* configENABLE_MPU */
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subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
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#endif /* configENABLE_MPU */
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b select_next_task
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save_ns_context:
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r2, [r3] /* Read pxCurrentTCB. */
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#if ( configENABLE_MPU == 1 )
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subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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adds r1, r1, #16 /* r1 = r1 + 16. */
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stmia r1!, {r4-r7} /* Store the low registers that are not saved automatically. */
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mov r4, r8 /* r4 = r8. */
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mov r5, r9 /* r5 = r9. */
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mov r6, r10 /* r6 = r10. */
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mov r7, r11 /* r7 = r11. */
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stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mrs r3, control /* r3 = CONTROL. */
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mov r4, lr /* r4 = LR/EXC_RETURN. */
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subs r1, r1, #48 /* r1 = r1 - 48. */
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stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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#else /* configENABLE_MPU */
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subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmia r1!, {r0, r2-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
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mov r4, r8 /* r4 = r8. */
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mov r5, r9 /* r5 = r9. */
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mov r6, r10 /* r6 = r10. */
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mov r7, r11 /* r7 = r11. */
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stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */
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#endif /* configENABLE_MPU */
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select_next_task:
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cpsid i
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bl vTaskSwitchContext
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cpsie i
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r3, [r2] /* Read pxCurrentTCB. */
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ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
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#if ( configENABLE_MPU == 1 )
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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movs r5, #1 /* r5 = 1. */
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bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r4, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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movs r5, #4 /* r5 = 4. */
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str r5, [r2] /* Program RNR = 4. */
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ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */
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movs r5, #5 /* r5 = 5. */
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str r5, [r2] /* Program RNR = 5. */
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ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */
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movs r5, #6 /* r5 = 6. */
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str r5, [r2] /* Program RNR = 6. */
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ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */
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movs r5, #7 /* r5 = 7. */
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str r5, [r2] /* Program RNR = 7. */
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ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */
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ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
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stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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movs r5, #1 /* r5 = 1. */
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orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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#if ( configENABLE_MPU == 1 )
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ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
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msr psplim, r2 /* Restore the PSPLIM register value for the task. */
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msr control, r3 /* Restore the CONTROL register value for the task. */
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mov lr, r4 /* LR = r4. */
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ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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str r0, [r2] /* Restore the task's xSecureContext. */
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cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
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push {r1,r4}
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bl SecureContext_LoadContext /* Restore the secure context. */
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pop {r1,r4}
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mov lr, r4 /* LR = r4. */
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lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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msr psp, r1 /* Remember the new top of stack for the task. */
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bx lr
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#else /* configENABLE_MPU */
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ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
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msr psplim, r2 /* Restore the PSPLIM register value for the task. */
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mov lr, r3 /* LR = r3. */
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ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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str r0, [r2] /* Restore the task's xSecureContext. */
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cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
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push {r1,r3}
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bl SecureContext_LoadContext /* Restore the secure context. */
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pop {r1,r3}
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mov lr, r3 /* LR = r3. */
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lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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msr psp, r1 /* Remember the new top of stack for the task. */
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bx lr
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#endif /* configENABLE_MPU */
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restore_ns_context:
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adds r1, r1, #16 /* Move to the high registers. */
|
|
ldmia r1!, {r4-r7} /* Restore the high registers that are not automatically restored. */
|
|
mov r8, r4 /* r8 = r4. */
|
|
mov r9, r5 /* r9 = r5. */
|
|
mov r10, r6 /* r10 = r6. */
|
|
mov r11, r7 /* r11 = r7. */
|
|
msr psp, r1 /* Remember the new top of stack for the task. */
|
|
subs r1, r1, #32 /* Go back to the low registers. */
|
|
ldmia r1!, {r4-r7} /* Restore the low registers that are not automatically restored. */
|
|
bx lr
|
|
/*-----------------------------------------------------------*/
|
|
|
|
SVC_Handler:
|
|
movs r0, #4
|
|
mov r1, lr
|
|
tst r0, r1
|
|
beq stacking_used_msp
|
|
mrs r0, psp
|
|
b vPortSVCHandler_C
|
|
stacking_used_msp:
|
|
mrs r0, msp
|
|
b vPortSVCHandler_C
|
|
/*-----------------------------------------------------------*/
|
|
|
|
vPortFreeSecureContext:
|
|
ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
|
|
ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
|
|
cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
|
|
beq free_secure_context
|
|
bx lr /* There is no secure context (xSecureContext is NULL). */
|
|
free_secure_context:
|
|
svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
|
|
bx lr /* Return. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
END
|