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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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989bc332b2
* Add XMOS XCore ports Some minor modifications are also made to the kernel to support the XCore compiler's automatic stack size calculation. * Update kernel to support SMP The XMOS XCore ports are also updated to support SMP. * Fix compiler warnings in xcore ports The port set and clear interrupt mask from ISR macros were removed from the ports so that the default macros found in FreeRTOS.h are used instead. The default macros do not result in warnings when they are used. * Remove inline function from timers.h Inline function converted to macro. This should now build when optimizations are off and inlining is disabled. * Fix compiler warnings in xcore ports and tasks.c * fixed documentation for ulTaskNotifyTake() and ulTaskNotifyTakeIndexed() * spelling fixes for tasks.c Co-authored-by: Michael Bruno <mikeb@xmos.com>
239 lines
8 KiB
C
239 lines
8 KiB
C
/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the Atmel AT91R40008
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* port.
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*
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in this file. The ISR routines, which can only be compiled
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* to ARM mode are contained in portISR.c.
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*----------------------------------------------------------*/
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/* Standard includes. */
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#include <stdlib.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Hardware specific definitions. */
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#include "AT91R40008.h"
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#include "pio.h"
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#include "aic.h"
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#include "tc.h"
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/* Constants required to setup the task context. */
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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#define portTICK_PRIORITY_6 ( 6 )
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/*-----------------------------------------------------------*/
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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/*
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* The scheduler can only be started from ARM mode, so
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* vPortISRStartFirstSTask() is defined in portISR.c.
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*/
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extern void vPortISRStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been called.
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*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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StackType_t *pxOriginalTOS;
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pxOriginalTOS = pxTopOfStack;
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/* To ensure asserts in tasks.c don't fail, although in this case the assert
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is not really required. */
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pxTopOfStack--;
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/* Setup the initial stack of the task. The stack is set exactly as
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expected by the portRESTORE_CONTEXT() macro. */
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/* First on the stack is the return address - which in this case is the
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start of the task. The offset is added to make the return address appear
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as it would within an IRQ ISR. */
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*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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pxTopOfStack--;
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/* When the task starts is will expect to find the function parameter in
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R0. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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/* The last thing onto the stack is the status register, which is set for
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system mode, with interrupts enabled. */
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*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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#ifdef THUMB_INTERWORK
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{
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/* We want the task to start in thumb mode. */
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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#endif
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pxTopOfStack--;
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/* Some optimisation levels use the stack differently to others. This
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means the interrupt flags cannot always be stored on the stack and will
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instead be stored in a variable, which is then saved as part of the
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tasks context. */
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*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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/* Start the first task. */
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vPortISRStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the ARM port will require this function as there
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is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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/*
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* Setup the tick timer to generate the tick interrupts at the required frequency.
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*/
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static void prvSetupTimerInterrupt( void )
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{
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volatile uint32_t ulDummy;
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/* Enable clock to the tick timer... */
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AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
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/* Stop the tick timer... */
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portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
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/* Start with tick timer interrupts disabled... */
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portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
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/* Clear any pending tick timer interrupts... */
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ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
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/* Store interrupt handler function address in tick timer vector register...
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The ISR installed depends on whether the preemptive or cooperative
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scheduler is being used. */
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#if configUSE_PREEMPTION == 1
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{
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extern void ( vPreemptiveTick )( void );
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AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
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}
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#else // else use cooperative scheduler
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{
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extern void ( vNonPreemptiveTick )( void );
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AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
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}
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#endif
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/* Tick timer interrupt level-sensitive, priority 6... */
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AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
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/* Enable the tick timer interrupt...
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First at timer level */
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portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
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/* Then at the AIC level. */
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AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
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/* Calculate timer compare value to achieve the desired tick rate... */
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if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
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{
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/* The tick rate is fast enough for us to use the faster timer input
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clock (main clock / 2). */
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portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
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portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
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}
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else
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{
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/* We must use a slower timer input clock (main clock / 8) because the
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tick rate is too slow for the faster input clock. */
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portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
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portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
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}
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/* Start tick timer... */
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portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
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}
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/*-----------------------------------------------------------*/
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