mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
222 lines
6.6 KiB
ArmAsm
222 lines
6.6 KiB
ArmAsm
/*
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FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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All rights reserved
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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.org 0
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.text
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.set SYS_MODE, 0x1f
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.set SVC_MODE, 0x13
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.set IRQ_MODE, 0x12
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.extern _boot
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.extern vTaskSwitchContext
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.extern ulICCIAR
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.extern ulICCEOIR
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.global _vector_table
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.global FIQInterrupt
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.global Undefined
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.global PrefetchAbortHandler
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.global DataAbortInterrupt
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.section .vectors
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_vector_table:
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B _boot
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B Undefined
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ldr pc, _swi
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B PrefetchAbortHandler
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B DataAbortHandler
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NOP /* Placeholder for address exception vector*/
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LDR PC, _irq
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B FIQHandler
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_irq: .word FreeRTOS_IRQ_Handler
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_swi: .word FreeRTOS_SWI_Handler
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/******************************************************************************
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* SVC handler is used to start the scheduler and yield a task.
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*****************************************************************************/
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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// portSAVE_CONTEXT
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LDR R0, =vTaskSwitchContext
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BLX R0
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vPortRestoreTaskContext:
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// portRESTORE_CONTEXT
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FreeRTOS_IRQ_Handler:
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/* Return to the interrupted instruction. */
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SUB lr, lr, #4
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/* Push the return address and SPSR. */
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PUSH {lr}
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MRS lr, SPSR
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PUSH {lr}
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/* Change to supervisor mode to allow reentry. */
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CPS #SVC_MODE
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/* Push used registers. */
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PUSH {r0-r4, r12}
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/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
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for future use. r1 holds the original ulPortInterruptNesting value for
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future use. */
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LDR r3, =ulPortInterruptNesting
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LDR r1, [r3]
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ADD r4, r1, #1
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STR r4, [r3]
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/* Read value from the interrupt acknowledge register, which is stored in r0
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for future parameter and interrupt clearing use. */
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LDR r2, ulICCIARConst
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LDR r0, [r2]
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/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
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future use. */
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MOV r2, sp
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AND r2, r2, #4
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SUB sp, sp, r2
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/* Call the interrupt handler. */
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PUSH {r0-r3, lr}
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BL vApplicationIRQHandler
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POP {r0-r3, lr}
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ADD sp, sp, r2
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CPSID i
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/* Write the value read from ICCIAR to ICCEOIR. */
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LDR r4, ulICCEOIRConst
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STR r0, [r4]
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/* Restore the old nesting count. */
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STR r1, [r3]
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/* A context switch is never performed if the nesting count is not 0. */
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CMP r1, #0
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BNE exit_without_switch
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/* Did the interrupt request a context switch? r1 holds the address of
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ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
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use. */
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LDR r1, =ulPortYieldRequired
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LDR r0, [r1]
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CMP r0, #0
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BNE switch_before_exit
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exit_without_switch:
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/* No context switch. Restore used registers, LR_irq and SPSR before
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returning. */
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POP {r0-r4, r12}
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CPS #IRQ_MODE
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POP {LR}
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MSR SPSR_cxsf, LR
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POP {LR}
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MOVS PC, LR
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switch_before_exit:
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/* A context swtich is to be performed. Clear the context switch pending
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flag. */
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MOV r0, #0
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STR r0, [r1]
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/* Restore used registers, LR-irq and SPSR before saving the context
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to the task stack. */
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POP {r0-r4, r12}
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CPS #IRQ_MODE
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POP {LR}
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MSR SPSR_cxsf, LR
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POP {LR}
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// portSAVE_CONTEXT
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/* Call the function that selects the new task to execute.
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vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
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instructions, or 8 byte aligned stack allocated data. LR does not need
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saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
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BL vTaskSwitchContext
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/* Restore the context of, and branch to, the task selected to execute
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next. */
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// portRESTORE_CONTEXT
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ulICCIARConst: .word ulICCIAR
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ulICCEOIRConst: .word ulICCEOIR
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Undefined:
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B .
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PrefetchAbortHandler:
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B .
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FIQHandler:
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B .
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DataAbortHandler:
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B .
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.end
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