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The introduction of `portMEMORY_BARRIER` will ensure the places in the kernel use a barrier will work. For example, `xTaskResumeAll` has a memory barrier to ensure its correctness when compiled with optimization enabled. Without the barrier `xTaskResumeAll` can fail (e.g. start reading and writing to address 0 and/or infinite looping) when `xPendingReadyList` contains more than one task to restore. In `xTaskResumeAll` the compiler chooses to cache the `pxTCB` the first time through the loop for use in every subsequent loop. This is incorrect as the removal of `pxTCB->xEventListItem` will actually change the value of `pxTCB` if it was read again at the top of the loop. The barrier forces the compiler to read `pxTCB` again at the top of the loop. The compiler is operating correctly. The removal `pxTCB->xEventListItem` executes on a `List_t *` and `ListItem_t *`. This means that the compiler can assume that any `MiniListItem_t` values are unchanged by the loop (i.e. "strict-aliasing"). This allows the compiler to cache `pxTCB` as it is obtained via a `MiniListItem_t`. This is incorrect in this case because it is possible for a `ListItem_t *` to actually alias a `MiniListItem_t`. This is technically a "violation of aliasing rules" so we use the the barrier to disable the strict-aliasing optimization in this loop. |
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| .. | ||
| ARM7_AT91FR40008 | ||
| ARM7_AT91SAM7S | ||
| ARM7_LPC23xx | ||
| ARM7_LPC2000 | ||
| ARM_CA9 | ||
| ARM_CA53_64_BIT | ||
| ARM_CA53_64_BIT_SRE | ||
| ARM_CM0 | ||
| ARM_CM3 | ||
| ARM_CM3_MPU | ||
| ARM_CM4_MPU | ||
| ARM_CM4F | ||
| ARM_CM7 | ||
| ARM_CM23 | ||
| ARM_CM23_NTZ/non_secure | ||
| ARM_CM33 | ||
| ARM_CM33_NTZ/non_secure | ||
| ARM_CM55 | ||
| ARM_CM55_NTZ/non_secure | ||
| ARM_CM85 | ||
| ARM_CM85_NTZ/non_secure | ||
| ARM_CR5 | ||
| ARM_CRx_No_GIC | ||
| ATMega323 | ||
| AVR32_UC3 | ||
| AVR_AVRDx | ||
| AVR_Mega0 | ||
| ColdFire_V2 | ||
| CORTUS_APS3 | ||
| H8S2329 | ||
| HCS12 | ||
| IA32_flat | ||
| MCF5235 | ||
| MicroBlaze | ||
| MicroBlazeV8 | ||
| MicroBlazeV9 | ||
| MSP430F449 | ||
| NiosII | ||
| PPC405_Xilinx | ||
| PPC440_Xilinx | ||
| RISC-V | ||
| RL78 | ||
| RX100 | ||
| RX200 | ||
| RX600 | ||
| RX600v2 | ||
| RX700v3_DPFPU | ||
| STR75x | ||
| TriCore_1782 | ||