mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
76be28cdc6
Earlier the System Call entry from an unprivileged task
looked like:
1. SVC for entering system call.
2. System call implementation.
3. SVC for exiting system call.
Now, the system call entry needs to make only one SVC
call and everything else is handled internally.
This PR also makes the following changes:
1. Update the Access Control List (ACL) mechanism to
grant access to all the kernel objects before the
scheduler is started.
2. Add one struct param for system calls with 5 parameters.
This removes the need for special handling for system
calls with 5 parameters.
3. Remove raise privilege SVC when MPU wrapper v2 is used.
4. Add additional run time parameter checks to MPU wrappers
for xTaskGenericNotify and xQueueTakeMutexRecursive APIs.
307 lines
12 KiB
ArmAsm
307 lines
12 KiB
ArmAsm
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Including FreeRTOSConfig.h here will cause build errors if the header file
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contains code not understood by the assembler - for example the 'extern' keyword.
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To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
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the code is included in C files but excluded by the preprocessor in assembly
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files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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#include <FreeRTOSConfig.h>
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#include <mpu_syscall_numbers.h>
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RSEG CODE:CODE(2)
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thumb
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EXTERN pxCurrentTCB
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EXTERN vTaskSwitchContext
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EXTERN vPortSVCHandler_C
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EXTERN vSystemCallEnter
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EXTERN vSystemCallExit
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PUBLIC xPortPendSVHandler
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PUBLIC vPortSVCHandler
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PUBLIC vPortStartFirstTask
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PUBLIC vPortEnableVFP
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PUBLIC vPortRestoreContextOfFirstTask
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PUBLIC xIsPrivileged
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PUBLIC vResetPrivilege
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/*-----------------------------------------------------------*/
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#ifndef configUSE_MPU_WRAPPERS_V1
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#define configUSE_MPU_WRAPPERS_V1 0
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#endif
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/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
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* and r0p1 cores. */
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#ifndef configENABLE_ERRATA_837070_WORKAROUND
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#define configENABLE_ERRATA_837070_WORKAROUND 0
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#endif
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/* These must be in sync with portmacro.h. */
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#define portSVC_START_SCHEDULER 100
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#define portSVC_SYSTEM_CALL_EXIT 103
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/*-----------------------------------------------------------*/
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xPortPendSVHandler:
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ldr r3, =pxCurrentTCB
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ldr r2, [r3] /* r2 = pxCurrentTCB. */
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ldr r1, [r2] /* r1 = Location where the context should be saved. */
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/*------------ Save Context. ----------- */
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mrs r3, control
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mrs r0, psp
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isb
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add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */
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tst lr, #0x10
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ittt eq
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vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
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vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
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vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
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sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */
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stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */
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ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */
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stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */
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str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */
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/*---------- Select next task. --------- */
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mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
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#endif
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msr basepri, r0
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dsb
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isb
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
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#endif
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bl vTaskSwitchContext
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mov r0, #0
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msr basepri, r0
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/*------------ Program MPU. ------------ */
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ldr r3, =pxCurrentTCB
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ldr r2, [r3] /* r2 = pxCurrentTCB. */
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add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r0, =0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [r0] /* Read the value of MPU_CTRL. */
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bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [r0] /* Disable MPU. */
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ldr r0, =0xe000ed9c /* Region Base Address register. */
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ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
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stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
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#ifdef configTOTAL_MPU_REGIONS
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#if ( configTOTAL_MPU_REGIONS == 16 )
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ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
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ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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#endif /* configTOTAL_MPU_REGIONS == 16. */
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#endif
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ldr r0, =0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [r0] /* Read the value of MPU_CTRL. */
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orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [r0] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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/*---------- Restore Context. ---------- */
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ldr r3, =pxCurrentTCB
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ldr r2, [r3] /* r2 = pxCurrentTCB. */
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ldr r1, [r2] /* r1 = Location of saved context in TCB. */
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ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
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msr psp, r0
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stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */
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ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
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msr control, r3
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tst lr, #0x10
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ittt eq
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vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
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vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
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vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
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str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
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bx lr
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/*-----------------------------------------------------------*/
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#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
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vPortSVCHandler:
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tst lr, #4
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ite eq
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mrseq r0, msp
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mrsne r0, psp
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ldr r1, [r0, #24]
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ldrb r2, [r1, #-2]
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cmp r2, #NUM_SYSTEM_CALLS
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blt syscall_enter
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cmp r2, #portSVC_SYSTEM_CALL_EXIT
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beq syscall_exit
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b vPortSVCHandler_C
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syscall_enter:
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mov r1, lr
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b vSystemCallEnter
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syscall_exit:
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mov r1, lr
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b vSystemCallExit
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#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
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vPortSVCHandler:
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#ifndef USE_PROCESS_STACK
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tst lr, #4
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ite eq
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mrseq r0, msp
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mrsne r0, psp
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#else
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mrs r0, psp
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#endif
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b vPortSVCHandler_C
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#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
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/*-----------------------------------------------------------*/
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vPortStartFirstTask:
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/* Use the NVIC offset register to locate the stack. */
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ldr r0, =0xE000ED08
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ldr r0, [r0]
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ldr r0, [r0]
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/* Set the msp back to the start of the stack. */
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msr msp, r0
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/* Clear the bit that indicates the FPU is in use in case the FPU was used
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before the scheduler was started - which would otherwise result in the
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unnecessary leaving of space in the SVC stack for lazy saving of FPU
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registers. */
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mov r0, #0
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msr control, r0
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/* Call SVC to start the first task. */
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cpsie i
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cpsie f
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dsb
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isb
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svc #portSVC_START_SCHEDULER
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/*-----------------------------------------------------------*/
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vPortRestoreContextOfFirstTask:
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ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [r0]
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ldr r0, [r0]
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msr msp, r0 /* Set the msp back to the start of the stack. */
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/*------------ Program MPU. ------------ */
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ldr r3, =pxCurrentTCB
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ldr r2, [r3] /* r2 = pxCurrentTCB. */
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add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r0, =0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [r0] /* Read the value of MPU_CTRL. */
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bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [r0] /* Disable MPU. */
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ldr r0, =0xe000ed9c /* Region Base Address register. */
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ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
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stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
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#ifdef configTOTAL_MPU_REGIONS
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#if ( configTOTAL_MPU_REGIONS == 16 )
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ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
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ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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#endif /* configTOTAL_MPU_REGIONS == 16. */
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#endif
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ldr r0, =0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [r0] /* Read the value of MPU_CTRL. */
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orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [r0] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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/*---------- Restore Context. ---------- */
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ldr r3, =pxCurrentTCB
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ldr r2, [r3] /* r2 = pxCurrentTCB. */
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ldr r1, [r2] /* r1 = Location of saved context in TCB. */
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ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
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msr psp, r0
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stmia r0, {r4-r11} /* Copy the hardware saved context on the task stack. */
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ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
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msr control, r3
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str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
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mov r0, #0
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msr basepri, r0
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bx lr
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/*-----------------------------------------------------------*/
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vPortEnableVFP:
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/* The FPU enable bits are in the CPACR. */
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ldr.w r0, =0xE000ED88
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ldr r1, [r0]
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/* Enable CP10 and CP11 coprocessors, then save back. */
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orr r1, r1, #( 0xf << 20 )
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str r1, [r0]
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bx r14
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/*-----------------------------------------------------------*/
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xIsPrivileged:
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mrs r0, control /* r0 = CONTROL. */
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tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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ite ne
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movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vResetPrivilege:
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mrs r0, control /* r0 = CONTROL. */
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orr r0, r0, #1 /* r0 = r0 | 1. */
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msr control, r0 /* CONTROL = r0. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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END
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