mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
76be28cdc6
Earlier the System Call entry from an unprivileged task
looked like:
1. SVC for entering system call.
2. System call implementation.
3. SVC for exiting system call.
Now, the system call entry needs to make only one SVC
call and everything else is handled internally.
This PR also makes the following changes:
1. Update the Access Control List (ACL) mechanism to
grant access to all the kernel objects before the
scheduler is started.
2. Add one struct param for system calls with 5 parameters.
This removes the need for special handling for system
calls with 5 parameters.
3. Remove raise privilege SVC when MPU wrapper v2 is used.
4. Add additional run time parameter checks to MPU wrappers
for xTaskGenericNotify and xQueueTakeMutexRecursive APIs.
609 lines
43 KiB
C
609 lines
43 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdint.h>
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
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* is defined correctly and privileged functions are placed in correct sections. */
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#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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/* Portasm includes. */
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#include "portasm.h"
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/* System call numbers includes. */
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#include "mpu_syscall_numbers.h"
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/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
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* header files. */
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#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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#if ( configENABLE_MPU == 1 )
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" program_mpu_first_task: \n"
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" ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
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" str r2, [r1] \n" /* Disable MPU. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r1, [r2] \n" /* Program MAIR0. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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" ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" \n"
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" movs r3, #4 \n" /* r3 = 4. */
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" str r3, [r1] \n" /* Program RNR = 4. */
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" ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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#if ( configTOTAL_MPU_REGIONS == 16 )
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" movs r3, #8 \n" /* r3 = 8. */
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" str r3, [r1] \n" /* Program RNR = 8. */
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" ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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" movs r3, #12 \n" /* r3 = 12. */
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" str r3, [r1] \n" /* Program RNR = 12. */
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" ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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#endif /* configTOTAL_MPU_REGIONS == 16 */
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" \n"
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
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" str r2, [r1] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" restore_context_first_task: \n"
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" ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
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" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
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" \n"
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" restore_special_regs_first_task: \n"
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" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
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" msr psp, r3 \n"
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" msr psplim, r4 \n"
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" msr control, r5 \n"
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" ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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" str r0, [r4] \n" /* Restore xSecureContext. */
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" \n"
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" restore_general_regs_first_task: \n"
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" ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
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" stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
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" ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */
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" \n"
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" restore_context_done_first_task: \n"
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" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
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" mov r0, #0 \n"
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" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
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" bx lr \n"
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" \n"
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" .align 4 \n"
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" pxCurrentTCBConst2: .word pxCurrentTCB \n"
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" xSecureContextConst2: .word xSecureContext \n"
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" xMPUCTRLConst2: .word 0xe000ed94 \n"
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" xMAIR0Const2: .word 0xe000edc0 \n"
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" xRNRConst2: .word 0xe000ed98 \n"
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" xRBARConst2: .word 0xe000ed9c \n"
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);
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}
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#else /* configENABLE_MPU */
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r3, [r2] \n" /* Read pxCurrentTCB. */
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" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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" ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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" ldr r4, xSecureContextConst2 \n"
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" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
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" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
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" movs r1, #2 \n" /* r1 = 2. */
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" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n" /* Discard everything up to r0. */
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" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
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" bx r3 \n" /* Finally, branch to EXC_RETURN. */
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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"xSecureContextConst2: .word xSecureContext \n"
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);
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}
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n" /* r0 = CONTROL. */
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" tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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" ite ne \n"
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" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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" bx lr \n" /* Return. */
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" \n"
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" .align 4 \n"
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::: "r0", "memory"
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);
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}
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/*-----------------------------------------------------------*/
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void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n" /* Read the CONTROL register. */
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" bic r0, #1 \n" /* Clear the bit 0. */
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" msr control, r0 \n" /* Write back the new CONTROL value. */
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" bx lr \n" /* Return to the caller. */
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::: "r0", "memory"
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);
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}
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/*-----------------------------------------------------------*/
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void vResetPrivilege( void ) /* __attribute__ (( naked )) */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n" /* r0 = CONTROL. */
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" orr r0, #1 \n" /* r0 = r0 | 1. */
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" msr control, r0 \n" /* CONTROL = r0. */
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" bx lr \n" /* Return to the caller. */
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::: "r0", "memory"
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);
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}
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/*-----------------------------------------------------------*/
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void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
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" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
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" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
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" cpsie i \n" /* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc %0 \n" /* System call to start the first task. */
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" nop \n"
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" \n"
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" .align 4 \n"
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"xVTORConst: .word 0xe000ed08 \n"
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::"i" ( portSVC_START_SCHEDULER ) : "memory"
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);
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}
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/*-----------------------------------------------------------*/
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uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
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" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" dsb \n"
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" isb \n"
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" bx lr \n" /* Return. */
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::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
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);
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}
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/*-----------------------------------------------------------*/
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void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" msr basepri, r0 \n" /* basepri = ulMask. */
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" dsb \n"
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" isb \n"
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" bx lr \n" /* Return. */
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::: "memory"
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);
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}
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/*-----------------------------------------------------------*/
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#if ( configENABLE_MPU == 1 )
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void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" .extern SecureContext_SaveContext \n"
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" .extern SecureContext_LoadContext \n"
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" \n"
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" ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
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" ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
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" \n"
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" cbz r0, save_ns_context \n" /* No secure context to save. */
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" save_s_context: \n"
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" push {r0-r2, lr} \n"
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" bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
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" pop {r0-r2, lr} \n"
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" \n"
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" save_ns_context: \n"
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" mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
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" lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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" bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
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" \n"
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" save_general_regs: \n"
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" mrs r3, psp \n"
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" \n"
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#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
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" add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */
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" tst lr, #0x10 \n"
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" ittt eq \n"
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" vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */
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" vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
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" vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */
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" sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */
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#endif /* configENABLE_FPU || configENABLE_MVE */
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" \n"
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" stmia r2!, {r4-r11} \n" /* Store r4-r11. */
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" ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
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" stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */
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" \n"
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" save_special_regs: \n"
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" mrs r3, psp \n" /* r3 = PSP. */
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" mrs r4, psplim \n" /* r4 = PSPLIM. */
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" mrs r5, control \n" /* r5 = CONTROL. */
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" stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
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" str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
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" \n"
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" select_next_task: \n"
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" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
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" msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" dsb \n"
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" isb \n"
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" bl vTaskSwitchContext \n"
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" mov r0, #0 \n" /* r0 = 0. */
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" msr basepri, r0 \n" /* Enable interrupts. */
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" \n"
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" program_mpu: \n"
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" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
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" str r2, [r1] \n" /* Disable MPU. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
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" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r1, [r2] \n" /* Program MAIR0. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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" ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" \n"
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" movs r3, #4 \n" /* r3 = 4. */
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" str r3, [r1] \n" /* Program RNR = 4. */
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" ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
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" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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#if ( configTOTAL_MPU_REGIONS == 16 )
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" movs r3, #8 \n" /* r3 = 8. */
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" str r3, [r1] \n" /* Program RNR = 8. */
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" ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
|
|
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
|
|
" movs r3, #12 \n" /* r3 = 12. */
|
|
" str r3, [r1] \n" /* Program RNR = 12. */
|
|
" ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
|
|
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
|
|
#endif /* configTOTAL_MPU_REGIONS == 16 */
|
|
" \n"
|
|
" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
|
|
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
|
|
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
|
|
" str r2, [r1] \n" /* Enable MPU. */
|
|
" dsb \n" /* Force memory writes before continuing. */
|
|
" \n"
|
|
" restore_context: \n"
|
|
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
|
|
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
|
|
" \n"
|
|
" restore_special_regs: \n"
|
|
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
|
|
" msr psp, r3 \n"
|
|
" msr psplim, r4 \n"
|
|
" msr control, r5 \n"
|
|
" ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
|
" str r0, [r4] \n" /* Restore xSecureContext. */
|
|
" cbz r0, restore_ns_context \n" /* No secure context to restore. */
|
|
" \n"
|
|
" restore_s_context: \n"
|
|
" push {r1-r3, lr} \n"
|
|
" bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
|
" pop {r1-r3, lr} \n"
|
|
" \n"
|
|
" restore_ns_context: \n"
|
|
" mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
|
|
" lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
|
" bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
|
|
" \n"
|
|
" restore_general_regs: \n"
|
|
" ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
|
|
" stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
|
|
" ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */
|
|
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
|
|
" tst lr, #0x10 \n"
|
|
" ittt eq \n"
|
|
" vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
|
|
" vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
|
|
" vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */
|
|
#endif /* configENABLE_FPU || configENABLE_MVE */
|
|
" \n"
|
|
" restore_context_done: \n"
|
|
" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
|
|
" bx lr \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
" pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
" xSecureContextConst: .word xSecureContext \n"
|
|
" xMPUCTRLConst: .word 0xe000ed94 \n"
|
|
" xMAIR0Const: .word 0xe000edc0 \n"
|
|
" xRNRConst: .word 0xe000ed98 \n"
|
|
" xRBARConst: .word 0xe000ed9c \n"
|
|
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
|
|
);
|
|
}
|
|
|
|
#else /* configENABLE_MPU */
|
|
|
|
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
|
{
|
|
__asm volatile
|
|
(
|
|
" .syntax unified \n"
|
|
" .extern SecureContext_SaveContext \n"
|
|
" .extern SecureContext_LoadContext \n"
|
|
" \n"
|
|
" ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
|
" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
|
|
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
|
|
" mrs r2, psp \n" /* Read PSP in r2. */
|
|
" \n"
|
|
" cbz r0, save_ns_context \n" /* No secure context to save. */
|
|
" push {r0-r2, r14} \n"
|
|
" bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
|
" pop {r0-r3} \n" /* LR is now in r3. */
|
|
" mov lr, r3 \n" /* LR = r3. */
|
|
" lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
|
" bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
|
" \n"
|
|
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
" ldr r1, [r3] \n" /* Read pxCurrentTCB.*/
|
|
" subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
|
|
" str r2, [r1] \n" /* Save the new top of stack in TCB. */
|
|
" mrs r1, psplim \n" /* r1 = PSPLIM. */
|
|
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
|
|
" stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
|
|
" b select_next_task \n"
|
|
" \n"
|
|
" save_ns_context: \n"
|
|
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
|
|
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
|
|
" tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
|
|
" it eq \n"
|
|
" vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
|
|
#endif /* configENABLE_FPU || configENABLE_MVE */
|
|
" subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
|
|
" str r2, [r1] \n" /* Save the new top of stack in TCB. */
|
|
" adds r2, r2, #12 \n" /* r2 = r2 + 12. */
|
|
" stm r2, {r4-r11} \n" /* Store the registers that are not saved automatically. */
|
|
" mrs r1, psplim \n" /* r1 = PSPLIM. */
|
|
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
|
|
" subs r2, r2, #12 \n" /* r2 = r2 - 12. */
|
|
" stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
|
|
" \n"
|
|
" select_next_task: \n"
|
|
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
|
|
" msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
|
" dsb \n"
|
|
" isb \n"
|
|
" bl vTaskSwitchContext \n"
|
|
" mov r0, #0 \n" /* r0 = 0. */
|
|
" msr basepri, r0 \n" /* Enable interrupts. */
|
|
" \n"
|
|
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
|
|
" ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
|
|
" \n"
|
|
" ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
|
|
" msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
|
|
" mov lr, r4 \n" /* LR = r4. */
|
|
" ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
|
" str r0, [r3] \n" /* Restore the task's xSecureContext. */
|
|
" cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
|
|
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
|
|
" push {r2, r4} \n"
|
|
" bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
|
" pop {r2, r4} \n"
|
|
" mov lr, r4 \n" /* LR = r4. */
|
|
" lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
|
" bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
|
" msr psp, r2 \n" /* Remember the new top of stack for the task. */
|
|
" bx lr \n"
|
|
" \n"
|
|
" restore_ns_context: \n"
|
|
" ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
|
|
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
|
|
" tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
|
|
" it eq \n"
|
|
" vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
|
|
#endif /* configENABLE_FPU || configENABLE_MVE */
|
|
" msr psp, r2 \n" /* Remember the new top of stack for the task. */
|
|
" bx lr \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
"xSecureContextConst: .word xSecureContext \n"
|
|
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
|
|
);
|
|
}
|
|
|
|
#endif /* configENABLE_MPU */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
|
|
|
|
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
|
{
|
|
__asm volatile
|
|
(
|
|
".syntax unified \n"
|
|
".extern vPortSVCHandler_C \n"
|
|
".extern vSystemCallEnter \n"
|
|
".extern vSystemCallExit \n"
|
|
" \n"
|
|
"tst lr, #4 \n"
|
|
"ite eq \n"
|
|
"mrseq r0, msp \n"
|
|
"mrsne r0, psp \n"
|
|
" \n"
|
|
"ldr r1, [r0, #24] \n"
|
|
"ldrb r2, [r1, #-2] \n"
|
|
"cmp r2, %0 \n"
|
|
"blt syscall_enter \n"
|
|
"cmp r2, %1 \n"
|
|
"beq syscall_exit \n"
|
|
"b vPortSVCHandler_C \n"
|
|
" \n"
|
|
"syscall_enter: \n"
|
|
" mov r1, lr \n"
|
|
" b vSystemCallEnter \n"
|
|
" \n"
|
|
"syscall_exit: \n"
|
|
" mov r1, lr \n"
|
|
" b vSystemCallExit \n"
|
|
" \n"
|
|
: /* No outputs. */
|
|
: "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
|
|
: "r0", "r1", "r2", "memory"
|
|
);
|
|
}
|
|
|
|
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
|
|
|
|
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
|
{
|
|
__asm volatile
|
|
(
|
|
" .syntax unified \n"
|
|
" \n"
|
|
" tst lr, #4 \n"
|
|
" ite eq \n"
|
|
" mrseq r0, msp \n"
|
|
" mrsne r0, psp \n"
|
|
" ldr r1, svchandler_address_const \n"
|
|
" bx r1 \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"svchandler_address_const: .word vPortSVCHandler_C \n"
|
|
);
|
|
}
|
|
|
|
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
|
|
{
|
|
__asm volatile
|
|
(
|
|
" .syntax unified \n"
|
|
" \n"
|
|
" svc %0 \n" /* Secure context is allocated in the supervisor call. */
|
|
" bx lr \n" /* Return. */
|
|
::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
|
|
);
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
|
{
|
|
__asm volatile
|
|
(
|
|
" .syntax unified \n"
|
|
" \n"
|
|
" ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */
|
|
" ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */
|
|
" cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
|
|
" it ne \n"
|
|
" svcne %0 \n" /* Secure context is freed in the supervisor call. */
|
|
" bx lr \n" /* Return. */
|
|
::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
|
|
);
|
|
}
|
|
/*-----------------------------------------------------------*/
|