mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-24 15:31:56 -04:00
93 lines
3.7 KiB
XML
93 lines
3.7 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<MemInfo Version="1" Minor="1">
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<Processor Endianness="Little" InstPath="mb_subsystem_i/microblaze_0">
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<AddressSpace Name="mb_subsystem_i_microblaze_0.mb_subsystem_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="65535">
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<BusBlock>
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<BitLane MemType="RAMB36" Placement="X2Y23">
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<DataWidth MSB="7" LSB="6"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X3Y30">
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<DataWidth MSB="5" LSB="4"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y22">
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<DataWidth MSB="3" LSB="2"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X3Y26">
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<DataWidth MSB="1" LSB="0"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X3Y32">
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<DataWidth MSB="15" LSB="14"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X1Y26">
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<DataWidth MSB="13" LSB="12"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X3Y31">
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<DataWidth MSB="11" LSB="10"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y26">
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<DataWidth MSB="9" LSB="8"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y29">
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<DataWidth MSB="23" LSB="22"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y27">
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<DataWidth MSB="21" LSB="20"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X4Y25">
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<DataWidth MSB="19" LSB="18"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y28">
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<DataWidth MSB="17" LSB="16"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y25">
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<DataWidth MSB="31" LSB="30"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X2Y24">
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<DataWidth MSB="29" LSB="28"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X3Y27">
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<DataWidth MSB="27" LSB="26"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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<BitLane MemType="RAMB36" Placement="X3Y29">
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<DataWidth MSB="25" LSB="24"/>
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<AddressRange Begin="0" End="16383"/>
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<Parity ON="false" NumBits="0"/>
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</BitLane>
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</BusBlock>
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</AddressSpace>
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</Processor>
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<Config>
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<Option Name="Part" Val="xc7k325tffg900-2"/>
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</Config>
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</MemInfo>
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