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116 lines
3.9 KiB
C
116 lines
3.9 KiB
C
/*
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* FreeRTOS V202212.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* This file contains the non-portable and therefore RX62N specific parts of
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* the IntQueue standard demo task - namely the configuration of the timers
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* that generate the interrupts and the interrupt entry points.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Demo includes. */
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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/* Hardware specifics. */
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#include "iodefine.h"
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#define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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#define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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void vInitialiseTimerForIntQueueTest( void )
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{
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/* Ensure interrupts do not start until full configuration is complete. */
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portENTER_CRITICAL();
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{
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/* Cascade two 8bit timer channels to generate the interrupts.
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8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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utilised for this test. */
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/* Enable the timers. */
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SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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/* Enable compare match A interrupt request. */
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TMR0.TCR.BIT.CMIEA = 1;
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TMR2.TCR.BIT.CMIEA = 1;
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/* Clear the timer on compare match A. */
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TMR0.TCR.BIT.CCLR = 1;
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TMR2.TCR.BIT.CCLR = 1;
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/* Set the compare match value. */
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TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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/* 16 bit operation ( count from timer 1,2 ). */
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TMR0.TCCR.BIT.CSS = 3;
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TMR2.TCCR.BIT.CSS = 3;
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/* Use PCLK as the input. */
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TMR1.TCCR.BIT.CSS = 1;
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TMR3.TCCR.BIT.CSS = 1;
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/* Divide PCLK by 8. */
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TMR1.TCCR.BIT.CKS = 2;
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TMR3.TCCR.BIT.CKS = 2;
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/* Enable TMR 0, 2 interrupts. */
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IEN( TMR0, CMIA0 ) = 1;
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IEN( TMR2, CMIA2 ) = 1;
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/* Set the timer interrupts to be above the kernel. The interrupts are
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assigned different priorities so they nest with each other. */
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IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );
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}
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portEXIT_CRITICAL();
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/* Ensure the interrupts are clear as they are edge detected. */
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IR( TMR0, CMIA0 ) = 0;
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IR( TMR2, CMIA2 ) = 0;
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}
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/*-----------------------------------------------------------*/
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#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )
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void vT0_1InterruptHandler( void )
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{
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portYIELD_FROM_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )
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void vT2_3InterruptHandler( void )
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{
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portYIELD_FROM_ISR( xSecondTimerHandler() );
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}
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