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FreeRTOS-Kernel/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC
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e14002270 cee9d5c560
Fix qemu riscv build error and miss debug info in assembly code (#838) 
1. add INCLUDE_xTaskGetCurrentTaskHandle for stream_buffer use
2. LDFLAGS add arch and abi info for linker
        for riscv64-unknown-elf multilib, if there is no arch and abi
        info, will link to default lib and have below error
        target emulation `elf32-littleriscv' does not match `elf64-littleriscv'
3. use CFLAGS to replace ASFLAGS when compile assembly code
        because DEBUG flag is added in CFLAGS, if we use ASFLAGS to compile
        assembly code, there is no debug info in assembly code objfile

Signed-off-by: Eric Chan <e14002270@gmail.com>
2022-08-10 15:04:36 +05:30
..
build/gcc Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780) 2022-02-08 13:58:34 -08:00
FreeRTOSConfig.h Fix qemu riscv build error and miss debug info in assembly code (#838) 2022-08-10 15:04:36 +05:30
main.c Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780) 2022-02-08 13:58:34 -08:00
main_blinky.c Extend qemu virt riscv demo (#774) 2022-01-26 17:55:06 -08:00
main_full.c Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780) 2022-02-08 13:58:34 -08:00
ns16550.c Extend qemu virt riscv demo (#774) 2022-01-26 17:55:06 -08:00
ns16550.h Extend qemu virt riscv demo (#774) 2022-01-26 17:55:06 -08:00
Readme.md Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780) 2022-02-08 13:58:34 -08:00
riscv-reg.h Extend qemu virt riscv demo (#774) 2022-01-26 17:55:06 -08:00
riscv-virt.c Extend qemu virt riscv demo (#774) 2022-01-26 17:55:06 -08:00
riscv-virt.h Extend qemu virt riscv demo (#774) 2022-01-26 17:55:06 -08:00
vector.S Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780) 2022-02-08 13:58:34 -08:00

Readme.md

Emulating generic RISC-V 32bit machine on QEMU

Requirements

  1. GNU RISC-V toolchains (tested on pre-built Sifive GNU Embedded Toolchain — v2020.12.8)
  1. qemu-riscv32-system (tested on pre-built Sifive QEMU — v2020.08.1)
  1. Linux OS (tested on Ubuntu 20.04.3 LTS)

How to build

Add path of toolchain that is described above section, such as:

$ export PATH="/YOUR_PATH/riscv64-unknown-elf/bin:${PATH}"

For release build:

$ make -C build/gcc/

For debug build:

$ make -C build/gcc/ DEBUG=1

To clean build artifacts:

$ make -C build/gcc/ clean

If the build was successful, the RTOSDemo.elf executable will be located in the build/gcc/output directory.

How to run

$ qemu-system-riscv32 -nographic -machine virt -net none \
  -chardev stdio,id=con,mux=on -serial chardev:con \
  -mon chardev=con,mode=readline -bios none \
  -smp 4 -kernel ./build/gcc/output/RTOSDemo.elf

How to debug with gdb

Append -s and -S options to the previous qemu command.

  • -s: enable to attach gdb to QEMU at port 1234
  • -S: start and halted CPU (wait for attach from gdb)

It is recommended to use the 'debug build' so that gdb can automatically map symbols. Run these commands after starting the QEMU with above options:

$ riscv64-unknown-elf-gdb -x build/gcc/gdbinit

Description

This demo just prints Tx/Rx message of queue to serial port, use no other hardware and use only primary core (currently hart 0). Other cores are simply going to wfi state and execute nothing else.