FreeRTOS-Kernel/FreeRTOS/Demo/RISC-V-spike-htif_GCC
Paul Bartell 569c78fd8c
Remove coroutines (#874)
* Remove co-routine centric CORTEX_LM3S102_Rowley demos.

Remove CORTEX_LM3S102_Rowley Demo2 and Demo3.
Update Demo1 to no longer use coroutines.

* Remove co-routines from MB91460_Softune demo

* FreeRTOS_96348hs_SK16FX100PMC: Remove co-routine usage.

Remove co-routine usage from FreeRTOS_96348hs_SK16FX100PMC demo.

* MB96350_Softune_Dice_Kit: Remove co-routine usage

Remove co-routines usage from MB96350_Softune_Dice_Kit demo

* AVR_Dx_IAR: Remove co-routine usage

* AVR_Dx_Atmel_Studio: Remove co-routine usage

* PIC24_MPLAB: Remove autogenerated files and add to .gitignore

* PIC24_MPLAB: Remove co-routine usage from demo

* AVR_ATMega323_IAR: Remove co-routine usage

* ColdFire_MCF52221_CodeWarrior: Remove coroutine usage

* AVR_ATMega4809_MPLAB.X: Remove co-routine usage

* AVR_ATMega4809_IAR: Remove co-routine usage

* AVR_ATMega4809_Atmel_Studio: Remove coroutine usage

* AVR_ATMega323_WinAVR: Remove coroutine usage

* AVR_Dx_MPLAB.X: Remove coroutine usage

* dsPIC_MPLAB: Remove coroutine usage

* CORTEX_LM3S102_GCC: Remove coroutines and coroutine centric demos

* CORTEX_LM3S102_GCC: Update makefile to discard unused symbols

Allows fitting in the limited ram/flash for this part.

* CORTEX_LM3S316_IAR: Remove coroutines

* Demos: Remove references to crflash.c, crhook.c, crflash.h, crhook.h

* Remove coroutine options from FreeRTOSConfig.h files

* Xilinx: Remove backup file generated by revup utility

* Demos: Remove Coroutine related config items and references

* Format CBMC FreeRTOSConfig.h

* Update URL from aws.amazon.com/freertos to github.com/FreeRTOS

* Fix copyright year and license text

* Fix license text in demo files

* Update header check excluded path list

* Add configBENCHMARK to lexicon
2022-11-22 10:29:53 +05:30
..
fake_rom.lds Small RISC-V spike demo improvements (#554) 2021-04-08 15:03:10 -07:00
FreeRTOSConfig.h Remove coroutines (#874) 2022-11-22 10:29:53 +05:30
htif.c Add RISC-V demo for the spike simulator. (#532) 2021-04-02 14:17:53 -07:00
htif.h Add RISC-V demo for the spike simulator. (#532) 2021-04-02 14:17:53 -07:00
main.c Set the mtvec register in the Spike demonstraction (#794) 2022-02-17 11:01:50 -08:00
main_blinky.c Apply release changes to main branch (#759) 2021-12-23 10:16:27 -08:00
Makefile Small RISC-V spike demo improvements (#554) 2021-04-08 15:03:10 -07:00
README.md Update spike project ReadMe (#793) 2022-02-18 00:50:40 -08:00
riscv-reg.h Apply release changes to main branch (#759) 2021-12-23 10:16:27 -08:00
riscv-virt.c Apply release changes to main branch (#759) 2021-12-23 10:16:27 -08:00
riscv-virt.h Apply release changes to main branch (#759) 2021-12-23 10:16:27 -08:00
spike-1.cfg Add RISC-V demo for the spike simulator. (#532) 2021-04-02 14:17:53 -07:00
start.S Apply release changes to main branch (#759) 2021-12-23 10:16:27 -08:00

Emulating generic RISC-V 32bit machine on spike

Requirements

  1. GNU RISC-V toolchains (tested on Crosstool-NG)
  2. spike from https://github.com/riscv/riscv-isa-sim
  3. OpenOCD from https://github.com/riscv/riscv-openocd

How to build toolchain

Clone the Crosstool-NG and configure Crosstool-NG.

$ git clone https://github.com/crosstool-ng/crosstool-ng
$ cd crosstool-ng
$ ./bootstrap
$ ./configure --enable-local
$ make

Generate toolchain configuration:

  • For RV32 builds:

    Create a file name as "defconfig" ( should be exactly the same, no file extension ) with the below content:

    CT_EXPERIMENTAL=y
    CT_ARCH_RISCV=y
    CT_ARCH_64=n
    CT_ARCH_ARCH="rv32ima"
    CT_ARCH_ABI="ilp32"
    CT_TARGET_CFLAGS="-mcmodel=medany"
    CT_TARGET_LDFLAGS="-mcmodel=medany"
    CT_MULTILIB=y
    CT_DEBUG_GDB=y
    
  • For RV64 builds: Create a file name as "defconfig" ( should be exactly the same, no file extension ) with the below content:

    CT_EXPERIMENTAL=y
    CT_ARCH_RISCV=y
    CT_ARCH_64=y
    CT_ARCH_ARCH="rv64ima"
    CT_ARCH_ABI="lp64"
    CT_TARGET_CFLAGS="-mcmodel=medany"
    CT_TARGET_LDFLAGS="-mcmodel=medany"
    CT_MULTILIB=y
    CT_DEBUG_GDB=y
    

Run the below command. The configurations will be save to .config file.:

./ct-ng defconfig

Build the GNU toolchain for RISC-V.

$ ./ct-ng build

A toolchain is installed at ~/x-tools/riscv32-unknown-elf or ~/x-tools/riscv64-unknown-elf directory depends on your build.

How to build

Add path of toolchain that is described above section.

$ export PATH=~/x-tools/{YOUR_TOOLCHAIN}/bin:$PATH

To build, simply run make. If you want a debug build, pass DEBUG=1. If you want an RV64 build, pass XLEN=64.

The resulting executable file is ./build/RTOSDemo32.axf or ./build/RTOSDemo64.axf.

How to run

RV32:

$ spike -p1 --isa RV32IMA -m0x80000000:0x10000000 --rbb-port 9824 \
        ./build/RTOSDemo32.axf

RV64:

$ spike -p1 --isa RV64IMA -m0x80000000:0x10000000 --rbb-port 9824 \
        ./build/RTOSDemo64.axf

How to debug with gdb

Start OpenOCD in one terminal:

$ openocd -f spike-1.cfg

Start gdb in another:

$ riscv64-unknown-elf-gdb ./build/RTOSDemo.axf
...
(gdb) target extended-remote localhost:3333
...
(gdb) info threads

(As of 3/22/2021 OpenOCD's RISC-V FreeRTOS awareness is still incomplete.)

Description

This demo starts separate transmit and receive threads. The transmit thread sends integers through a queue. Both threads print out what they're sending/receiving using HTIF.