FreeRTOS-Kernel/FreeRTOS/Demo/RISC-V-spike-htif_GCC
Kody Stribrny 7d09b88e5a
Fix C source and header file license spacing (#1155)
The line 'Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.'
used to have two spaces between the first and second sentences.
This would cause the header check to fail due to the copyright regex located
ab999f9624/.github/scripts/core_checker.py (L396)
2024-01-12 16:43:31 -08:00
..
fake_rom.lds risc-v: Fix build flags and linker scripts (#906) 2023-05-31 11:48:13 -07:00
FreeRTOSConfig.h Fix C source and header file license spacing (#1155) 2024-01-12 16:43:31 -08:00
htif.c Add RISC-V demo for the spike simulator. (#532) 2021-04-02 14:17:53 -07:00
htif.h Add RISC-V demo for the spike simulator. (#532) 2021-04-02 14:17:53 -07:00
main.c Fix formatting in kernel demo application files (#1148) 2024-01-02 11:05:59 +05:30
main_blinky.c Fix formatting in kernel demo application files (#1148) 2024-01-02 11:05:59 +05:30
Makefile risc-v: Fix build flags and linker scripts (#906) 2023-05-31 11:48:13 -07:00
README.md Update spike project ReadMe (#793) 2022-02-18 00:50:40 -08:00
riscv-reg.h Fix C source and header file license spacing (#1155) 2024-01-12 16:43:31 -08:00
riscv-virt.c Fix C source and header file license spacing (#1155) 2024-01-12 16:43:31 -08:00
riscv-virt.h Fix C source and header file license spacing (#1155) 2024-01-12 16:43:31 -08:00
spike-1.cfg Add RISC-V demo for the spike simulator. (#532) 2021-04-02 14:17:53 -07:00
start.S [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00

Emulating generic RISC-V 32bit machine on spike

Requirements

  1. GNU RISC-V toolchains (tested on Crosstool-NG)
  2. spike from https://github.com/riscv/riscv-isa-sim
  3. OpenOCD from https://github.com/riscv/riscv-openocd

How to build toolchain

Clone the Crosstool-NG and configure Crosstool-NG.

$ git clone https://github.com/crosstool-ng/crosstool-ng
$ cd crosstool-ng
$ ./bootstrap
$ ./configure --enable-local
$ make

Generate toolchain configuration:

  • For RV32 builds:

    Create a file name as "defconfig" ( should be exactly the same, no file extension ) with the below content:

    CT_EXPERIMENTAL=y
    CT_ARCH_RISCV=y
    CT_ARCH_64=n
    CT_ARCH_ARCH="rv32ima"
    CT_ARCH_ABI="ilp32"
    CT_TARGET_CFLAGS="-mcmodel=medany"
    CT_TARGET_LDFLAGS="-mcmodel=medany"
    CT_MULTILIB=y
    CT_DEBUG_GDB=y
    
  • For RV64 builds: Create a file name as "defconfig" ( should be exactly the same, no file extension ) with the below content:

    CT_EXPERIMENTAL=y
    CT_ARCH_RISCV=y
    CT_ARCH_64=y
    CT_ARCH_ARCH="rv64ima"
    CT_ARCH_ABI="lp64"
    CT_TARGET_CFLAGS="-mcmodel=medany"
    CT_TARGET_LDFLAGS="-mcmodel=medany"
    CT_MULTILIB=y
    CT_DEBUG_GDB=y
    

Run the below command. The configurations will be save to .config file.:

./ct-ng defconfig

Build the GNU toolchain for RISC-V.

$ ./ct-ng build

A toolchain is installed at ~/x-tools/riscv32-unknown-elf or ~/x-tools/riscv64-unknown-elf directory depends on your build.

How to build

Add path of toolchain that is described above section.

$ export PATH=~/x-tools/{YOUR_TOOLCHAIN}/bin:$PATH

To build, simply run make. If you want a debug build, pass DEBUG=1. If you want an RV64 build, pass XLEN=64.

The resulting executable file is ./build/RTOSDemo32.axf or ./build/RTOSDemo64.axf.

How to run

RV32:

$ spike -p1 --isa RV32IMA -m0x80000000:0x10000000 --rbb-port 9824 \
        ./build/RTOSDemo32.axf

RV64:

$ spike -p1 --isa RV64IMA -m0x80000000:0x10000000 --rbb-port 9824 \
        ./build/RTOSDemo64.axf

How to debug with gdb

Start OpenOCD in one terminal:

$ openocd -f spike-1.cfg

Start gdb in another:

$ riscv64-unknown-elf-gdb ./build/RTOSDemo.axf
...
(gdb) target extended-remote localhost:3333
...
(gdb) info threads

(As of 3/22/2021 OpenOCD's RISC-V FreeRTOS awareness is still incomplete.)

Description

This demo starts separate transmit and receive threads. The transmit thread sends integers through a queue. Both threads print out what they're sending/receiving using HTIF.