mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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376 lines
11 KiB
C
376 lines
11 KiB
C
/* --COPYRIGHT--,BSD
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* Copyright (c) 2014, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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//*****************************************************************************
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//
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// aes256.c - Driver for the aes256 Module.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup aes256_api aes256
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_regaccess.h"
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#include "inc/hw_memmap.h"
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#ifdef __MSP430_HAS_AES256__
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#include "aes256.h"
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#include <assert.h>
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uint8_t AES256_setCipherKey(uint16_t baseAddress,
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const uint8_t * cipherKey,
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uint16_t keyLength)
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{
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uint8_t i;
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uint16_t sCipherKey;
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HWREG16(baseAddress + OFS_AESACTL0) &= (~(AESKL_1 + AESKL_2));
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switch(keyLength)
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{
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case AES256_KEYLENGTH_128BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128;
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break;
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case AES256_KEYLENGTH_192BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192;
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break;
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case AES256_KEYLENGTH_256BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256;
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break;
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default:
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return(STATUS_FAIL);
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}
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keyLength = keyLength / 8;
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for(i = 0; i < keyLength; i = i + 2)
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{
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sCipherKey = (uint16_t)(cipherKey[i]);
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sCipherKey = sCipherKey | ((uint16_t)(cipherKey[i + 1]) << 8);
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HWREG16(baseAddress + OFS_AESAKEY) = sCipherKey;
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}
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// Wait until key is written
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while(0x00 == (HWREG16(baseAddress + OFS_AESASTAT) & AESKEYWR))
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{
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;
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}
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return(STATUS_SUCCESS);
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}
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void AES256_encryptData(uint16_t baseAddress,
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const uint8_t * data,
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uint8_t * encryptedData)
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{
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uint8_t i;
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uint16_t tempData = 0;
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uint16_t tempVariable = 0;
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// Set module to encrypt mode
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HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3;
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// Write data to encrypt to module
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for(i = 0; i < 16; i = i + 2)
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{
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tempVariable = (uint16_t)(data[i]);
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tempVariable = tempVariable | ((uint16_t)(data[i + 1]) << 8);
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HWREG16(baseAddress + OFS_AESADIN) = tempVariable;
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}
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// Key that is already written shall be used
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// Encryption is initialized by setting AESKEYWR to 1
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HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;
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// Wait unit finished ~167 MCLK
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while(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY))
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{
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;
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}
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// Write encrypted data back to variable
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for(i = 0; i < 16; i = i + 2)
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{
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tempData = HWREG16(baseAddress + OFS_AESADOUT);
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*(encryptedData + i) = (uint8_t)tempData;
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*(encryptedData + i + 1) = (uint8_t)(tempData >> 8);
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}
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}
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void AES256_decryptData(uint16_t baseAddress,
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const uint8_t * data,
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uint8_t * decryptedData)
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{
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uint8_t i;
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uint16_t tempData = 0;
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uint16_t tempVariable = 0;
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// Set module to decrypt mode
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HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3);
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// Write data to decrypt to module
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for(i = 0; i < 16; i = i + 2)
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{
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tempVariable = (uint16_t)(data[i + 1] << 8);
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tempVariable = tempVariable | ((uint16_t)(data[i]));
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HWREG16(baseAddress + OFS_AESADIN) = tempVariable;
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}
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// Key that is already written shall be used
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// Now decryption starts
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HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;
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// Wait unit finished ~167 MCLK
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while(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY))
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{
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;
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}
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// Write encrypted data back to variable
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for(i = 0; i < 16; i = i + 2)
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{
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tempData = HWREG16(baseAddress + OFS_AESADOUT);
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*(decryptedData + i) = (uint8_t)tempData;
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*(decryptedData + i + 1) = (uint8_t)(tempData >> 8);
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}
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}
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uint8_t AES256_setDecipherKey(uint16_t baseAddress,
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const uint8_t * cipherKey,
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uint16_t keyLength)
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{
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uint8_t i;
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uint16_t tempVariable = 0;
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// Set module to decrypt mode
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HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0);
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HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1;
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switch(keyLength)
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{
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case AES256_KEYLENGTH_128BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128;
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break;
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case AES256_KEYLENGTH_192BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192;
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break;
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case AES256_KEYLENGTH_256BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256;
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break;
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default:
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return(STATUS_FAIL);
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}
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keyLength = keyLength / 8;
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// Write cipher key to key register
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for(i = 0; i < keyLength; i = i + 2)
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{
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tempVariable = (uint16_t)(cipherKey[i]);
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tempVariable = tempVariable | ((uint16_t)(cipherKey[i + 1]) << 8);
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HWREG16(baseAddress + OFS_AESAKEY) = tempVariable;
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}
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// Wait until key is processed ~52 MCLK
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while((HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) == AESBUSY)
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{
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;
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}
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return(STATUS_SUCCESS);
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}
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void AES256_clearInterrupt(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_AESACTL0) &= ~AESRDYIFG;
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}
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uint32_t AES256_getInterruptStatus(uint16_t baseAddress)
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{
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return ((HWREG16(baseAddress + OFS_AESACTL0) & AESRDYIFG) << 0x04);
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}
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void AES256_enableInterrupt(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_AESACTL0) |= AESRDYIE;
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}
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void AES256_disableInterrupt(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_AESACTL0) &= ~AESRDYIE;
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}
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void AES256_reset(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_AESACTL0) |= AESSWRST;
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}
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void AES256_startEncryptData(uint16_t baseAddress,
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const uint8_t * data)
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{
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uint8_t i;
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uint16_t tempVariable = 0;
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// Set module to encrypt mode
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HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3;
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// Write data to encrypt to module
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for(i = 0; i < 16; i = i + 2)
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{
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tempVariable = (uint16_t)(data[i]);
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tempVariable = tempVariable | ((uint16_t)(data[i + 1 ]) << 8);
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HWREG16(baseAddress + OFS_AESADIN) = tempVariable;
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}
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// Key that is already written shall be used
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// Encryption is initialized by setting AESKEYWR to 1
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HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;
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}
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void AES256_startDecryptData(uint16_t baseAddress,
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const uint8_t * data)
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{
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uint8_t i;
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uint16_t tempVariable = 0;
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// Set module to decrypt mode
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HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3);
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// Write data to decrypt to module
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for(i = 0; i < 16; i = i + 2)
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{
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tempVariable = (uint16_t)(data[i + 1] << 8);
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tempVariable = tempVariable | ((uint16_t)(data[i]));
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HWREG16(baseAddress + OFS_AESADIN) = tempVariable;
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}
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// Key that is already written shall be used
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// Now decryption starts
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HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR;
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}
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uint8_t AES256_startSetDecipherKey(uint16_t baseAddress,
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const uint8_t * cipherKey,
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uint16_t keyLength)
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{
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uint8_t i;
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uint16_t tempVariable = 0;
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HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0);
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HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1;
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switch(keyLength)
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{
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case AES256_KEYLENGTH_128BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128;
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break;
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case AES256_KEYLENGTH_192BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192;
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break;
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case AES256_KEYLENGTH_256BIT:
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HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256;
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break;
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default:
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return(STATUS_FAIL);
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}
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keyLength = keyLength / 8;
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// Write cipher key to key register
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for(i = 0; i < keyLength; i = i + 2)
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{
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tempVariable = (uint16_t)(cipherKey[i]);
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tempVariable = tempVariable | ((uint16_t)(cipherKey[i + 1]) << 8);
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HWREG16(baseAddress + OFS_AESAKEY) = tempVariable;
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}
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return(STATUS_SUCCESS);
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}
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uint8_t AES256_getDataOut(uint16_t baseAddress,
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uint8_t *outputData)
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{
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uint8_t i;
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uint16_t tempData = 0;
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// If module is busy, exit and return failure
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if(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY))
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{
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return(STATUS_FAIL);
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}
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// Write encrypted data back to variable
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for(i = 0; i < 16; i = i + 2)
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{
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tempData = HWREG16(baseAddress + OFS_AESADOUT);
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*(outputData + i) = (uint8_t)tempData;
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*(outputData + i + 1) = (uint8_t)(tempData >> 8);
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}
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return(STATUS_SUCCESS);
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}
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uint16_t AES256_isBusy(uint16_t baseAddress)
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{
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return (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY);
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}
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void AES256_clearErrorFlag(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_AESACTL0) &= ~AESERRFG;
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}
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uint32_t AES256_getErrorFlagStatus(uint16_t baseAddress)
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{
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return (HWREG16(baseAddress + OFS_AESACTL0) & AESERRFG);
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}
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#endif
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//*****************************************************************************
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//
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//! Close the doxygen group for aes256_api
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//! @}
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//
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//*****************************************************************************
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