mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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291 lines
11 KiB
C
291 lines
11 KiB
C
/* --COPYRIGHT--,BSD
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* Copyright (c) 2014, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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//*****************************************************************************
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//
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// adc12_b.c - Driver for the adc12_b Module.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup adc12_b_api adc12_b
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_regaccess.h"
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#include "inc/hw_memmap.h"
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#ifdef __MSP430_HAS_ADC12_B__
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#include "adc12_b.h"
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#include <assert.h>
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bool ADC12_B_init(uint16_t baseAddress,
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ADC12_B_initParam *param)
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{
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//Make sure the ENC bit is cleared before initializing the ADC12
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HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;
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bool retVal = STATUS_SUCCESS;
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//Turn OFF ADC12B Module & Clear Interrupt Registers
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HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12ENC + ADC12SC);
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HWREG16(baseAddress + OFS_ADC12IER0) &= 0x0000; //Reset ALL interrupt enables
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HWREG16(baseAddress + OFS_ADC12IER1) &= 0x0000;
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HWREG16(baseAddress + OFS_ADC12IER2) &= 0x0000;
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HWREG16(baseAddress + OFS_ADC12IFGR0) &= 0x0000; //Reset ALL interrupt flags
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HWREG16(baseAddress + OFS_ADC12IFGR1) &= 0x0000;
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HWREG16(baseAddress + OFS_ADC12IFGR2) &= 0x0000;
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//Set ADC12B Control 1
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HWREG16(baseAddress + OFS_ADC12CTL1) =
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param->sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source
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+ (param->clockSourceDivider & ADC12DIV_7) //Set Clock Divider
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+ (param->clockSourcePredivider & ADC12PDIV__64)
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+ param->clockSourceSelect; //Setup Clock Source
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//Set ADC12B Control 2
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HWREG16(baseAddress + OFS_ADC12CTL2) =
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ADC12RES_2; //Default resolution to 12-bits
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//Set ADC12B Control 3
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HWREG16(baseAddress + OFS_ADC12CTL3) =
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param->internalChannelMap; // Map internal channels
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return (retVal);
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}
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void ADC12_B_enable(uint16_t baseAddress)
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{
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// Clear ENC bit
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HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;
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//Enable the ADC12B Module
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HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ON;
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}
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void ADC12_B_disable(uint16_t baseAddress)
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{
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// Clear ENC bit
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HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;
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//Disable ADC12B module
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HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ON;
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}
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void ADC12_B_setupSamplingTimer(uint16_t baseAddress,
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uint16_t clockCycleHoldCountLowMem,
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uint16_t clockCycleHoldCountHighMem,
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uint16_t multipleSamplesEnabled)
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{
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HWREG16(baseAddress + OFS_ADC12CTL1) |= ADC12SHP;
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//Reset clock cycle hold counts and msc bit before setting them
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HWREG16(baseAddress + OFS_ADC12CTL0) &=
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~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC);
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//Set clock cycle hold counts and msc bit
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HWREG16(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem
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+ (clockCycleHoldCountHighMem << 4)
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+ multipleSamplesEnabled;
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}
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void ADC12_B_disableSamplingTimer(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP);
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}
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void ADC12_B_configureMemory(uint16_t baseAddress,
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ADC12_B_configureMemoryParam *param)
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{
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//Set the offset in respect to ADC12MCTL0
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uint16_t memoryBufferControlOffset =
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(OFS_ADC12MCTL0 + param->memoryBufferControlIndex);
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//Reset the memory buffer control and Set the input source
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HWREG16(baseAddress + memoryBufferControlOffset) =
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param->inputSourceSelect //Set Input Source
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+ param->refVoltageSourceSelect //Set Vref+/-
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+ param->endOfSequence; //Set End of Sequence
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HWREG16(baseAddress + memoryBufferControlOffset)
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&= ~(ADC12WINC);
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HWREG16(baseAddress + memoryBufferControlOffset)
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|= param->windowComparatorSelect;
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//(OFS_ADC12MCTL0_H + memoryIndex) == offset of OFS_ADC12MCTLX_H
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HWREG16(baseAddress + memoryBufferControlOffset)
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&= ~(ADC12DIF);
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HWREG16(baseAddress + memoryBufferControlOffset)
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|= param->differentialModeSelect;
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//(OFS_ADC12MCTL0_H + memoryIndex) == offset of OFS_ADC12MCTLX_H
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}
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void ADC12_B_setWindowCompAdvanced(uint16_t baseAddress,
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uint16_t highThreshold,
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uint16_t lowThreshold)
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{
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HWREG16(baseAddress + OFS_ADC12HI) = highThreshold;
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HWREG16(baseAddress + OFS_ADC12LO) = lowThreshold;
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}
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void ADC12_B_enableInterrupt(uint16_t baseAddress,
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uint16_t interruptMask0,
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uint16_t interruptMask1,
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uint16_t interruptMask2)
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{
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HWREG16(baseAddress + OFS_ADC12IER0) |= interruptMask0;
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HWREG16(baseAddress + OFS_ADC12IER1) |= interruptMask1;
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HWREG16(baseAddress + OFS_ADC12IER2) |= interruptMask2;
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}
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void ADC12_B_disableInterrupt(uint16_t baseAddress,
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uint16_t interruptMask0,
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uint16_t interruptMask1,
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uint16_t interruptMask2)
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{
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HWREG16(baseAddress + OFS_ADC12IER0) &= ~(interruptMask0);
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HWREG16(baseAddress + OFS_ADC12IER1) &= ~(interruptMask1);
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HWREG16(baseAddress + OFS_ADC12IER2) &= ~(interruptMask2);
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}
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void ADC12_B_clearInterrupt(uint16_t baseAddress,
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uint8_t interruptRegisterChoice,
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uint16_t memoryInterruptFlagMask)
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{
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HWREG16(baseAddress + OFS_ADC12IFGR0 + 2 * interruptRegisterChoice) &=
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~(memoryInterruptFlagMask);
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}
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uint16_t ADC12_B_getInterruptStatus(uint16_t baseAddress,
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uint8_t interruptRegisterChoice,
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uint16_t memoryInterruptFlagMask)
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{
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return (HWREG16(baseAddress + OFS_ADC12IFGR0 + 2 * interruptRegisterChoice)
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& memoryInterruptFlagMask);
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}
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void ADC12_B_startConversion(uint16_t baseAddress,
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uint16_t startingMemoryBufferIndex,
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uint8_t conversionSequenceModeSelect)
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{
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//Reset the ENC bit to set the starting memory address and conversion mode
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//sequence
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HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);
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//Reset the bits about to be set
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HWREG16(baseAddress + OFS_ADC12CTL3) &= ~(ADC12CSTARTADD_31);
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HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12CONSEQ_3);
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HWREG16(baseAddress + OFS_ADC12CTL3) |= startingMemoryBufferIndex;
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HWREG16(baseAddress + OFS_ADC12CTL1) |= conversionSequenceModeSelect;
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HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC;
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}
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void ADC12_B_disableConversions(uint16_t baseAddress,
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bool preempt)
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{
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if(ADC12_B_PREEMPTCONVERSION == preempt)
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{
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HWREG8(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3);
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//Reset conversion sequence mode to single-channel, single-conversion
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}
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else if(~(HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3))
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{
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//To prevent preemption of a single-channel, single-conversion we must
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//wait for the ADC core to finish the conversion.
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while(ADC12_B_isBusy(baseAddress))
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{
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;
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}
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}
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HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);
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}
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uint16_t ADC12_B_getResults(uint16_t baseAddress,
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uint8_t memoryBufferIndex)
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{
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return (HWREG16(baseAddress + (OFS_ADC12MEM0 + memoryBufferIndex)));
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//(0x60 + memoryBufferIndex) == offset of ADC12MEMx
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}
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void ADC12_B_setResolution(uint16_t baseAddress,
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uint8_t resolutionSelect)
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{
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HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3);
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HWREG8(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect;
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}
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void ADC12_B_setSampleHoldSignalInversion(uint16_t baseAddress,
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uint16_t invertedSignal)
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{
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HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH);
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HWREG16(baseAddress + OFS_ADC12CTL1) |= invertedSignal;
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}
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void ADC12_B_setDataReadBackFormat(uint16_t baseAddress,
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uint8_t readBackFormat)
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{
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HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF);
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HWREG8(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat;
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}
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void ADC12_B_setAdcPowerMode(uint16_t baseAddress,
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uint8_t powerMode)
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{
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HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12PWRMD);
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HWREG8(baseAddress + OFS_ADC12CTL2_L) |= powerMode;
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}
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uint32_t ADC12_B_getMemoryAddressForDMA(uint16_t baseAddress,
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uint8_t memoryIndex)
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{
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return (baseAddress + (OFS_ADC12MEM0 + memoryIndex));
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//(0x60 + memoryIndex) == offset of ADC12MEMx
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}
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uint8_t ADC12_B_isBusy(uint16_t baseAddress)
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{
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return (HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY);
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}
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#endif
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//*****************************************************************************
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//
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//! Close the doxygen group for adc12_b_api
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//! @}
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//
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//*****************************************************************************
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