mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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597 lines
16 KiB
C
597 lines
16 KiB
C
/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* @file encodings.h
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* @author Microsemi SoC Products Group
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* @brief Mi-V soft processor register bit mask and shift constants encodings.
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*
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* SVN $Revision: 9825 $
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* SVN $Date: 2018-03-19 10:31:41 +0530 (Mon, 19 Mar 2018) $
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*/
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#ifndef RISCV_CSR_ENCODING_H
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#define RISCV_CSR_ENCODING_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_HIE 0x00000004
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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#define MSTATUS_SPIE 0x00000020
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#define MSTATUS_HPIE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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#define MSTATUS_SPP 0x00000100
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#define MSTATUS_HPP 0x00000600
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#define MSTATUS_MPP 0x00001800
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_SUM 0x00040000 /*changed in v1.10*/
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#define MSTATUS_MXR 0x00080000 /*changed in v1.10*/
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#define MSTATUS_TVM 0x00100000 /*changed in v1.10*/
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#define MSTATUS_TW 0x00200000 /*changed in v1.10*/
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#define MSTATUS_TSR 0x00400000 /*changed in v1.10*/
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#define MSTATUS_RES 0x7F800000 /*changed in v1.10*/
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000
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#define MCAUSE32_CAUSE 0x7FFFFFFF
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#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
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#define MCAUSE32_INT 0x80000000
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#define MCAUSE64_INT 0x8000000000000000
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_PUM 0x00040000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000
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#define MIP_SSIP (1u << IRQ_S_SOFT)
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#define MIP_HSIP (1u << IRQ_H_SOFT)
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#define MIP_MSIP (1u << IRQ_M_SOFT)
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#define MIP_STIP (1u << IRQ_S_TIMER)
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#define MIP_HTIP (1u << IRQ_H_TIMER)
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#define MIP_MTIP (1u << IRQ_M_TIMER)
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#define MIP_SEIP (1u << IRQ_S_EXT)
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#define MIP_HEIP (1u << IRQ_H_EXT)
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#define MIP_MEIP (1u << IRQ_M_EXT)
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define VM_MBARE 0
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#define VM_MBB 1
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#define VM_MBBID 2
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#define VM_SV32 8
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#define VM_SV39 9
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#define VM_SV48 10
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define DEFAULT_RSTVEC 0x00001000
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#define DEFAULT_NMIVEC 0x00001004
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#define DEFAULT_MTVEC 0x00001010
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#define CONFIG_STRING_ADDR 0x0000100C
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#define EXT_IO_BASE 0x40000000
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#define DRAM_BASE 0x80000000
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/* page table entry (PTE) fields */
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#define PTE_V 0x001 /* Valid */
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#define PTE_TYPE 0x01E /* Type */
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#define PTE_R 0x020 /* Referenced */
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#define PTE_D 0x040 /* Dirty */
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#define PTE_SOFT 0x380 /* Reserved for Software */
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#define PTE_TYPE_TABLE 0x00
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#define PTE_TYPE_TABLE_GLOBAL 0x02
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#define PTE_TYPE_URX_SR 0x04
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#define PTE_TYPE_URWX_SRW 0x06
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#define PTE_TYPE_UR_SR 0x08
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#define PTE_TYPE_URW_SRW 0x0A
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#define PTE_TYPE_URX_SRX 0x0C
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#define PTE_TYPE_URWX_SRWX 0x0E
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#define PTE_TYPE_SR 0x10
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#define PTE_TYPE_SRW 0x12
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#define PTE_TYPE_SRX 0x14
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#define PTE_TYPE_SRWX 0x16
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#define PTE_TYPE_SR_GLOBAL 0x18
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#define PTE_TYPE_SRW_GLOBAL 0x1A
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#define PTE_TYPE_SRX_GLOBAL 0x1C
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#define PTE_TYPE_SRWX_GLOBAL 0x1E
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#define PTE_PPN_SHIFT 10
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#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
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#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
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#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
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((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
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(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
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#ifdef __riscv
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#if __riscv_xlen == 64
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define MCAUSE_INT MCAUSE64_INT
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# define MCAUSE_CAUSE MCAUSE64_CAUSE
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# define RISCV_PGLEVEL_BITS 9
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#else
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# define MSTATUS_SD MSTATUS32_SD
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# define SSTATUS_SD SSTATUS32_SD
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# define RISCV_PGLEVEL_BITS 10
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# define MCAUSE_INT MCAUSE32_INT
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# define MCAUSE_CAUSE MCAUSE32_CAUSE
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#endif
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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#ifndef __ASSEMBLER__
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#ifdef __GNUC__
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#define read_csr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define write_csr(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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#define swap_csr(reg, val) ({ unsigned long __tmp; \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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else \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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__tmp; })
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#define set_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define clear_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define rdtime() read_csr(time)
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#define rdcycle() read_csr(cycle)
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#define rdinstret() read_csr(instret)
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#ifdef __riscv_atomic
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#define MASK(nr) (1UL << nr)
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#define MASK_NOT(nr) (~(1UL << nr))
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/**
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* atomic_read - read atomic variable
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* @v: pointer of type int
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*
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* Atomically reads the value of @v.
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*/
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static inline int atomic_read(const int *v)
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{
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return *((volatile int *)(v));
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}
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/**
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* atomic_set - set atomic variable
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* @v: pointer of type int
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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static inline void atomic_set(int *v, int i)
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{
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*v = i;
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}
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/**
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* atomic_add - add integer to atomic variable
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* @i: integer value to add
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* @v: pointer of type int
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*
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* Atomically adds @i to @v.
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*/
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static inline void atomic_add(int i, int *v)
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{
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__asm__ __volatile__ (
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"amoadd.w zero, %1, %0"
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: "+A" (*v)
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: "r" (i));
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}
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static inline int atomic_fetch_add(unsigned int mask, int *v)
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{
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int out;
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__asm__ __volatile__ (
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"amoadd.w %2, %1, %0"
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: "+A" (*v), "=r" (out)
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: "r" (mask));
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return out;
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}
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/**
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* atomic_sub - subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type int
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*
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* Atomically subtracts @i from @v.
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*/
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static inline void atomic_sub(int i, int *v)
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{
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atomic_add(-i, v);
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}
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static inline int atomic_fetch_sub(unsigned int mask, int *v)
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{
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int out;
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__asm__ __volatile__ (
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"amosub.w %2, %1, %0"
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: "+A" (*v), "=r" (out)
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: "r" (mask));
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return out;
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}
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/**
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* atomic_add_return - add integer to atomic variable
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* @i: integer value to add
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* @v: pointer of type int
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*
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* Atomically adds @i to @v and returns the result
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*/
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static inline int atomic_add_return(int i, int *v)
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{
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register int c;
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__asm__ __volatile__ (
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"amoadd.w %0, %2, %1"
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: "=r" (c), "+A" (*v)
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: "r" (i));
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return (c + i);
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}
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/**
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* atomic_sub_return - subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type int
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*
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* Atomically subtracts @i from @v and returns the result
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*/
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static inline int atomic_sub_return(int i, int *v)
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{
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return atomic_add_return(-i, v);
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}
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/**
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* atomic_inc - increment atomic variable
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* @v: pointer of type int
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*
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* Atomically increments @v by 1.
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*/
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static inline void atomic_inc(int *v)
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{
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atomic_add(1, v);
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}
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/**
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* atomic_dec - decrement atomic variable
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* @v: pointer of type int
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*
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* Atomically decrements @v by 1.
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*/
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static inline void atomic_dec(int *v)
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{
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atomic_add(-1, v);
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}
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static inline int atomic_inc_return(int *v)
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{
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return atomic_add_return(1, v);
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}
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static inline int atomic_dec_return(int *v)
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{
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return atomic_sub_return(1, v);
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}
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/**
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* atomic_sub_and_test - subtract value from variable and test result
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* @i: integer value to subtract
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* @v: pointer of type int
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*
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* Atomically subtracts @i from @v and returns
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* true if the result is zero, or false for all
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* other cases.
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*/
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static inline int atomic_sub_and_test(int i, int *v)
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{
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return (atomic_sub_return(i, v) == 0);
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}
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/**
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* atomic_inc_and_test - increment and test
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* @v: pointer of type int
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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static inline int atomic_inc_and_test(int *v)
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{
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return (atomic_inc_return(v) == 0);
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}
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/**
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* atomic_dec_and_test - decrement and test
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* @v: pointer of type int
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*
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* Atomically decrements @v by 1 and
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* returns true if the result is 0, or false for all other
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* cases.
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*/
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static inline int atomic_dec_and_test(int *v)
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{
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return (atomic_dec_return(v) == 0);
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}
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/**
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* atomic_add_negative - add and test if negative
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* @i: integer value to add
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* @v: pointer of type int
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*
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* Atomically adds @i to @v and returns true
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* if the result is negative, or false when
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* result is greater than or equal to zero.
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*/
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static inline int atomic_add_negative(int i, int *v)
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{
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return (atomic_add_return(i, v) < 0);
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}
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static inline int atomic_xchg(int *v, int n)
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{
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register int c;
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__asm__ __volatile__ (
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"amoswap.w %0, %2, %1"
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: "=r" (c), "+A" (*v)
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: "r" (n));
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return c;
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}
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/**
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* atomic_and - Atomically clear bits in atomic variable
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* @mask: Mask of the bits to be retained
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* @v: pointer of type int
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*
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* Atomically retains the bits set in @mask from @v
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*/
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static inline void atomic_and(unsigned int mask, int *v)
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{
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__asm__ __volatile__ (
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"amoand.w zero, %1, %0"
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: "+A" (*v)
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: "r" (mask));
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}
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static inline int atomic_fetch_and(unsigned int mask, int *v)
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{
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int out;
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__asm__ __volatile__ (
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"amoand.w %2, %1, %0"
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: "+A" (*v), "=r" (out)
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: "r" (mask));
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return out;
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}
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/**
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* atomic_or - Atomically set bits in atomic variable
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* @mask: Mask of the bits to be set
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* @v: pointer of type int
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*
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* Atomically sets the bits set in @mask in @v
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*/
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static inline void atomic_or(unsigned int mask, int *v)
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{
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__asm__ __volatile__ (
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"amoor.w zero, %1, %0"
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: "+A" (*v)
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: "r" (mask));
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}
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static inline int atomic_fetch_or(unsigned int mask, int *v)
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{
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int out;
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__asm__ __volatile__ (
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"amoor.w %2, %1, %0"
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: "+A" (*v), "=r" (out)
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: "r" (mask));
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return out;
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}
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/**
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* atomic_xor - Atomically flips bits in atomic variable
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* @mask: Mask of the bits to be flipped
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* @v: pointer of type int
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*
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* Atomically flips the bits set in @mask in @v
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*/
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static inline void atomic_xor(unsigned int mask, int *v)
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{
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__asm__ __volatile__ (
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"amoxor.w zero, %1, %0"
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: "+A" (*v)
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: "r" (mask));
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}
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static inline int atomic_fetch_xor(unsigned int mask, int *v)
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{
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int out;
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__asm__ __volatile__ (
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"amoxor.w %2, %1, %0"
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: "+A" (*v), "=r" (out)
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: "r" (mask));
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return out;
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}
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/*----------------------------------------------------*/
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long __res, __mask;
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__mask = MASK(nr);
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__asm__ __volatile__ ( \
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"amoor.w %0, %2, %1" \
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: "=r" (__res), "+A" (*addr) \
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: "r" (__mask)); \
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return ((__res & __mask) != 0);
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
|
|
*/
|
|
static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
|
|
{
|
|
unsigned long __res, __mask;
|
|
__mask = MASK_NOT(nr);
|
|
__asm__ __volatile__ ( \
|
|
"amoand.w %0, %2, %1" \
|
|
: "=r" (__res), "+A" (*addr) \
|
|
: "r" (__mask)); \
|
|
|
|
return ((__res & __mask) != 0);
|
|
}
|
|
|
|
/**
|
|
* test_and_change_bit - Change a bit and return its old value
|
|
* @nr: Bit to change
|
|
* @addr: Address to count from
|
|
*
|
|
* This operation is atomic and cannot be reordered.
|
|
* It also implies a memory barrier.
|
|
*/
|
|
static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
|
|
{
|
|
|
|
unsigned long __res, __mask;
|
|
__mask = MASK(nr);
|
|
__asm__ __volatile__ ( \
|
|
"amoxor.w %0, %2, %1" \
|
|
: "=r" (__res), "+A" (*addr) \
|
|
: "r" (__mask)); \
|
|
|
|
return ((__res & __mask) != 0);
|
|
}
|
|
|
|
/**
|
|
* set_bit - Atomically set a bit in memory
|
|
* @nr: the bit to set
|
|
* @addr: the address to start counting from
|
|
*
|
|
* This function is atomic and may not be reordered.
|
|
*/
|
|
|
|
static inline void set_bit(int nr, volatile unsigned long *addr)
|
|
{
|
|
__asm__ __volatile__ ( \
|
|
"AMOOR.w zero, %1, %0" \
|
|
: "+A" (*addr) \
|
|
: "r" (MASK(nr)));
|
|
}
|
|
|
|
/**
|
|
* clear_bit - Clears a bit in memory
|
|
* @nr: Bit to clear
|
|
* @addr: Address to start counting from
|
|
*
|
|
* clear_bit() is atomic and may not be reordered.
|
|
*/
|
|
static inline void clear_bit(int nr, volatile unsigned long *addr)
|
|
{
|
|
__asm__ __volatile__ ( \
|
|
"AMOAND.w zero, %1, %0" \
|
|
: "+A" (*addr) \
|
|
: "r" (MASK_NOT(nr)));
|
|
}
|
|
|
|
/**
|
|
* change_bit - Toggle a bit in memory
|
|
* @nr: Bit to change
|
|
* @addr: Address to start counting from
|
|
*
|
|
* change_bit() is atomic and may not be reordered.
|
|
*/
|
|
static inline void change_bit(int nr, volatile unsigned long *addr)
|
|
{
|
|
__asm__ __volatile__ ( \
|
|
"AMOXOR.w zero, %1, %0" \
|
|
: "+A" (*addr) \
|
|
: "r" (MASK(nr)));
|
|
}
|
|
|
|
#endif /* __riscv_atomic */
|
|
|
|
#endif /*__GNUC__*/
|
|
|
|
#endif /*__ASSEMBLER__*/
|
|
|
|
#endif /*__riscv*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /*RISCV_CSR_ENCODING_H*/
|
|
|