mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
1b7a2e40a3
Change configCHECK_FOR_STACK_OVERFLOW to 3 to also check the interrupt stack. Add a build configuration to allow use on the PIC32 USBII starter kit. Increase some delays when talking to the LCD to ensure it always displays correctly. Rewrite the register test tasks.
557 lines
11 KiB
ArmAsm
557 lines
11 KiB
ArmAsm
/*
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FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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>>! NOTE: The modification to the GPL is included to allow you to distribute
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>>! a combined work that includes FreeRTOS without being obliged to provide
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>>! the source code for proprietary components outside of the FreeRTOS
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>>! kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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compatible FAT file system, and our tiny thread aware UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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licenses offer ticketed support, indemnification and middleware.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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1 tab == 4 spaces!
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*/
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#include <xc.h>
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#include <sys/asm.h>
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.set nomips16
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.set noreorder
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.global vRegTest1
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.global vRegTest2
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.set noreorder
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.set noat
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.ent error_loop
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/* Reg test tasks call the error loop when they find an error. Sitting in the
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tight error loop prevents them incrementing their ulRegTestnCycles counter, and
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so allows the check softwate timer to know an error has been found. */
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error_loop:
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b .
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nop
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.end error_loop
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.set noreorder
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.set noat
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.ent vRegTest1
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vRegTest1:
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/* Fill the registers with known values. */
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addiu $1, $0, 0x11
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addiu $2, $0, 0x12
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addiu $3, $0, 0x13
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/* $4 contains the address of the loop counter - don't mess with $4. */
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addiu $5, $0, 0x15
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addiu $6, $0, 0x16
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addiu $7, $0, 0x17
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addiu $8, $0, 0x18
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addiu $9, $0, 0x19
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addiu $10, $0, 0x110
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addiu $11, $0, 0x111
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addiu $12, $0, 0x112
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addiu $13, $0, 0x113
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addiu $14, $0, 0x114
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addiu $15, $0, 0x115
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addiu $16, $0, 0x116
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addiu $17, $0, 0x117
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addiu $18, $0, 0x118
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addiu $19, $0, 0x119
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addiu $20, $0, 0x120
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addiu $21, $0, 0x121
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addiu $23, $0, 0x123
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addiu $24, $0, 0x124
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addiu $25, $0, 0x125
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addiu $30, $0, 0x130
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addiu $22, $0, 0x131
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mthi $22
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addiu $22, $0, 0x132
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mtlo $22
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vRegTest1Loop:
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/* Check each register maintains the value assigned to it for the lifetime
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of the task. */
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addiu $22, $0, 0x00
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addiu $22, $1, -0x11
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beq $22, $0, .+16
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nop
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/* The register value was not that expected. Jump to the error loop so the
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cycle counter stops incrementing. */
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $2, -0x12
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $3, -0x13
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $5, -0x15
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $6, -0x16
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $7, -0x17
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $8, -0x18
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $9, -0x19
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $10, -0x110
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $11, -0x111
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $12, -0x112
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $13, -0x113
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $14, -0x114
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $15, -0x115
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $16, -0x116
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $17, -0x117
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $18, -0x118
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $19, -0x119
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $20, -0x120
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $21, -0x121
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $23, -0x123
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $24, -0x124
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $25, -0x125
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $30, -0x130
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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mfhi $22
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addiu $22, $22, -0x131
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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mflo $22, $ac1
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addiu $22, $22, -0x132
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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/* No errors detected. Increment the loop count so the check timer knows
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this task is still running without error, then loop back to do it all
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again. The address of the loop counter is in $4. */
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lw $22, 0( $4 )
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addiu $22, $22, 0x01
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sw $22, 0( $4 )
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b vRegTest1Loop
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nop
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.end vRegTest1
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.set noreorder
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.set noat
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.ent vRegTest2
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vRegTest2:
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addiu $1, $0, 0x21
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addiu $2, $0, 0x22
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addiu $3, $0, 0x23
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/* $4 contains the address of the loop counter - don't mess with $4. */
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addiu $5, $0, 0x25
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addiu $6, $0, 0x26
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addiu $7, $0, 0x27
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addiu $8, $0, 0x28
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addiu $9, $0, 0x29
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addiu $10, $0, 0x210
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addiu $11, $0, 0x211
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addiu $12, $0, 0x212
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addiu $13, $0, 0x213
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addiu $14, $0, 0x214
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addiu $15, $0, 0x215
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addiu $16, $0, 0x216
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addiu $17, $0, 0x217
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addiu $18, $0, 0x218
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addiu $19, $0, 0x219
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addiu $20, $0, 0x220
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addiu $21, $0, 0x221
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addiu $23, $0, 0x223
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addiu $24, $0, 0x224
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addiu $25, $0, 0x225
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addiu $30, $0, 0x230
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addiu $22, $0, 0x231
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mthi $22
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addiu $22, $0, 0x232
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mtlo $22
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vRegTest2Loop:
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addiu $22, $0, 0x00
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addiu $22, $1, -0x21
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $2, -0x22
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $3, -0x23
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $5, -0x25
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $6, -0x26
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $7, -0x27
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $8, -0x28
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $9, -0x29
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $10, -0x210
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $11, -0x211
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $12, -0x212
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $13, -0x213
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $14, -0x214
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $15, -0x215
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $16, -0x216
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $17, -0x217
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $18, -0x218
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $19, -0x219
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $20, -0x220
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $21, -0x221
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $23, -0x223
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $24, -0x224
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $25, -0x225
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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addiu $22, $0, 0x00
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addiu $22, $30, -0x230
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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mfhi $22
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addiu $22, $22, -0x231
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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mflo $22, $ac1
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addiu $22, $22, -0x232
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beq $22, $0, .+16
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nop
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b error_loop
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nop
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/* No errors detected. Increment the loop count so the check timer knows
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this task is still running without error, then loop back to do it all
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again. The address of the loop counter is in $4. */
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lw $22, 0( $4 )
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addiu $22, $22, 0x01
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sw $22, 0( $4 )
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b vRegTest2Loop
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nop
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.end vRegTest2
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