mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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94aa31c3cb
* deleted old version wolfSSL before updating * updated wolfSSL to the latest version(v4.4.0) * updated wolfSSL to the latest version(v4.4.0) * added macros for timing resistance Co-authored-by: RichardBarry <3073890+RichardBarry@users.noreply.github.com> Co-authored-by: Ming Yue <mingyue86010@gmail.com>
71 lines
3.3 KiB
Tcl
71 lines
3.3 KiB
Tcl
# this method initializes debug modules which are not affected by software reset
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# register names should be referenced including the register group name to improve performance
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proc init_debug_modules {} {
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# initialize LR to avoid invalid stack after reset
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reg "User\\/System Mode Registers/LR" = 0xFFFFFFFF
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# clear DWT function registers
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reg "Core Debug Registers/DEMCR" = 0x1000001
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reg "Data Watchpoint and Trace Unit Registers/DWT_FUNCTION0" = 0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_FUNCTION1" = 0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_FUNCTION2" = 0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_FUNCTION3" = 0x0
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# clear FPB comparators
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reg "Flash Patch and Breakpoint Unit Registers/FP_COMP0" = 0x0
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reg "Flash Patch and Breakpoint Unit Registers/FP_COMP1" = 0x0
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reg "Flash Patch and Breakpoint Unit Registers/FP_COMP2" = 0x0
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reg "Flash Patch and Breakpoint Unit Registers/FP_COMP3" = 0x0
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reg "Flash Patch and Breakpoint Unit Registers/FP_COMP4" = 0x0
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reg "Flash Patch and Breakpoint Unit Registers/FP_COMP5" = 0x0
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}
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proc init_trace_modules {} {
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# clear DWT registers
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reg "Data Watchpoint and Trace Unit Registers/DWT_CTRL" =0x40000000
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reg "Data Watchpoint and Trace Unit Registers/DWT_CYCCNT" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_CPICNT" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_EXCCNT" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_SLEEPCNT" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_LSUCNT" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_FOLDCNT" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_COMP0" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_COMP1" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_COMP2" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_COMP3" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_MASK0" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_MASK1" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_MASK2" =0x0
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reg "Data Watchpoint and Trace Unit Registers/DWT_MASK3" =0x0
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# clear ITM registers
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reg "Instrumentation Trace Macrocell Registers/ITM_LAR" =0xc5acce55
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reg "Instrumentation Trace Macrocell Registers/ITM_TER" =0x0
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reg "Instrumentation Trace Macrocell Registers/ITM_TPR" =0x0
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reg "Instrumentation Trace Macrocell Registers/ITM_TCR" =0x0
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reg "Instrumentation Trace Macrocell Registers/ITM_LAR" =0x1
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# reset Funnel registers
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reg "Embedded Trace Funnel Registers/ETF_FCR" =0x300
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# clear MCM registers
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reg "Core Platform Miscellaneous Control Module (MCM) Registers/MCM_ETBCC" =0x0
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reg "Core Platform Miscellaneous Control Module (MCM) Registers/MCM_ETBRL" =0x0
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# set SCB_VTOR register for RAM
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reg "System Control Registers/SCB_VTOR" =0x20000000
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}
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proc envsetup {} {
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# Environment Setup
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radix x
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config hexprefix 0x
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config MemIdentifier p
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config MemWidth 32
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config MemAccess 32
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config MemSwap off
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}
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#-------------------------------------------------------------------------------
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# Main
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#-------------------------------------------------------------------------------
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envsetup
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init_debug_modules
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init_trace_modules
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