sifive_hifive1_revb 0.1 From sifive,hifive1-revb,model device generator 8 32 32 read-write riscv_clint0_0 From riscv,clint0,control peripheral generator 0x2000000 0 0x10000 registers msip_0 MSIP Register for hart 0 0x0 mtimecmp_0 MTIMECMP Register for hart 0 0x4000 64 mtime MTIME Register 0xBFF8 64 riscv_plic0_0 From riscv,plic0,control peripheral generator 0xC000000 0 0x4000000 registers priority_1 PRIORITY Register for interrupt id 1 0x4 priority_2 PRIORITY Register for interrupt id 2 0x8 priority_3 PRIORITY Register for interrupt id 3 0xC priority_4 PRIORITY Register for interrupt id 4 0x10 priority_5 PRIORITY Register for interrupt id 5 0x14 priority_6 PRIORITY Register for interrupt id 6 0x18 priority_7 PRIORITY Register for interrupt id 7 0x1C priority_8 PRIORITY Register for interrupt id 8 0x20 priority_9 PRIORITY Register for interrupt id 9 0x24 priority_10 PRIORITY Register for interrupt id 10 0x28 priority_11 PRIORITY Register for interrupt id 11 0x2C priority_12 PRIORITY Register for interrupt id 12 0x30 priority_13 PRIORITY Register for interrupt id 13 0x34 priority_14 PRIORITY Register for interrupt id 14 0x38 priority_15 PRIORITY Register for interrupt id 15 0x3C priority_16 PRIORITY Register for interrupt id 16 0x40 priority_17 PRIORITY Register for interrupt id 17 0x44 priority_18 PRIORITY Register for interrupt id 18 0x48 priority_19 PRIORITY Register for interrupt id 19 0x4C priority_20 PRIORITY Register for interrupt id 20 0x50 priority_21 PRIORITY Register for interrupt id 21 0x54 priority_22 PRIORITY Register for interrupt id 22 0x58 priority_23 PRIORITY Register for interrupt id 23 0x5C priority_24 PRIORITY Register for interrupt id 24 0x60 priority_25 PRIORITY Register for interrupt id 25 0x64 priority_26 PRIORITY Register for interrupt id 26 0x68 priority_27 PRIORITY Register for interrupt id 27 0x6C priority_28 PRIORITY Register for interrupt id 28 0x70 priority_29 PRIORITY Register for interrupt id 29 0x74 priority_30 PRIORITY Register for interrupt id 30 0x78 priority_31 PRIORITY Register for interrupt id 31 0x7C priority_32 PRIORITY Register for interrupt id 32 0x80 priority_33 PRIORITY Register for interrupt id 33 0x84 priority_34 PRIORITY Register for interrupt id 34 0x88 priority_35 PRIORITY Register for interrupt id 35 0x8C priority_36 PRIORITY Register for interrupt id 36 0x90 priority_37 PRIORITY Register for interrupt id 37 0x94 priority_38 PRIORITY Register for interrupt id 38 0x98 priority_39 PRIORITY Register for interrupt id 39 0x9C priority_40 PRIORITY Register for interrupt id 40 0xA0 priority_41 PRIORITY Register for interrupt id 41 0xA4 priority_42 PRIORITY Register for interrupt id 42 0xA8 priority_43 PRIORITY Register for interrupt id 43 0xAC priority_44 PRIORITY Register for interrupt id 44 0xB0 priority_45 PRIORITY Register for interrupt id 45 0xB4 priority_46 PRIORITY Register for interrupt id 46 0xB8 priority_47 PRIORITY Register for interrupt id 47 0xBC priority_48 PRIORITY Register for interrupt id 48 0xC0 priority_49 PRIORITY Register for interrupt id 49 0xC4 priority_50 PRIORITY Register for interrupt id 50 0xC8 priority_51 PRIORITY Register for interrupt id 51 0xCC priority_52 PRIORITY Register for interrupt id 52 0xD0 pending_0 PENDING Register for interrupt ids 31 to 0 0x1000 pending_1 PENDING Register for interrupt ids 52 to 32 0x1004 enable_0_0 ENABLE Register for interrupt ids 31 to 0 for hart 0 0x2000 enable_1_0 ENABLE Register for interrupt ids 52 to 32 for hart 0 0x2004 threshold_0 PRIORITY THRESHOLD Register for hart 0 0x200000 claimplete_0 CLAIM and COMPLETE Register for hart 0 0x200004 sifive_aon0_0 From sifive,aon0,mem peripheral generator 0x10000000 0 0x8000 registers backup_0 Backup Register 0 0x80 backup_1 Backup Register 1 0x84 backup_2 Backup Register 2 0x88 backup_3 Backup Register 3 0x8C backup_4 Backup Register 4 0x90 backup_5 Backup Register 5 0x94 backup_6 Backup Register 6 0x98 backup_7 Backup Register 7 0x9C backup_8 Backup Register 8 0xA0 backup_9 Backup Register 9 0xA4 backup_10 Backup Register 10 0xA8 backup_11 Backup Register 11 0xAC backup_12 Backup Register 12 0xB0 backup_13 Backup Register 13 0xB4 backup_14 Backup Register 14 0xB8 backup_15 Backup Register 15 0xBC wdogcfg wdog Configuration 0x0 wdogscale Counter scale value. [3:0] read-write wdogrsten Controls whether the comparator output can set the wdogrst bit and hence cause a full reset. [8:8] read-write wdogzerocmp Reset counter to zero after match. [9:9] read-write wdogenalways Enable Always - run continuously [12:12] read-write wdogcoreawake Increment the watchdog counter if the processor is not asleep [13:13] read-write wdogip0 Interrupt 0 Pending [28:28] read-write wdogcount Counter Register 0x8 wdogs Scaled value of Counter 0x10 wdogfeed Feed register 0x18 wdogkey Key Register 0x1C wdogcmp0 Comparator 0 0x20 rtccfg rtc Configuration 0x40 rtcscale Counter scale value. [3:0] read-write rtcenalways Enable Always - run continuously [12:12] read-write rtcip0 Interrupt 0 Pending [28:28] read-write rtccountlo Low bits of Counter 0x48 rtccounthi High bits of Counter 0x4C rtcs Scaled value of Counter 0x50 rtccmp0 Comparator 0 0x60 pmuwakeupi0 Wakeup program instruction 0 0x100 pmuwakeupi1 Wakeup program instruction 1 0x104 pmuwakeupi2 Wakeup program instruction 2 0x108 pmuwakeupi3 Wakeup program instruction 3 0x10C pmuwakeupi4 Wakeup program instruction 4 0x110 pmuwakeupi5 Wakeup program instruction 5 0x114 pmuwakeupi6 Wakeup program instruction 6 0x118 pmuwakeupi7 Wakeup program instruction 7 0x11C pmusleepi0 Sleep program instruction 0 0x120 pmusleepi1 Sleep program instruction 1 0x124 pmusleepi2 Sleep program instruction 2 0x128 pmusleepi3 Sleep program instruction 3 0x12C pmusleepi4 Sleep program instruction 4 0x130 pmusleepi5 Sleep program instruction 5 0x134 pmusleepi6 Sleep program instruction 6 0x138 pmusleepi7 Sleep program instruction 7 0x13C pmuie PMU Interrupt Enables 0x140 pmucause PMU Wakeup Cause 0x144 pmusleep Initiate PMU Sleep Sequence 0x148 pmukey PMU Key. Reads as 1 when PMU is unlocked 0x14C aoncfg AON Block Configuration Information 0x300 has_bandgap Bandgap feature is present [0:0] read-only has_bod Brownout detector feature is present [1:1] read-only has_lfrosc Low Frequency Ring Oscillator feature is present [2:2] read-only has_lfrcosc Low Frequency RC Oscillator feature is present [3:3] read-only has_lfxosc Low Frequency Crystal Oscillator feature is present [4:4] read-only has_por Power-On-Reset feature is present [5:5] read-only has_ldo Low Dropout Regulator feature is present [6:6] read-only lfrosccfg Ring Oscillator Configuration and Status 0x70 lfroscdiv Ring Oscillator Divider Register [5:0] read-write lfrosctrim Ring Oscillator Trim Register [20:16] read-write lfroscen Ring Oscillator Enable [30:30] read-write lfroscrdy Ring Oscillator Ready [31:31] read-only lfclkmux Low-Frequency Clock Mux Control and Status 0x7C lfextclk_sel Low Frequency Clock Source Selector [0:0] read-write internal Use internal LF clock source 0 external Use external LF clock source 1 lfextclk_mux_status Setting of the aon_lfclksel pin [31:31] read-only external Use external LF clock source 0 sw Use clock source selected by lfextclk_sel 1 sifive_fe310_g000_prci_0 From sifive,fe310-g000,prci,mem peripheral generator 0x10008000 0 0x8000 registers hfrosccfg Ring Oscillator Configuration and Status 0x0 hfroscdiv Ring Oscillator Divider Register [5:0] read-write hfrosctrim Ring Oscillator Trim Register [20:16] read-write hfroscen Ring Oscillator Enable [30:30] read-write hfroscrdy Ring Oscillator Ready [31:31] read-only hfxosccfg Crystal Oscillator Configuration and Status 0x4 hfxoscen Crystal Oscillator Enable [30:30] read-write hfxoscrdy Crystal Oscillator Ready [31:31] read-only pllcfg PLL Configuration and Status 0x8 pllr PLL R Value [2:0] read-write pllf PLL F Value [9:4] read-write pllq PLL Q Value [11:10] read-write pllsel PLL Select [16:16] read-write pllrefsel PLL Reference Select [17:17] read-write pllbypass PLL Bypass [18:18] read-write plllock PLL Lock [31:31] read-only plloutdiv PLL Final Divide Configuration 0xC plloutdiv PLL Final Divider Value [5:0] read-write plloutdivby1 PLL Final Divide By 1 [13:8] read-write procmoncfg Process Monitor Configuration and Status 0xF0 procmon_div_sel Proccess Monitor Divider [4:0] read-write procmon_delay_sel Process Monitor Delay Selector [12:8] read-write procmon_en Process Monitor Enable [16:16] read-write procomon_sel Process Monitor Select [25:24] read-write sifive_gpio0_0 From sifive,gpio0,control peripheral generator 0x10012000 0 0x1000 registers input_val Pin value 0x0 input_en Pin input enable 0x4 output_en Pin output enable 0x8 output_val Output value 0xC pue Internal pull-up enable 0x10 ds Pin drive strength 0x14 rise_ie Rise interrupt enable 0x18 rise_ip Rise interrupt pending 0x1C fall_ie Fall interrupt enable 0x20 fall_ip Fall interrupt pending 0x24 high_ie High interrupt enable 0x28 high_ip High interrupt pending 0x2C low_ie Low interrupt enable 0x30 low_ip Low interrupt pending 0x34 iof_en I/O function enable 0x38 iof_sel I/O function select 0x3C out_xor Output XOR (invert) 0x40 sifive_uart0_0 From sifive,uart0,control peripheral generator 0x10013000 0 0x1000 registers txdata Transmit data register 0x0 data Transmit data [7:0] read-write full Transmit FIFO full [31:31] read-only rxdata Receive data register 0x4 data Received data [7:0] read-only empty Receive FIFO empty [31:31] read-only txctrl Transmit control register 0x8 txen Transmit enable [0:0] read-write nstop Number of stop bits [1:1] read-write txcnt Transmit watermark level [18:16] read-write rxctrl Receive control register 0xC rxen Receive enable [0:0] read-write rxcnt Receive watermark level [18:16] read-write ie UART interrupt enable 0x10 txwm Transmit watermark interrupt enable [0:0] read-write rxwm Receive watermark interrupt enable [1:1] read-write ip UART interrupt pending 0x14 txwm Transmit watermark interrupt pending [0:0] read-only rxwm Receive watermark interrupt pending [1:1] read-only div Baud rate divisor 0x18 div Baud rate divisor. [15:0] read-write sifive_spi0_0 From sifive,spi0,control peripheral generator 0x10014000 0 0x1000 registers sckdiv Serial clock divisor 0x0 div Divisor for serial clock. [11:0] read-write sckmode Serial clock mode 0x4 pha Serial clock phase [0:0] read-write pol Serial clock polarity [1:1] read-write csid Chip select ID 0x10 csid Chip select ID. [31:0] read-write csdef Chip select default 0x14 csdef Chip select default value. Reset to all-1s. [31:0] read-write csmode Chip select mode 0x18 mode Chip select mode [1:0] read-write delay0 Delay control 0 0x28 cssck CS to SCK Delay [7:0] read-write sckcs SCK to CS Delay [23:16] read-write delay1 Delay control 1 0x2C intercs Minimum CS inactive time [7:0] read-write interxfr Maximum interframe delay [23:16] read-write extradel SPI extra sampling delay to increase the SPI frequency 0x38 coarse Coarse grain sample delay (multiples of system clocks) [11:0] read-write fine Fine grain sample delay (multiples of process-specific buffer delay) [16:12] read-write sampledel Number of delay stages from slave to the SPI controller 0x3C sd Number of delay stages from slave to SPI controller [4:0] read-write fmt Frame format 0x40 proto SPI protocol [1:0] read-write endian SPI endianness [2:2] read-write dir SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. [3:3] read-write len Number of bits per frame [19:16] read-write txdata Tx FIFO Data 0x48 data Transmit data [7:0] read-write full FIFO full flag [31:31] read-only rxdata Rx FIFO data 0x4C data Received data [7:0] read-only empty FIFO empty flag [31:31] read-write txmark Tx FIFO watermark 0x50 txmark Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise. [2:0] read-write rxmark Rx FIFO watermark 0x54 rxmark Receive watermark [2:0] read-write fctrl SPI flash interface control 0x60 en SPI Flash Mode Select [0:0] read-write ffmt SPI flash instruction format 0x64 cmd_en Enable sending of command [0:0] read-write addr_len Number of address bytes (0 to 4) [3:1] read-write pad_cnt Number of dummy cycles [7:4] read-write cmd_proto Protocol for transmitting command [9:8] read-write addr_proto Protocol for transmitting address and padding [11:10] read-write data_proto Protocol for receiving data bytes [13:12] read-write cmd_code Value of command byte [23:16] read-write pad_code First 8 bits to transmit during dummy cycles [31:24] read-write ie SPI interrupt enable 0x70 txwm Transmit watermark enable [0:0] read-write rxwm Receive watermark enable [1:1] read-write ip SPI interrupt pending 0x74 txwm Transmit watermark pending [0:0] read-only rxwm Receive watermark pending [1:1] read-only sifive_pwm0_0 From sifive,pwm0,control peripheral generator 0x10015000 0 0x1000 registers pwmcfg PWM configuration register 0x0 pwmscale PWM Counter scale [3:0] read-write pwmsticky PWM Sticky - disallow clearing pwmcmpXip bits [8:8] read-write pwmzerocmp PWM Zero - counter resets to zero after match [9:9] read-write pwmdeglitch PWM Deglitch - latch pwmcmpXip within same cycle [10:10] read-write pwmenalways PWM enable always - run continuously [12:12] read-write pwmenoneshot PWM enable one shot - run one cycle [13:13] read-write pwmcmp0center PWM0 Compare Center [16:16] read-write pwmcmp1center PWM1 Compare Center [17:17] read-write pwmcmp2center PWM2 Compare Center [18:18] read-write pwmcmp3center PWM3 Compare Center [19:19] read-write pwmcmp0invert PWM0 Invert [20:20] read-write pwmcmp1invert PWM1 Invert [21:21] read-write pwmcmp2invert PWM2 Invert [22:22] read-write pwmcmp3invert PWM3 Invert [23:23] read-write pwmcmp0gang PWM0/PWM1 Compare Gang [24:24] read-write pwmcmp1gang PWM1/PWM2 Compare Gang [25:25] read-write pwmcmp2gang PWM2/PWM3 Compare Gang [26:26] read-write pwmcmp3gang PWM3/PWM0 Compare Gang [27:27] read-write pwmcmp0ip PWM0 Interrupt Pending [28:28] read-write pwmcmp1ip PWM1 Interrupt Pending [29:29] read-write pwmcmp2ip PWM2 Interrupt Pending [30:30] read-write pwmcmp3ip PWM3 Interrupt Pending [31:31] read-write pwmcount PWM count register 0x8 pwmcount PWM count register. [30:0] read-write pwms Scaled PWM count register 0x10 pwms Scaled PWM count register. [15:0] read-write pwmcmp0 PWM 0 compare register 0x20 pwmcmp0 PWM 0 Compare Value [15:0] read-write pwmcmp1 PWM 1 compare register 0x24 pwmcmp1 PWM 1 Compare Value [15:0] read-write pwmcmp2 PWM 2 compare register 0x28 pwmcmp2 PWM 2 Compare Value [15:0] read-write pwmcmp3 PWM 3 compare register 0x2C pwmcmp3 PWM 3 Compare Value [15:0] read-write sifive_i2c0_0 From sifive,i2c0,control peripheral generator 0x10016000 0 0x1000 registers prescale_low Clock Prescale register lo-byte 0x0 prescale_high Clock Prescale register hi-byte 0x4 control Control register 0x8 en I2C core enable bit [6:6] read-write ien I2C core interrupt enable bit [7:7] read-write transmit__receive Transmit and receive data byte register 0xC command__status Command write and status read register 0x10 wr_iack__rd_if Clear interrupt and Interrupt pending [0:0] read-write wr_res__rd_tip Reserved and Transfer in progress [1:1] read-write wr_res__rd_res Reserved and Reserved [2:2] read-write wr_ack__rd_res Send ACK/NACK and Reserved [3:3] read-write wr_txd__rd_res Transmit data and Reserved [4:4] read-write wr_rxd__rd_al Receive data and Arbitration lost [5:5] read-write wr_sto__rd_busy Generate stop and I2C bus busy [6:6] read-write wr_sta__rd_rxack Generate start and Got ACK/NACK [7:7] read-write sifive_uart0_1 From sifive,uart0,control peripheral generator 0x10023000 0 0x1000 registers txdata Transmit data register 0x0 data Transmit data [7:0] read-write full Transmit FIFO full [31:31] read-only rxdata Receive data register 0x4 data Received data [7:0] read-only empty Receive FIFO empty [31:31] read-only txctrl Transmit control register 0x8 txen Transmit enable [0:0] read-write nstop Number of stop bits [1:1] read-write txcnt Transmit watermark level [18:16] read-write rxctrl Receive control register 0xC rxen Receive enable [0:0] read-write rxcnt Receive watermark level [18:16] read-write ie UART interrupt enable 0x10 txwm Transmit watermark interrupt enable [0:0] read-write rxwm Receive watermark interrupt enable [1:1] read-write ip UART interrupt pending 0x14 txwm Transmit watermark interrupt pending [0:0] read-only rxwm Receive watermark interrupt pending [1:1] read-only div Baud rate divisor 0x18 div Baud rate divisor. [15:0] read-write sifive_spi0_1 From sifive,spi0,control peripheral generator 0x10024000 0 0x1000 registers sckdiv Serial clock divisor 0x0 div Divisor for serial clock. [11:0] read-write sckmode Serial clock mode 0x4 pha Serial clock phase [0:0] read-write pol Serial clock polarity [1:1] read-write csid Chip select ID 0x10 csid Chip select ID. [31:0] read-write csdef Chip select default 0x14 csdef Chip select default value. Reset to all-1s. [31:0] read-write csmode Chip select mode 0x18 mode Chip select mode [1:0] read-write delay0 Delay control 0 0x28 cssck CS to SCK Delay [7:0] read-write sckcs SCK to CS Delay [23:16] read-write delay1 Delay control 1 0x2C intercs Minimum CS inactive time [7:0] read-write interxfr Maximum interframe delay [23:16] read-write extradel SPI extra sampling delay to increase the SPI frequency 0x38 coarse Coarse grain sample delay (multiples of system clocks) [11:0] read-write fine Fine grain sample delay (multiples of process-specific buffer delay) [16:12] read-write sampledel Number of delay stages from slave to the SPI controller 0x3C sd Number of delay stages from slave to SPI controller [4:0] read-write fmt Frame format 0x40 proto SPI protocol [1:0] read-write endian SPI endianness [2:2] read-write dir SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. [3:3] read-write len Number of bits per frame [19:16] read-write txdata Tx FIFO Data 0x48 data Transmit data [7:0] read-write full FIFO full flag [31:31] read-only rxdata Rx FIFO data 0x4C data Received data [7:0] read-only empty FIFO empty flag [31:31] read-write txmark Tx FIFO watermark 0x50 txmark Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise. [2:0] read-write rxmark Rx FIFO watermark 0x54 rxmark Receive watermark [2:0] read-write fctrl SPI flash interface control 0x60 en SPI Flash Mode Select [0:0] read-write ffmt SPI flash instruction format 0x64 cmd_en Enable sending of command [0:0] read-write addr_len Number of address bytes (0 to 4) [3:1] read-write pad_cnt Number of dummy cycles [7:4] read-write cmd_proto Protocol for transmitting command [9:8] read-write addr_proto Protocol for transmitting address and padding [11:10] read-write data_proto Protocol for receiving data bytes [13:12] read-write cmd_code Value of command byte [23:16] read-write pad_code First 8 bits to transmit during dummy cycles [31:24] read-write ie SPI interrupt enable 0x70 txwm Transmit watermark enable [0:0] read-write rxwm Receive watermark enable [1:1] read-write ip SPI interrupt pending 0x74 txwm Transmit watermark pending [0:0] read-only rxwm Receive watermark pending [1:1] read-only sifive_pwm0_1 From sifive,pwm0,control peripheral generator 0x10025000 0 0x1000 registers pwmcfg PWM configuration register 0x0 pwmscale PWM Counter scale [3:0] read-write pwmsticky PWM Sticky - disallow clearing pwmcmpXip bits [8:8] read-write pwmzerocmp PWM Zero - counter resets to zero after match [9:9] read-write pwmdeglitch PWM Deglitch - latch pwmcmpXip within same cycle [10:10] read-write pwmenalways PWM enable always - run continuously [12:12] read-write pwmenoneshot PWM enable one shot - run one cycle [13:13] read-write pwmcmp0center PWM0 Compare Center [16:16] read-write pwmcmp1center PWM1 Compare Center [17:17] read-write pwmcmp2center PWM2 Compare Center [18:18] read-write pwmcmp3center PWM3 Compare Center [19:19] read-write pwmcmp0invert PWM0 Invert [20:20] read-write pwmcmp1invert PWM1 Invert [21:21] read-write pwmcmp2invert PWM2 Invert [22:22] read-write pwmcmp3invert PWM3 Invert [23:23] read-write pwmcmp0gang PWM0/PWM1 Compare Gang [24:24] read-write pwmcmp1gang PWM1/PWM2 Compare Gang [25:25] read-write pwmcmp2gang PWM2/PWM3 Compare Gang [26:26] read-write pwmcmp3gang PWM3/PWM0 Compare Gang [27:27] read-write pwmcmp0ip PWM0 Interrupt Pending [28:28] read-write pwmcmp1ip PWM1 Interrupt Pending [29:29] read-write pwmcmp2ip PWM2 Interrupt Pending [30:30] read-write pwmcmp3ip PWM3 Interrupt Pending [31:31] read-write pwmcount PWM count register 0x8 pwmcount PWM count register. [30:0] read-write pwms Scaled PWM count register 0x10 pwms Scaled PWM count register. [15:0] read-write pwmcmp0 PWM 0 compare register 0x20 pwmcmp0 PWM 0 Compare Value [15:0] read-write pwmcmp1 PWM 1 compare register 0x24 pwmcmp1 PWM 1 Compare Value [15:0] read-write pwmcmp2 PWM 2 compare register 0x28 pwmcmp2 PWM 2 Compare Value [15:0] read-write pwmcmp3 PWM 3 compare register 0x2C pwmcmp3 PWM 3 Compare Value [15:0] read-write sifive_spi0_2 From sifive,spi0,control peripheral generator 0x10034000 0 0x1000 registers sckdiv Serial clock divisor 0x0 div Divisor for serial clock. [11:0] read-write sckmode Serial clock mode 0x4 pha Serial clock phase [0:0] read-write pol Serial clock polarity [1:1] read-write csid Chip select ID 0x10 csid Chip select ID. [31:0] read-write csdef Chip select default 0x14 csdef Chip select default value. Reset to all-1s. [31:0] read-write csmode Chip select mode 0x18 mode Chip select mode [1:0] read-write delay0 Delay control 0 0x28 cssck CS to SCK Delay [7:0] read-write sckcs SCK to CS Delay [23:16] read-write delay1 Delay control 1 0x2C intercs Minimum CS inactive time [7:0] read-write interxfr Maximum interframe delay [23:16] read-write extradel SPI extra sampling delay to increase the SPI frequency 0x38 coarse Coarse grain sample delay (multiples of system clocks) [11:0] read-write fine Fine grain sample delay (multiples of process-specific buffer delay) [16:12] read-write sampledel Number of delay stages from slave to the SPI controller 0x3C sd Number of delay stages from slave to SPI controller [4:0] read-write fmt Frame format 0x40 proto SPI protocol [1:0] read-write endian SPI endianness [2:2] read-write dir SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. [3:3] read-write len Number of bits per frame [19:16] read-write txdata Tx FIFO Data 0x48 data Transmit data [7:0] read-write full FIFO full flag [31:31] read-only rxdata Rx FIFO data 0x4C data Received data [7:0] read-only empty FIFO empty flag [31:31] read-write txmark Tx FIFO watermark 0x50 txmark Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise. [2:0] read-write rxmark Rx FIFO watermark 0x54 rxmark Receive watermark [2:0] read-write fctrl SPI flash interface control 0x60 en SPI Flash Mode Select [0:0] read-write ffmt SPI flash instruction format 0x64 cmd_en Enable sending of command [0:0] read-write addr_len Number of address bytes (0 to 4) [3:1] read-write pad_cnt Number of dummy cycles [7:4] read-write cmd_proto Protocol for transmitting command [9:8] read-write addr_proto Protocol for transmitting address and padding [11:10] read-write data_proto Protocol for receiving data bytes [13:12] read-write cmd_code Value of command byte [23:16] read-write pad_code First 8 bits to transmit during dummy cycles [31:24] read-write ie SPI interrupt enable 0x70 txwm Transmit watermark enable [0:0] read-write rxwm Receive watermark enable [1:1] read-write ip SPI interrupt pending 0x74 txwm Transmit watermark pending [0:0] read-only rxwm Receive watermark pending [1:1] read-only sifive_pwm0_2 From sifive,pwm0,control peripheral generator 0x10035000 0 0x1000 registers pwmcfg PWM configuration register 0x0 pwmscale PWM Counter scale [3:0] read-write pwmsticky PWM Sticky - disallow clearing pwmcmpXip bits [8:8] read-write pwmzerocmp PWM Zero - counter resets to zero after match [9:9] read-write pwmdeglitch PWM Deglitch - latch pwmcmpXip within same cycle [10:10] read-write pwmenalways PWM enable always - run continuously [12:12] read-write pwmenoneshot PWM enable one shot - run one cycle [13:13] read-write pwmcmp0center PWM0 Compare Center [16:16] read-write pwmcmp1center PWM1 Compare Center [17:17] read-write pwmcmp2center PWM2 Compare Center [18:18] read-write pwmcmp3center PWM3 Compare Center [19:19] read-write pwmcmp0invert PWM0 Invert [20:20] read-write pwmcmp1invert PWM1 Invert [21:21] read-write pwmcmp2invert PWM2 Invert [22:22] read-write pwmcmp3invert PWM3 Invert [23:23] read-write pwmcmp0gang PWM0/PWM1 Compare Gang [24:24] read-write pwmcmp1gang PWM1/PWM2 Compare Gang [25:25] read-write pwmcmp2gang PWM2/PWM3 Compare Gang [26:26] read-write pwmcmp3gang PWM3/PWM0 Compare Gang [27:27] read-write pwmcmp0ip PWM0 Interrupt Pending [28:28] read-write pwmcmp1ip PWM1 Interrupt Pending [29:29] read-write pwmcmp2ip PWM2 Interrupt Pending [30:30] read-write pwmcmp3ip PWM3 Interrupt Pending [31:31] read-write pwmcount PWM count register 0x8 pwmcount PWM count register. [30:0] read-write pwms Scaled PWM count register 0x10 pwms Scaled PWM count register. [15:0] read-write pwmcmp0 PWM 0 compare register 0x20 pwmcmp0 PWM 0 Compare Value [15:0] read-write pwmcmp1 PWM 1 compare register 0x24 pwmcmp1 PWM 1 Compare Value [15:0] read-write pwmcmp2 PWM 2 compare register 0x28 pwmcmp2 PWM 2 Compare Value [15:0] read-write pwmcmp3 PWM 3 compare register 0x2C pwmcmp3 PWM 3 Compare Value [15:0] read-write