Project Status (08/27/2011 - 12:37:45)
Project File:	system.xmp	Implementation State:	Programming File Generated
Module Name:	system	Errors:	No Errors
Product Version:	EDK 13.1	Warnings:	238 Warnings (0 new)

 

XPS Reports					[-]
Report Name	Generated	Errors	Warnings	Infos
Platgen Log File	Sat 27. Aug 12:17:02 2011	0	19 Warnings (18 new)	34 Infos (32 new)
Libgen Log File
Simgen Log File
BitInit Log File
System Log File	Sat 27. Aug 12:34:09 2011

 

XPS Synthesis Summary (estimated values)						[-]
Report	Generated	Flip Flops Used	LUTs Used	BRAMS Used	Errors
system	Sat 27. Aug 12:17:50 2011	14696	14247	14	0
mcb_ddr3_wrapper	Sat 27. Aug 12:16:50 2011	373	690		0
debug_module_wrapper	Sat 27. Aug 12:16:27 2011	131	142		0
clock_generator_0_wrapper	Sat 27. Aug 12:16:17 2011		1		0
microblaze_0_bram_block_wrapper	Sat 27. Aug 12:16:12 2011			4	0
microblaze_0_d_bram_ctrl_wrapper	Sat 27. Aug 12:16:06 2011	2	6		0
microblaze_0_i_bram_ctrl_wrapper	Sat 27. Aug 12:16:01 2011	2	6		0
axi4lite_0_wrapper	Sat 27. Aug 12:15:55 2011	2905	1827		0
axi_timer_0_wrapper	Fri 26. Aug 21:17:55 2011	260	272		0
microblaze_0_intc_wrapper	Fri 26. Aug 21:17:45 2011	86	115		0
ethernet_dma_wrapper	Fri 26. Aug 21:17:37 2011	3728	3798		0
ethernet_dma_wrapper_fifo_generator_v8_1_6_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:16:56 2011	107	109		0
ethernet_dma_wrapper_fifo_generator_v8_1_7_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:15:53 2011	98	100		0
ethernet_dma_wrapper_fifo_generator_v8_1_2_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:14:50 2011	68	49	1	0
ethernet_dma_wrapper_fifo_generator_v8_1_1_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:13:47 2011	74	59	1	0
ethernet_dma_wrapper_fifo_generator_v8_1_5_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:12:44 2011	69	49	1	0
ethernet_dma_wrapper_fifo_generator_v8_1_4_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:11:41 2011	99	103		0
ethernet_dma_wrapper_fifo_generator_v8_1_3_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:10:39 2011	97	98		0
ethernet_wrapper	Fri 26. Aug 21:09:24 2011	3166	3264		0
ethernet_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:08:27 2011	104	148		0
ethernet_wrapper_blk_mem_gen_v5_2_2_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:07:29 2011			1	0
ethernet_wrapper_blk_mem_gen_v5_2_1_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:07:03 2011			2	0
ethernet_wrapper_blk_mem_gen_v5_2_4_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:06:36 2011			1	0
ethernet_wrapper_blk_mem_gen_v5_2_3_blk_mem_gen_v5_2_xst_1	Fri 26. Aug 21:06:10 2011	2	49	2	0
push_buttons_4bits_wrapper	Fri 26. Aug 21:04:24 2011	72	85		0
leds_4bits_wrapper	Fri 26. Aug 21:04:14 2011	33	41		0
rs232_uart_1_wrapper	Fri 26. Aug 21:04:05 2011	84	102		0
proc_sys_reset_0_wrapper	Fri 26. Aug 21:03:43 2011	69	55		0
microblaze_0_dlmb_wrapper	Fri 26. Aug 21:03:19 2011	1	1		0
microblaze_0_ilmb_wrapper	Fri 26. Aug 21:03:15 2011	1	1		0
microblaze_0_wrapper	Fri 26. Aug 21:03:10 2011	1301	1703		0
axi4_0_wrapper	Fri 26. Aug 21:02:14 2011	1488	1083		0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_2_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:01:57 2011	90	97	2	0
axi4_0_wrapper_FIFO_GENERATOR_V8_1_1_fifo_generator_v8_1_xst_1	Fri 26. Aug 21:00:49 2011	89	96	1	0

 

Device Utilization Summary (actual values)					[-]
Slice Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Registers	12,060	54,576	22%
Number used as Flip Flops	12,052
Number used as Latches	0
Number used as Latch-thrus	0
Number used as AND/OR logics	8
Number of Slice LUTs	10,940	27,288	40%
Number used as logic	9,639	27,288	35%
Number using O6 output only	6,889
Number using O5 output only	260
Number using O5 and O6	2,490
Number used as ROM	0
Number used as Memory	693	6,408	10%
Number used as Dual Port RAM	250
Number using O6 output only	10
Number using O5 output only	4
Number using O5 and O6	236
Number used as Single Port RAM	1
Number using O6 output only	1
Number using O5 output only	0
Number using O5 and O6	0
Number used as Shift Register	442
Number using O6 output only	205
Number using O5 output only	7
Number using O5 and O6	230
Number used exclusively as route-thrus	608
Number with same-slice register load	566
Number with same-slice carry load	37
Number with other load	5
Number of occupied Slices	4,589	6,822	67%
Number of LUT Flip Flop pairs used	13,843
Number with an unused Flip Flop	3,765	13,843	27%
Number with an unused LUT	2,903	13,843	20%
Number of fully used LUT-FF pairs	7,175	13,843	51%
Number of unique control sets	697
Number of slice register sites lost         to control set restrictions	2,541	54,576	4%
Number of bonded IOBs	87	296	29%
Number of LOCed IOBs	87	87	100%
IOB Flip Flops	27
Number of RAMB16BWERs	12	116	10%
Number of RAMB8BWERs	4	232	1%
Number of BUFIO2/BUFIO2_2CLKs	3	32	9%
Number used as BUFIO2s	3
Number used as BUFIO2_2CLKs	0
Number of BUFIO2FB/BUFIO2FB_2CLKs	0	32	0%
Number of BUFG/BUFGMUXs	6	16	37%
Number used as BUFGs	5
Number used as BUFGMUX	1
Number of DCM/DCM_CLKGENs	0	8	0%
Number of ILOGIC2/ISERDES2s	12	376	3%
Number used as ILOGIC2s	12
Number used as ISERDES2s	0
Number of IODELAY2/IODRP2/IODRP2_MCBs	34	376	9%
Number used as IODELAY2s	10
Number used as IODRP2s	2
Number used as IODRP2_MCBs	22
Number of OLOGIC2/OSERDES2s	60	376	15%
Number used as OLOGIC2s	14
Number used as OSERDES2s	46
Number of BSCANs	1	4	25%
Number of BUFHs	0	256	0%
Number of BUFPLLs	0	8	0%
Number of BUFPLL_MCBs	1	4	25%
Number of DSP48A1s	3	58	5%
Number of GTPA1_DUALs	0	2	0%
Number of ICAPs	0	1	0%
Number of MCBs	1	2	50%
Number of PCIE_A1s	0	1	0%
Number of PCILOGICSEs	0	2	0%
Number of PLL_ADVs	2	4	50%
Number of PMVs	0	1	0%
Number of STARTUPs	0	1	0%
Number of SUSPEND_SYNCs	0	1	0%
Average Fanout of Non-Clock Nets	3.89

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Translation Report	Current	Sat 27. Aug 12:19:05 2011	0	87 Warnings (0 new)	13 Infos (8 new)
Map Report	Current	Sat 27. Aug 12:28:13 2011	0	50 Warnings (0 new)	1134 Infos (0 new)
Place and Route Report	Current	Sat 27. Aug 12:31:43 2011	0	51 Warnings (0 new)	3 Infos (0 new)
Post-PAR Static Timing Report	Current	Sat 27. Aug 12:32:50 2011	0	3 Warnings (0 new)	3 Infos (0 new)
Bitgen Report	Current	Sat 27. Aug 12:34:09 2011	0	47 Warnings (0 new)	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Log File	Current	Sat 27. Aug 12:34:09 2011

Date Generated: 08/27/2011 - 12:37:46