| XPS Synthesis Summary (estimated values) | [-] |
| Report | Generated | Flip Flops Used | LUTs Used | BRAMS Used | Errors |
| RTOSDemo | Mon 30. May 20:53:55 2011 | 7701 | 7505 | 48 | 0 |
| clock_generator_0_wrapper | Mon 30. May 20:53:21 2011 | | | | 0 |
| microblaze_0_intc_wrapper | Mon 30. May 19:38:32 2011 | 72 | 88 | | 0 |
| axi_bram_ctrl_0_bram_block_wrapper | Mon 30. May 19:38:24 2011 | | | 32 | 0 |
| axi_bram_ctrl_0_wrapper | Mon 30. May 19:38:16 2011 | 406 | 619 | | 0 |
| axi_timer_0_wrapper | Mon 30. May 19:38:03 2011 | 260 | 272 | | 0 |
| ethernet_lite_wrapper | Mon 30. May 19:37:52 2011 | 461 | 639 | 2 | 0 |
| ethernet_lite_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1 | Mon 30. May 19:37:36 2011 | 71 | 44 | | 0 |
| push_buttons_4bits_wrapper | Mon 30. May 19:35:44 2011 | 72 | 85 | | 0 |
| leds_4bits_wrapper | Mon 30. May 19:35:34 2011 | 33 | 41 | | 0 |
| rs232_uart_1_wrapper | Mon 30. May 19:35:24 2011 | 84 | 102 | | 0 |
| debug_module_wrapper | Mon 30. May 19:35:15 2011 | 131 | 142 | | 0 |
| proc_sys_reset_0_wrapper | Mon 30. May 19:35:01 2011 | 69 | 55 | | 0 |
| microblaze_0_bram_block_wrapper | Mon 30. May 19:34:55 2011 | | | 4 | 0 |
| microblaze_0_d_bram_ctrl_wrapper | Mon 30. May 19:34:50 2011 | 2 | 6 | | 0 |
| microblaze_0_i_bram_ctrl_wrapper | Mon 30. May 19:34:45 2011 | 2 | 6 | | 0 |
| microblaze_0_dlmb_wrapper | Mon 30. May 19:34:39 2011 | 1 | 1 | | 0 |
| microblaze_0_ilmb_wrapper | Mon 30. May 19:34:35 2011 | 1 | 1 | | 0 |
| microblaze_0_wrapper | Mon 30. May 19:34:30 2011 | 1989 | 2776 | 10 | 0 |
| axi4lite_0_wrapper | Mon 30. May 19:33:39 2011 | 2720 | 1760 | | 0 |
| axi4_0_wrapper | Mon 30. May 19:33:14 2011 | 1256 | 824 | | 0 |
| Device Utilization Summary (actual values) | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
5,491 |
54,576 |
10% |
|
| Number used as Flip Flops |
5,482 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
9 |
|
|
|
| Number of Slice LUTs |
5,420 |
27,288 |
19% |
|
| Number used as logic |
4,951 |
27,288 |
18% |
|
| Number using O6 output only |
3,573 |
|
|
|
| Number using O5 output only |
99 |
|
|
|
| Number using O5 and O6 |
1,279 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
242 |
6,408 |
3% |
|
| Number used as Dual Port RAM |
96 |
|
|
|
| Number using O6 output only |
4 |
|
|
|
| Number using O5 output only |
1 |
|
|
|
| Number using O5 and O6 |
91 |
|
|
|
| Number used as Single Port RAM |
4 |
|
|
|
| Number using O6 output only |
4 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
0 |
|
|
|
| Number used as Shift Register |
142 |
|
|
|
| Number using O6 output only |
48 |
|
|
|
| Number using O5 output only |
1 |
|
|
|
| Number using O5 and O6 |
93 |
|
|
|
| Number used exclusively as route-thrus |
227 |
|
|
|
| Number with same-slice register load |
217 |
|
|
|
| Number with same-slice carry load |
10 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
2,280 |
6,822 |
33% |
|
| Number of LUT Flip Flop pairs used |
6,801 |
|
|
|
| Number with an unused Flip Flop |
2,068 |
6,801 |
30% |
|
| Number with an unused LUT |
1,381 |
6,801 |
20% |
|
| Number of fully used LUT-FF pairs |
3,352 |
6,801 |
49% |
|
| Number of unique control sets |
364 |
|
|
|
Number of slice register sites lost
to control set restrictions |
1,396 |
54,576 |
2% |
|
| Number of bonded IOBs |
30 |
296 |
10% |
|
| Number of LOCed IOBs |
30 |
30 |
100% |
|
| IOB Flip Flops |
18 |
|
|
|
| Number of RAMB16BWERs |
48 |
116 |
41% |
|
| Number of RAMB8BWERs |
0 |
232 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2s |
1 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
| Number of BUFG/BUFGMUXs |
3 |
16 |
18% |
|
| Number used as BUFGs |
3 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
0 |
8 |
0% |
|
| Number of ILOGIC2/ISERDES2s |
10 |
376 |
2% |
|
| Number used as ILOGIC2s |
10 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
376 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
7 |
376 |
1% |
|
| Number used as OLOGIC2s |
7 |
|
|
|
| Number used as OSERDES2s |
0 |
|
|
|
| Number of BSCANs |
1 |
4 |
25% |
|
| Number of BUFHs |
0 |
256 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
8 |
58 |
13% |
|
| Number of GTPA1_DUALs |
0 |
2 |
0% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
0 |
2 |
0% |
|
| Number of PCIE_A1s |
0 |
1 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
1 |
4 |
25% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.93 |
|
|
|