Added LM3S811 demos for GCC and IAR. Mods to tasks.c and queue.c.

.git-blame-ignore-revs

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.github/CODEOWNERS

@@ -1,37 +0,0 @@
-# Each line is a file pattern followed by one or more owners.
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-# These owners will be the default owners for everything in
-# the repo. Unless a later match takes precedence,
-# @global-owner1 and @global-owner2 will be requested for
-# review when someone opens a pull request.
-*      @FreeRTOS/pr-bar-raisers
-
-# Order is important; the last matching pattern takes the most
-# precedence. When someone opens a pull request that only
-# modifies JS files, only @js-owner and not the global
-# owner(s) will be requested for a review.
-# *.c FreeRTOS/pr-bar-raiser
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-# You can also use email addresses if you prefer. They'll be
-# used to look up users just like we do for commit author
-# emails.
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-# directory at the root of the repository and any of its
-# subdirectories.
-# /build/logs/ @doctocat
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-# The `docs/*` pattern will match files like
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-# docs/*  docs@example.com
-
-# In this example, @octocat owns any file in an apps directory
-# anywhere in your repository.
-# apps/ @octocat
-
-# In this example, @doctocat owns any file in the `/docs`
-# directory in the root of your repository and any of its
-# subdirectories.
-# /docs/ @doctocat

.github/CONTRIBUTING.md

@@ -1,70 +0,0 @@
-# Contribution guidelines
-
-Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or
-documentation, we welcome our community to be involved in this project.
-
-Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible.
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-## Code of conduct
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-For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
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-## Security issue notifications
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-
-
-## Submitting a bugs/feature request
-Have a bug to report or feature to request? Follow these steps:
-1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed.
-2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below.
-3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features.
-
-When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include:
-
-* A clear description of the situation - what you observe, what you expect, and your view on how the two differ.
-* A reproducible test case or sequence of steps.
-* The version of our code being used.
-* Any modifications you've made relevant to the bug.
-* Details of your environment or deployment. Highlight anything unusual.
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-## Contributing via pull request
-Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that:
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-1. You are working against the latest source on the *main* branch.
-2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already.
-3. You open an issue to discuss any significant work - we would hate for your time to be wasted.
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-To send us a pull request, please:
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-1. Fork the repository.
-2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change.
-3. Follow the [coding style guide](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
-4. Commit to your fork using clear commit messages.
-5. Send us a pull request, answering any default questions in the pull request interface.
-   NOTE: Please make sure the default option (Allow edits from maintainers) is left checked.
-6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation.
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-GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and
-[creating a pull request](https://help.github.com/articles/creating-a-pull-request/).
-
-## Coding style
-* Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
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-## Getting your pull request merged
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-## Finding contributions to work on
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-## Licensing
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-We may ask you to sign a [Contributor License Agreement (CLA)](https://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes.

.github/ISSUE_TEMPLATE/bug-report.md

@@ -1,40 +0,0 @@
----
-name: Bug report
-about: Create a report to help us improve FreeRTOS. This should only be used for confirmed
-  bugs. If you suspect something it is best to first discuss it on the FreeRTOS community
-  support forums linked below.
-title: "[BUG]"
-labels: bug
-assignees: ''
-
----
-
-**Describe the bug**
-A concise description of what the bug is.
-
-**Target**
-- Development board: [e.g. HiFive11 RevB]
-- Instruction Set Architecture: [e.g. RV32IMAC]
-- IDE and version: [e.g. Freedom Studio 4.12.0.2019-08-2]
-- Toolchain and version: [e.g. riscv64-unknown-elf-gcc-8.3.0-2019.08.0]
-
-**Host**
-- Host OS: [e.g. MacOS]
-- Version: [e.g. Mojave 10.14.6]
-
-**To Reproduce**
-- Use project ... and configure with ...
-- Run on ... and could observe ...
-
-**Expected behavior**
-A concise description of what you expected to happen.
-
-**Screenshots**
-If applicable, add screenshots to help explain your problem.
-
-**Additional context**
-Add any other context about the problem here.
-e.g. code snippet to reproduce the issue.
-e.g. stack trace, memory dump, debugger log, and many etc.
-
-<!-- For general inquiries, please post in [FreeRTOS forum](https://forums.FreeRTOS.org) for community support. -->

.github/ISSUE_TEMPLATE/config.yml

@@ -1,5 +0,0 @@
-blank_issues_enabled: false
-contact_links:
-  - name: FreeRTOS Community Support Forum
-    url: https://forums.freertos.org/
-    about: Please ask and answer questions about FreeRTOS here.

.github/ISSUE_TEMPLATE/documentation-issue.md

@@ -1,23 +0,0 @@
----
-name: Documentation issue
-about: Create a report to help us improve our documentation.
-title: "[DOC]"
-labels: documentation
-assignees: ''
-
----
-
-**Describe the issue**
-Please describe the issue and expected clarification in concise language.
-
-**Reference**
-Please attach the URL at which you are experiencing the issue.
-
-**Screenshot**
-If applicable, please attach screenshot.
-
-**Browser**
-- Browser: [e.g. Chrome]
-- Version: [e.g. 80.0.3987.132]
-
-<!-- For general inquiries, please post in [FreeRTOS forum](https://forums.FreeRTOS.org) for community support. -->

.github/ISSUE_TEMPLATE/feature_request.md

@@ -1,30 +0,0 @@
----
-name: Feature request
-about: Suggest a new feature for this project
-title: "[Feature Request] <replace with your title>"
-labels: enhancement
-assignees: ''
-
----
-
-**Is your feature request related to a problem? Please describe.**
-A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
-
-**Describe the solution you'd like**
-A clear and concise description of what you want to happen.
-
-**Describe alternatives you've considered**
-A clear and concise description of any alternative solutions or features you've considered.
-
-**How many devices will this feature impact?**
-Expected volume for your product.
-
-**What are your project timelines?**
-Timeline for milestones such as design completion, testing and validation, and production.
-
-**Additional context**
-Add any other context or screenshots about the feature request here.
-
-
-If you have the same (or similar) feature request, please upvote this issue with thumbs up 👍
-and use the comments section to provide answers to the questions above.

.github/SECURITY.md

@@ -1,5 +0,0 @@
-## Reporting a Vulnerability
-
-If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security 
-via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com. 
-Please do **not** create a public github issue.

.github/allowed_urls.txt

@@ -1,3 +0,0 @@
-https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166
-https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus
-https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads

.github/pull_request_process.md

@@ -1,115 +0,0 @@
-# Pull Request Process
-
-This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](CONTRIBUTING.md)
-
-## ****Terminologies****
-
-**FreeRTOS Partner Contributors**: These are selected developers and experts from community. 
-
-**FreeRTOS Team**: The FreeRTOS team consists of “AWS employees”. 
-
-**CODEOWNERS**: For all the FreeRTOS repositories, “FreeRTOS Team” and/or “FreeRTOS Partner contributors” will be CODEOWNER.
-
-**Contributor**: The Contributor is the person who submitted the pull request.
-
-**Assignee**: The Assignee is an AWS Employee who is responsible for identifying reviewers  and managing the PR. They track the progress of pull requests and ensure that they are reviewed and merged in a timely manner. 
-
-**Reviewer**: Reviewers are responsible for reviewing pull requests and providing feedback to the contributor. Two approving reviews, one of which must be from the CODEOWNER of the reposiroty, are required for a PR to be merged. 
-
-
-## ****Pull Request Life-Cycle****
-
-Once a pull request (PR) is submitted, it goes through the following stages:
-
-1. Open
-    1. The PR is created.
-    2. All the GitHub Actions pass and the PR is ready to be reviewed. 
-2. Triage
-    1. The PR is assigned to an assignee.
-    2. The assignee assigns a reviewer from the FreeRTOS Team to the PR.
-3. Review
-    1. The reviewer provides feedback and discusses open questions with the contributor, if needed.
-    2. If the contributor and the reviewer conclude, after discussion, that the PR will not be merged, then the PR is closed.
-    3. The PR contributor addresses the feedback and makes changes to the PR, if needed.
-    4. The reviewer approves the PR and assigns a second reviewer.
-4. Second Review
-    1. The second reviewer reviews the PR and provides feedback, if needed.
-    2. The PR contributor addresses the feedback and makes changes to the PR, if needed.
-    3. The second reviewer approves the PR.
-5. Testing
-    1. One of the reviewers tests the PR to ensure that it works correctly.
-6. Ready to Merge  
-   A PR becomes Ready to Merge when all the branch protection rules are satisfied. We have branch protection rules which require the following:
-    1. At least 2 reviews. 
-    2. One review from the CODEOWNER of the given repository. 
-    3. All PR checks must pass.
-7. Merge
-    1. The PR is merged.
-
-</br>
-
-The status of a PR is indicated through GitHub labels added by Reviewers/Assignees. The following are the most common status indicators: Triaged, Reviewer Assigned, Concept ACK/NACK, First Code Review In Progress, First Code Review Complete, Second Code Review In Progress, Second Code Review Complete, Testing In Progress and Testing Complete.
-
-Please note that we may decide to skip some stages depending on the type of PR. For example, a PR with a simple doc update will likely not go through all the above stages, however every PR is required to get approvals from 2 reviewers.
-
-The pictorial representation of our PR process is shown below.
-
-![PR Process](media/pr_process.png)
-
-
-</br>
-
-## **Turnaround Times**
-
-The length of time required to review a PR is unpredictable and varies from PR to PR since it depends on the complexity of the changes, availability of reviewers, and overall workload of the team. We generally attempt to resolve each PR in accordance with the timeframes below, excluding weekends and public holidays:
-
-* Triage: < 24 hours
-* Concept ACK/NACK: 1-2 weeks
-* Code Review: 1-2 weeks
-* Testing: 1-2 weeks
-
-
-## **Addressing the changes requested by reviewers**
-
-The author should address any review comments in 4 weeks or less. If the author is unable to address the comments in that time, we will do one of the following:
-
-* Make the required changes ourselves and merge the pull request.
-* Close the pull request.
-
-</br>
-
-### **Best Practices for Faster Reviews**
-
-Here are some best practices to follow so that your PR gets reviewed quickly. 
-
-1. If you plan to contribute a new feature to FreeRTOS, please get confirmation beforehand that the FreeRTOS team and community want, and will accept, this feature. This is true especially when you plan to make large or significant changes.  To get confirmation and feedback from FreeRTOS Team and  community, create a post in the FreeRTOS forums. 
-2. Smaller is better. Small, focused PR’s are reviewed more quickly and thoroughly, are simpler to rollback, and involve less wasted effort if rejected.  Avoid opening pull requests that span the whole repository.
-3. Don’t mix refactoring, bug fixes and feature development into a single PR. Lets say you are developing feature-x  and you come across poorly named variables or incomplete/incorrect comments. You should consider fixing those, but in a separate PR, not in the same PR as feature-x. 
-4. Comments matter. The code you develop will need to be maintained for a long time. Well placed comments provide context to your reviewers, maintainers and users, and also prevent them from misunderstanding the purpose of the code.  However, DO NOT add comments to explain things which are obvious by just glancing at the code. [Good Read: https://stackoverflow.blog/2021/12/23/best-practices-for-writing-code-comments/]
-5. Test your PR. In your PR, please accompany your changes with suitable unit tests and any other tests that will be helpful, and include descriptions of how to perform any manual tests. Instructions for unit tests can be found at [freertos.org](https://freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html#Testing) and [Github](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Test/CMock/Readme.md)
-
-
-**Push Back its ok:**
-Sometimes reviewers make mistakes. If a reviewer has requested you to make changes and you feel strongly about doing it a certain way, you are free to debate the merits of the requested change with the reviewer, while still following the code of conduct. You might be overruled, but you might also prevail. 
-
-**Be Pragmatic**
-Put a bit of thought into how your PR can be made easier to review and merge. No document can replace common sense and good taste. The best practices shared here and the contribution guidelines, if followed, will help you get your code reviewed and merged with less friction. 
-
-</br>
-
-### **Why is  my PR closed?** 
-
-Pull requests older than 120 days or not in-line with scope of the project will be closed. Exceptions can be made for pull requests that have active review comments, or that are awaiting other dependent pull requests. Closed pull requests are easy to recreate, and little work is lost by closing a pull request that is subsequently reopened. We want to limit the total number of pull requests in flight to:
-
-* Maintain a clean project
-* Remove old pull requests that would be difficult to rebase since the underlying code has changed over time
-* Encourage code velocity
-
-### **Why is my PR not getting reviewed/merged?**
-
-* It may be because of a feature freeze due to an upcoming release. During this time, only bug fixes are taken into consideration. If your pull request is a new feature, it will not be prioritised until after the release. Wait for the release.
-* It could be related to best practices (see contributing.md) not being followed. One common issue is that the pull request is too big to review. Let’s say you’ve touched 21 files and have 9347 insertions. When your would-be reviewers pull up the diffs, they run away - this pull request is going to take a few hours to review and they don’t have a few hours right now. They’ll get to it later, just as soon as they have more free time (ha!).
-* If you think the above two situations are not the reason, and you are not getting some pull request love,  please drop a couple of reminders on the PR comments. If everything else fails, please create a post on FreeRTOS forums with link to PR. 
-
-
-

.github/pull_request_template.md

@@ -1,23 +0,0 @@
-<!--- Title -->
-
-Description
------------
-<!--- Describe your changes in detail. -->
-
-Test Steps
------------
-<!-- Describe the steps to reproduce. -->
-
-Checklist:
-----------
-<!--- Go over all the following points, and put an `x` in all the boxes that apply. -->
-<!--- If you're unsure about any of these, don't hesitate to ask. We're here to help! -->
-- [ ] I have tested my changes. No regression in existing tests.
-- [ ] I have modified and/or added unit-tests to cover the code changes in this Pull Request.
-
-Related Issue
------------
-<!-- If any, please provide issue ID. -->
-
-
-By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

.github/scripts/find_replace.sh

@@ -1,6 +0,0 @@
-#!/bin/bash
-old_text=$1
-new_text=$2
-echo "Old text: ${old_text}"
-echo "New text: ${new_text}"
-grep -rl "${old_text}" . | xargs gsed -i -e '1h;2,$H;$!d;g' -e "s/${old_text}/${new_text}/g"

.github/scripts/kernel_checker.py

@@ -1,247 +0,0 @@
-#!/usr/bin/env python3
-#/*
-# * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-# * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-# *
-# * SPDX-License-Identifier: MIT
-# *
-# * Permission is hereby granted, free of charge, to any person obtaining a copy of
-# * this software and associated documentation files (the "Software"), to deal in
-# * the Software without restriction, including without limitation the rights to
-# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-# * the Software, and to permit persons to whom the Software is furnished to do so,
-# * subject to the following conditions:
-# *
-# * The above copyright notice and this permission notice shall be included in all
-# * copies or substantial portions of the Software.
-# *
-# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-# *
-# * https://www.FreeRTOS.org
-# * https://github.com/FreeRTOS
-# *
-# */
-
-import os
-import re
-from common.header_checker import HeaderChecker
-
-#--------------------------------------------------------------------------------------------------
-#                                            CONFIG
-#--------------------------------------------------------------------------------------------------
-KERNEL_IGNORED_FILES = [
-    'FreeRTOS-openocd.c',
-    'Makefile',
-    '.DS_Store',
-    'cspell.config.yaml',
-    '.clang-format'
-]
-
-KERNEL_IGNORED_EXTENSIONS = [
-    '.yml',
-    '.css',
-    '.idx',
-    '.md',
-    '.url',
-    '.sty',
-    '.0-rc2',
-    '.s82',
-    '.js',
-    '.out',
-    '.pack',
-    '.2',
-    '.1-kernel-only',
-    '.0-kernel-only',
-    '.0-rc1',
-    '.readme',
-    '.tex',
-    '.png',
-    '.bat',
-    '.sh',
-    '.txt',
-    '.cmake',
-    '.config'
-]
-
-KERNEL_ASM_EXTENSIONS = [
-    '.s',
-    '.S',
-    '.src',
-    '.inc',
-    '.s26',
-    '.s43',
-    '.s79',
-    '.s85',
-    '.s87',
-    '.s90',
-    '.asm',
-    '.h'
-]
-
-KERNEL_PY_EXTENSIONS = [
-    '.py'
-]
-
-KERNEL_IGNORED_PATTERNS = [
-    r'.*\.git.*',
-    r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*',
-    r'.*portable/GCC/ARM7_AT91SAM7S/.*',
-    r'.*portable/MPLAB/PIC18F/stdio.h',
-    r'.*portable/ThirdParty/xClang/XCOREAI/*',
-    r'.*IAR/ARM_C*',
-    r'.*IAR/78K0R/*',
-    r'.*CCS/MSP430X/*',
-    r'.*portable/template/*',
-    r'.*template_configuration/*'
-]
-
-KERNEL_THIRD_PARTY_PATTERNS = [
-    r'.*portable/ThirdParty/GCC/Posix/port*',
-    r'.*portable/ThirdParty/*',
-    r'.*portable/IAR/AVR32_UC3/.*',
-    r'.*portable/GCC/AVR32_UC3/.*',
-]
-
-KERNEL_ARM_COLLAB_FILES_PATTERNS = [
-    r'.*portable/ARMv8M/*',
-    r'.*portable/.*/ARM_CM23*',
-    r'.*portable/.*/ARM_CM33*',
-    r'.*portable/.*/ARM_CM35*',
-    r'.*portable/.*/ARM_CM55*',
-    r'.*portable/.*/ARM_CM85*',
-]
-
-KERNEL_HEADER = [
-    '/*\n',
-    ' * FreeRTOS Kernel <DEVELOPMENT BRANCH>\n',
-    ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n',
-    ' *\n',
-    ' * SPDX-License-Identifier: MIT\n',
-    ' *\n',
-    ' * Permission is hereby granted, free of charge, to any person obtaining a copy of\n',
-    ' * this software and associated documentation files (the "Software"), to deal in\n',
-    ' * the Software without restriction, including without limitation the rights to\n',
-    ' * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n',
-    ' * the Software, and to permit persons to whom the Software is furnished to do so,\n',
-    ' * subject to the following conditions:\n',
-    ' *\n',
-    ' * The above copyright notice and this permission notice shall be included in all\n',
-    ' * copies or substantial portions of the Software.\n',
-    ' *\n',
-    ' * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n',
-    ' * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n',
-    ' * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n',
-    ' * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n',
-    ' * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n',
-    ' * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n',
-    ' *\n',
-    ' * https://www.FreeRTOS.org\n',
-    ' * https://github.com/FreeRTOS\n',
-    ' *\n',
-    ' */\n',
-]
-
-
-FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
-
-FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
-                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d Arm Limited and/or its affiliates( \*\/)?$)|" + \
-                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm.com>( \*\/)?$)"
-
-
-class KernelHeaderChecker(HeaderChecker):
-    def __init__(
-        self,
-        header,
-        padding=1000,
-        ignored_files=None,
-        ignored_ext=None,
-        ignored_patterns=None,
-        py_ext=None,
-        asm_ext=None,
-        third_party_patterns=None,
-        copyright_regex = None
-    ):
-        super().__init__(header, padding, ignored_files, ignored_ext, ignored_patterns,
-                         py_ext, asm_ext, third_party_patterns, copyright_regex)
-
-        self.armCollabRegex = re.compile(FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX)
-
-        self.armCollabFilesPatternList = []
-        for pattern in KERNEL_ARM_COLLAB_FILES_PATTERNS:
-            self.armCollabFilesPatternList.append(re.compile(pattern))
-
-    def isArmCollabFile(self, path):
-        for pattern in self.armCollabFilesPatternList:
-            if pattern.match(path):
-                return True
-        return False
-
-    def checkArmCollabFile(self, path):
-        isValid = False
-        file_ext = os.path.splitext(path)[-1]
-
-        with open(path, encoding="utf-8", errors="ignore") as file:
-            chunk = file.read(len("".join(self.header)) + self.padding)
-            lines = [("%s\n" % line) for line in chunk.strip().splitlines()][
-                : len(self.header) + 2
-            ]
-            if (len(lines) > 0) and (lines[0].find("#!") == 0):
-                lines.remove(lines[0])
-
-        # Split lines in sections.
-        headers = dict()
-        headers["text"] = []
-        headers["copyright"] = []
-        headers["spdx"] = []
-        for line in lines:
-            if self.armCollabRegex.match(line):
-                headers["copyright"].append(line)
-            elif "SPDX-License-Identifier:" in line:
-                headers["spdx"].append(line)
-            else:
-                headers["text"].append(line)
-
-        text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"])
-        spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"])
-
-        if text_equal and spdx_equal and len(headers["copyright"]) == 3:
-            isValid = True
-
-        return isValid
-
-    def customCheck(self, path):
-        isValid = False
-        if self.isArmCollabFile(path):
-            isValid = self.checkArmCollabFile(path)
-        return isValid
-
-
-def main():
-    parser = HeaderChecker.configArgParser()
-    args   = parser.parse_args()
-
-    # Configure the checks then run
-    checker = KernelHeaderChecker(KERNEL_HEADER,
-                                  copyright_regex=FREERTOS_COPYRIGHT_REGEX,
-                                  ignored_files=KERNEL_IGNORED_FILES,
-                                  ignored_ext=KERNEL_IGNORED_EXTENSIONS,
-                                  ignored_patterns=KERNEL_IGNORED_PATTERNS,
-                                  third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS,
-                                  py_ext=KERNEL_PY_EXTENSIONS,
-                                  asm_ext=KERNEL_ASM_EXTENSIONS)
-    checker.ignoreFile(os.path.split(__file__)[-1])
-
-    rc = checker.processArgs(args)
-    if rc:
-        checker.showHelp(__file__)
-
-    return rc
-
-if __name__ == '__main__':
-    exit(main())

.github/scripts/manifest_updater.py

@@ -1,32 +0,0 @@
-#!/usr/bin/env python3
-import os
-import argparse
-
-THIS_FILE_PATH = os.path.dirname(os.path.abspath(__file__))
-MANIFEST_FILE = os.path.join(THIS_FILE_PATH, '..', '..', 'manifest.yml')
-
-def update_manifest_file(new_version_number):
-    updated_lines = []
-    with open(MANIFEST_FILE, 'r') as f:
-        for line in f:
-            line = line.strip()
-            if line.startswith('version'):
-                updated_lines.append(f'version: "V{new_version_number}"\n')
-            else:
-                updated_lines.append(f'{line}\n')
-
-    with open(MANIFEST_FILE, 'w') as f:
-        f.writelines(updated_lines)
-
-def parse_args():
-    parser = argparse.ArgumentParser()
-    parser.add_argument('-v', '--version', required=True, help='New version number.')
-    args = parser.parse_args()
-    return args
-
-def main():
-    args = parse_args()
-    update_manifest_file(args.version)
-
-if __name__ == '__main__':
-    main()

.github/third_party_tools.md

@@ -1,14 +0,0 @@
-Note that these tools are provided by different vendors and not by the FreeRTOS
-team.
-
-## Tracing Tools
-| Tool | Website | Getting Started |
-|------|---------|-----------------|
-| Tracelyzer | [Link](https://percepio.com/tracealyzer/freertostrace/) | [Link](https://percepio.com/getstarted/latest/html/freertos.html) |
-| SystemView | [Link](https://www.segger.com/products/development-tools/systemview/) | [Link](https://wiki.segger.com/FreeRTOS_with_SystemView) |
-
-## Static Code Analysis Tools
-| Tool | Website | Getting Started |
-|------|---------|-----------------|
-| Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel/blob/main/examples/codesonar/README.md) |
-| Coverity | [Link](https://www.blackduck.com/static-analysis-tools-sast/coverity.html) | [Link](../examples/coverity/README.md) |

.github/uncrustify.cfg

@@ -1,673 +0,0 @@
-# Uncrustify-0.69.0
-
-newlines                        = auto     # lf/crlf/cr/auto
-input_tab_size                  = 4        # unsigned number
-output_tab_size                 = 4        # unsigned number
-string_escape_char              = 92       # unsigned number
-string_escape_char2             = 0        # unsigned number
-string_replace_tab_chars        = false    # true/false
-tok_split_gte                   = false    # true/false
-disable_processing_cmt          = " *INDENT-OFF*"      # string
-enable_processing_cmt           = " *INDENT-ON*"     # string
-enable_digraphs                 = false    # true/false
-utf8_bom                        = ignore   # ignore/add/remove/force
-utf8_byte                       = false    # true/false
-utf8_force                      = false    # true/false
-sp_arith                        = force    # ignore/add/remove/force
-sp_arith_additive               = ignore   # ignore/add/remove/force
-sp_assign                       = force    # ignore/add/remove/force
-sp_cpp_lambda_assign            = ignore   # ignore/add/remove/force
-sp_cpp_lambda_paren             = ignore   # ignore/add/remove/force
-sp_assign_default               = force    # ignore/add/remove/force
-sp_before_assign                = force    # ignore/add/remove/force
-sp_after_assign                 = force    # ignore/add/remove/force
-sp_enum_paren                   = ignore   # ignore/add/remove/force
-sp_enum_assign                  = force    # ignore/add/remove/force
-sp_enum_before_assign           = force    # ignore/add/remove/force
-sp_enum_after_assign            = force    # ignore/add/remove/force
-sp_enum_colon                   = ignore   # ignore/add/remove/force
-sp_pp_concat                    = add      # ignore/add/remove/force
-sp_pp_stringify                 = add      # ignore/add/remove/force
-sp_before_pp_stringify          = ignore   # ignore/add/remove/force
-sp_bool                         = force    # ignore/add/remove/force
-sp_compare                      = force    # ignore/add/remove/force
-sp_inside_paren                 = force    # ignore/add/remove/force
-sp_paren_paren                  = force    # ignore/add/remove/force
-sp_cparen_oparen                = ignore   # ignore/add/remove/force
-sp_balance_nested_parens        = false    # true/false
-sp_paren_brace                  = force    # ignore/add/remove/force
-sp_brace_brace                  = ignore   # ignore/add/remove/force
-sp_before_ptr_star              = force    # ignore/add/remove/force
-sp_before_unnamed_ptr_star      = force    # ignore/add/remove/force
-sp_between_ptr_star             = remove   # ignore/add/remove/force
-sp_after_ptr_star               = force    # ignore/add/remove/force
-sp_after_ptr_block_caret        = ignore   # ignore/add/remove/force
-sp_after_ptr_star_qualifier     = ignore   # ignore/add/remove/force
-sp_after_ptr_star_func          = ignore   # ignore/add/remove/force
-sp_ptr_star_paren               = ignore   # ignore/add/remove/force
-sp_before_ptr_star_func         = ignore   # ignore/add/remove/force
-sp_before_byref                 = force    # ignore/add/remove/force
-sp_before_unnamed_byref         = ignore   # ignore/add/remove/force
-sp_after_byref                  = remove   # ignore/add/remove/force
-sp_after_byref_func             = remove   # ignore/add/remove/force
-sp_before_byref_func            = ignore   # ignore/add/remove/force
-sp_after_type                   = force    # ignore/add/remove/force
-sp_after_decltype               = ignore   # ignore/add/remove/force
-sp_before_template_paren        = ignore   # ignore/add/remove/force
-sp_template_angle               = ignore   # ignore/add/remove/force
-sp_before_angle                 = remove   # ignore/add/remove/force
-sp_inside_angle                 = remove   # ignore/add/remove/force
-sp_inside_angle_empty           = ignore   # ignore/add/remove/force
-sp_angle_colon                  = ignore   # ignore/add/remove/force
-sp_after_angle                  = force    # ignore/add/remove/force
-sp_angle_paren                  = ignore   # ignore/add/remove/force
-sp_angle_paren_empty            = ignore   # ignore/add/remove/force
-sp_angle_word                   = ignore   # ignore/add/remove/force
-sp_angle_shift                  = add      # ignore/add/remove/force
-sp_permit_cpp11_shift           = false    # true/false
-sp_before_sparen                = remove   # ignore/add/remove/force
-sp_inside_sparen                = force    # ignore/add/remove/force
-sp_inside_sparen_open           = ignore   # ignore/add/remove/force
-sp_inside_sparen_close          = ignore   # ignore/add/remove/force
-sp_after_sparen                 = force    # ignore/add/remove/force
-sp_sparen_brace                 = force    # ignore/add/remove/force
-sp_invariant_paren              = ignore   # ignore/add/remove/force
-sp_after_invariant_paren        = ignore   # ignore/add/remove/force
-sp_special_semi                 = ignore   # ignore/add/remove/force
-sp_before_semi                  = remove   # ignore/add/remove/force
-sp_before_semi_for              = remove   # ignore/add/remove/force
-sp_before_semi_for_empty        = add      # ignore/add/remove/force
-sp_after_semi                   = add      # ignore/add/remove/force
-sp_after_semi_for               = force    # ignore/add/remove/force
-sp_after_semi_for_empty         = force    # ignore/add/remove/force
-sp_before_square                = remove   # ignore/add/remove/force
-sp_before_squares               = remove   # ignore/add/remove/force
-sp_cpp_before_struct_binding    = ignore   # ignore/add/remove/force
-sp_inside_square                = force    # ignore/add/remove/force
-sp_inside_square_oc_array       = ignore   # ignore/add/remove/force
-sp_after_comma                  = force    # ignore/add/remove/force
-sp_before_comma                 = remove   # ignore/add/remove/force
-sp_after_mdatype_commas         = ignore   # ignore/add/remove/force
-sp_before_mdatype_commas        = ignore   # ignore/add/remove/force
-sp_between_mdatype_commas       = ignore   # ignore/add/remove/force
-sp_paren_comma                  = force    # ignore/add/remove/force
-sp_before_ellipsis              = ignore   # ignore/add/remove/force
-sp_type_ellipsis                = ignore   # ignore/add/remove/force
-sp_type_question                = ignore   # ignore/add/remove/force
-sp_paren_ellipsis               = ignore   # ignore/add/remove/force
-sp_paren_qualifier              = ignore   # ignore/add/remove/force
-sp_paren_noexcept               = ignore   # ignore/add/remove/force
-sp_after_class_colon            = ignore   # ignore/add/remove/force
-sp_before_class_colon           = ignore   # ignore/add/remove/force
-sp_after_constr_colon           = ignore   # ignore/add/remove/force
-sp_before_constr_colon          = ignore   # ignore/add/remove/force
-sp_before_case_colon            = remove   # ignore/add/remove/force
-sp_after_operator               = ignore   # ignore/add/remove/force
-sp_after_operator_sym           = ignore   # ignore/add/remove/force
-sp_after_operator_sym_empty     = ignore   # ignore/add/remove/force
-sp_after_cast                   = force    # ignore/add/remove/force
-sp_inside_paren_cast            = force    # ignore/add/remove/force
-sp_cpp_cast_paren               = ignore   # ignore/add/remove/force
-sp_sizeof_paren                 = remove   # ignore/add/remove/force
-sp_sizeof_ellipsis              = ignore   # ignore/add/remove/force
-sp_sizeof_ellipsis_paren        = ignore   # ignore/add/remove/force
-sp_decltype_paren               = ignore   # ignore/add/remove/force
-sp_after_tag                    = ignore   # ignore/add/remove/force
-sp_inside_braces_enum           = force    # ignore/add/remove/force
-sp_inside_braces_struct         = force    # ignore/add/remove/force
-sp_inside_braces_oc_dict        = ignore   # ignore/add/remove/force
-sp_after_type_brace_init_lst_open = ignore   # ignore/add/remove/force
-sp_before_type_brace_init_lst_close = ignore   # ignore/add/remove/force
-sp_inside_type_brace_init_lst   = ignore   # ignore/add/remove/force
-sp_inside_braces                = force    # ignore/add/remove/force
-sp_inside_braces_empty          = remove   # ignore/add/remove/force
-sp_type_func                    = force    # ignore/add/remove/force
-sp_type_brace_init_lst          = ignore   # ignore/add/remove/force
-sp_func_proto_paren             = remove   # ignore/add/remove/force
-sp_func_proto_paren_empty       = ignore   # ignore/add/remove/force
-sp_func_def_paren               = remove   # ignore/add/remove/force
-sp_func_def_paren_empty         = ignore   # ignore/add/remove/force
-sp_inside_fparens               = remove   # ignore/add/remove/force
-sp_inside_fparen                = force    # ignore/add/remove/force
-sp_inside_tparen                = ignore   # ignore/add/remove/force
-sp_after_tparen_close           = ignore   # ignore/add/remove/force
-sp_square_fparen                = ignore   # ignore/add/remove/force
-sp_fparen_brace                 = add      # ignore/add/remove/force
-sp_fparen_brace_initializer     = ignore   # ignore/add/remove/force
-sp_fparen_dbrace                = ignore   # ignore/add/remove/force
-sp_func_call_paren              = remove   # ignore/add/remove/force
-sp_func_call_paren_empty        = ignore   # ignore/add/remove/force
-sp_func_call_user_paren         = ignore   # ignore/add/remove/force
-sp_func_call_user_inside_fparen = ignore   # ignore/add/remove/force
-sp_func_call_user_paren_paren   = ignore   # ignore/add/remove/force
-sp_func_class_paren             = remove   # ignore/add/remove/force
-sp_func_class_paren_empty       = ignore   # ignore/add/remove/force
-sp_return_paren                 = remove   # ignore/add/remove/force
-sp_return_brace                 = ignore   # ignore/add/remove/force
-sp_attribute_paren              = remove   # ignore/add/remove/force
-sp_defined_paren                = remove   # ignore/add/remove/force
-sp_throw_paren                  = ignore   # ignore/add/remove/force
-sp_after_throw                  = ignore   # ignore/add/remove/force
-sp_catch_paren                  = ignore   # ignore/add/remove/force
-sp_oc_catch_paren               = ignore   # ignore/add/remove/force
-sp_oc_classname_paren           = ignore   # ignore/add/remove/force
-sp_version_paren                = ignore   # ignore/add/remove/force
-sp_scope_paren                  = ignore   # ignore/add/remove/force
-sp_super_paren                  = remove   # ignore/add/remove/force
-sp_this_paren                   = remove   # ignore/add/remove/force
-sp_macro                        = force    # ignore/add/remove/force
-sp_macro_func                   = force    # ignore/add/remove/force
-sp_else_brace                   = ignore   # ignore/add/remove/force
-sp_brace_else                   = ignore   # ignore/add/remove/force
-sp_brace_typedef                = force    # ignore/add/remove/force
-sp_catch_brace                  = ignore   # ignore/add/remove/force
-sp_oc_catch_brace               = ignore   # ignore/add/remove/force
-sp_brace_catch                  = ignore   # ignore/add/remove/force
-sp_oc_brace_catch               = ignore   # ignore/add/remove/force
-sp_finally_brace                = ignore   # ignore/add/remove/force
-sp_brace_finally                = ignore   # ignore/add/remove/force
-sp_try_brace                    = ignore   # ignore/add/remove/force
-sp_getset_brace                 = ignore   # ignore/add/remove/force
-sp_word_brace                   = add      # ignore/add/remove/force
-sp_word_brace_ns                = add      # ignore/add/remove/force
-sp_before_dc                    = remove   # ignore/add/remove/force
-sp_after_dc                     = remove   # ignore/add/remove/force
-sp_d_array_colon                = ignore   # ignore/add/remove/force
-sp_not                          = remove   # ignore/add/remove/force
-sp_inv                          = remove   # ignore/add/remove/force
-sp_addr                         = remove   # ignore/add/remove/force
-sp_member                       = remove   # ignore/add/remove/force
-sp_deref                        = remove   # ignore/add/remove/force
-sp_sign                         = remove   # ignore/add/remove/force
-sp_incdec                       = remove   # ignore/add/remove/force
-sp_before_nl_cont               = add      # ignore/add/remove/force
-sp_after_oc_scope               = ignore   # ignore/add/remove/force
-sp_after_oc_colon               = ignore   # ignore/add/remove/force
-sp_before_oc_colon              = ignore   # ignore/add/remove/force
-sp_after_oc_dict_colon          = ignore   # ignore/add/remove/force
-sp_before_oc_dict_colon         = ignore   # ignore/add/remove/force
-sp_after_send_oc_colon          = ignore   # ignore/add/remove/force
-sp_before_send_oc_colon         = ignore   # ignore/add/remove/force
-sp_after_oc_type                = ignore   # ignore/add/remove/force
-sp_after_oc_return_type         = ignore   # ignore/add/remove/force
-sp_after_oc_at_sel              = ignore   # ignore/add/remove/force
-sp_after_oc_at_sel_parens       = ignore   # ignore/add/remove/force
-sp_inside_oc_at_sel_parens      = ignore   # ignore/add/remove/force
-sp_before_oc_block_caret        = ignore   # ignore/add/remove/force
-sp_after_oc_block_caret         = ignore   # ignore/add/remove/force
-sp_after_oc_msg_receiver        = ignore   # ignore/add/remove/force
-sp_after_oc_property            = ignore   # ignore/add/remove/force
-sp_after_oc_synchronized        = ignore   # ignore/add/remove/force
-sp_cond_colon                   = force    # ignore/add/remove/force
-sp_cond_colon_before            = ignore   # ignore/add/remove/force
-sp_cond_colon_after             = ignore   # ignore/add/remove/force
-sp_cond_question                = force    # ignore/add/remove/force
-sp_cond_question_before         = ignore   # ignore/add/remove/force
-sp_cond_question_after          = ignore   # ignore/add/remove/force
-sp_cond_ternary_short           = ignore   # ignore/add/remove/force
-sp_case_label                   = force    # ignore/add/remove/force
-sp_range                        = ignore   # ignore/add/remove/force
-sp_after_for_colon              = ignore   # ignore/add/remove/force
-sp_before_for_colon             = ignore   # ignore/add/remove/force
-sp_extern_paren                 = ignore   # ignore/add/remove/force
-sp_cmt_cpp_start                = ignore   # ignore/add/remove/force
-sp_cmt_cpp_doxygen              = false    # true/false
-sp_cmt_cpp_qttr                 = false    # true/false
-sp_endif_cmt                    = force    # ignore/add/remove/force
-sp_after_new                    = ignore   # ignore/add/remove/force
-sp_between_new_paren            = ignore   # ignore/add/remove/force
-sp_after_newop_paren            = ignore   # ignore/add/remove/force
-sp_inside_newop_paren           = ignore   # ignore/add/remove/force
-sp_inside_newop_paren_open      = ignore   # ignore/add/remove/force
-sp_inside_newop_paren_close     = ignore   # ignore/add/remove/force
-sp_before_tr_emb_cmt            = force    # ignore/add/remove/force
-sp_num_before_tr_emb_cmt        = 1        # unsigned number
-sp_annotation_paren             = ignore   # ignore/add/remove/force
-sp_skip_vbrace_tokens           = false    # true/false
-sp_after_noexcept               = ignore   # ignore/add/remove/force
-sp_vala_after_translation       = ignore   # ignore/add/remove/force
-force_tab_after_define          = false    # true/false
-indent_columns                  = 4        # unsigned number
-indent_continue                 = 0        # number
-indent_continue_class_head      = 0        # unsigned number
-indent_single_newlines          = false    # true/false
-indent_param                    = 0        # unsigned number
-indent_with_tabs                = 0        # unsigned number
-indent_cmt_with_tabs            = false    # true/false
-indent_align_string             = true     # true/false
-indent_xml_string               = 0        # unsigned number
-indent_brace                    = 0        # unsigned number
-indent_braces                   = false    # true/false
-indent_braces_no_func           = false    # true/false
-indent_braces_no_class          = false    # true/false
-indent_braces_no_struct         = false    # true/false
-indent_brace_parent             = false    # true/false
-indent_paren_open_brace         = false    # true/false
-indent_cs_delegate_brace        = false    # true/false
-indent_cs_delegate_body         = false    # true/false
-indent_namespace                = false    # true/false
-indent_namespace_single_indent  = false    # true/false
-indent_namespace_level          = 0        # unsigned number
-indent_namespace_limit          = 0        # unsigned number
-indent_extern                   = false    # true/false
-indent_class                    = true     # true/false
-indent_class_colon              = true     # true/false
-indent_class_on_colon           = false    # true/false
-indent_constr_colon             = false    # true/false
-indent_ctor_init_leading        = 2        # unsigned number
-indent_ctor_init                = 0        # number
-indent_else_if                  = false    # true/false
-indent_var_def_blk              = 0        # number
-indent_var_def_cont             = false    # true/false
-indent_shift                    = false    # true/false
-indent_func_def_force_col1      = false    # true/false
-indent_func_call_param          = false    # true/false
-indent_func_def_param           = false    # true/false
-indent_func_proto_param         = false    # true/false
-indent_func_class_param         = false    # true/false
-indent_func_ctor_var_param      = false    # true/false
-indent_template_param           = false    # true/false
-indent_func_param_double        = false    # true/false
-indent_func_const               = 0        # unsigned number
-indent_func_throw               = 0        # unsigned number
-indent_member                   = 3        # unsigned number
-indent_member_single            = false    # true/false
-indent_sing_line_comments       = 0        # unsigned number
-indent_relative_single_line_comments = false    # true/false
-indent_switch_case              = 4        # unsigned number
-indent_switch_pp                = true     # true/false
-indent_case_shift               = 0        # unsigned number
-indent_case_brace               = 3        # number
-indent_col1_comment             = false    # true/false
-indent_col1_multi_string_literal = false    # true/false
-indent_label                    = 1        # number
-indent_access_spec              = 1        # number
-indent_access_spec_body         = false    # true/false
-indent_paren_nl                 = false    # true/false
-indent_paren_close              = 0        # unsigned number
-indent_paren_after_func_def     = false    # true/false
-indent_paren_after_func_decl    = false    # true/false
-indent_paren_after_func_call    = false    # true/false
-indent_comma_paren              = false    # true/false
-indent_bool_paren               = false    # true/false
-indent_semicolon_for_paren      = false    # true/false
-indent_first_bool_expr          = false    # true/false
-indent_first_for_expr           = false    # true/false
-indent_square_nl                = false    # true/false
-indent_preserve_sql             = false    # true/false
-indent_align_assign             = true     # true/false
-indent_align_paren              = true     # true/false
-indent_oc_block                 = false    # true/false
-indent_oc_block_msg             = 0        # unsigned number
-indent_oc_msg_colon             = 0        # unsigned number
-indent_oc_msg_prioritize_first_colon = true     # true/false
-indent_oc_block_msg_xcode_style = false    # true/false
-indent_oc_block_msg_from_keyword = false    # true/false
-indent_oc_block_msg_from_colon  = false    # true/false
-indent_oc_block_msg_from_caret  = false    # true/false
-indent_oc_block_msg_from_brace  = false    # true/false
-indent_min_vbrace_open          = 0        # unsigned number
-indent_vbrace_open_on_tabstop   = false    # true/false
-indent_token_after_brace        = true     # true/false
-indent_cpp_lambda_body          = false    # true/false
-indent_using_block              = true     # true/false
-indent_ternary_operator         = 0        # unsigned number
-indent_off_after_return_new     = false    # true/false
-indent_single_after_return      = false    # true/false
-indent_ignore_asm_block         = false    # true/false
-nl_collapse_empty_body          = false    # true/false
-nl_assign_leave_one_liners      = true     # true/false
-nl_class_leave_one_liners       = true     # true/false
-nl_enum_leave_one_liners        = false    # true/false
-nl_getset_leave_one_liners      = false    # true/false
-nl_cs_property_leave_one_liners = false    # true/false
-nl_func_leave_one_liners        = false    # true/false
-nl_cpp_lambda_leave_one_liners  = false    # true/false
-nl_if_leave_one_liners          = false    # true/false
-nl_while_leave_one_liners       = false    # true/false
-nl_for_leave_one_liners         = false    # true/false
-nl_oc_msg_leave_one_liner       = false    # true/false
-nl_oc_mdef_brace                = ignore   # ignore/add/remove/force
-nl_oc_block_brace               = ignore   # ignore/add/remove/force
-nl_oc_interface_brace           = ignore   # ignore/add/remove/force
-nl_oc_implementation_brace      = ignore   # ignore/add/remove/force
-nl_start_of_file                = remove   # ignore/add/remove/force
-nl_start_of_file_min            = 0        # unsigned number
-nl_end_of_file                  = force    # ignore/add/remove/force
-nl_end_of_file_min              = 1        # unsigned number
-nl_assign_brace                 = add      # ignore/add/remove/force
-nl_assign_square                = ignore   # ignore/add/remove/force
-nl_tsquare_brace                = ignore   # ignore/add/remove/force
-nl_after_square_assign          = ignore   # ignore/add/remove/force
-nl_fcall_brace                  = add      # ignore/add/remove/force
-nl_enum_brace                   = force    # ignore/add/remove/force
-nl_enum_class                   = ignore   # ignore/add/remove/force
-nl_enum_class_identifier        = ignore   # ignore/add/remove/force
-nl_enum_identifier_colon        = ignore   # ignore/add/remove/force
-nl_enum_colon_type              = ignore   # ignore/add/remove/force
-nl_struct_brace                 = force    # ignore/add/remove/force
-nl_union_brace                  = force    # ignore/add/remove/force
-nl_if_brace                     = add      # ignore/add/remove/force
-nl_brace_else                   = add      # ignore/add/remove/force
-nl_elseif_brace                 = ignore   # ignore/add/remove/force
-nl_else_brace                   = add      # ignore/add/remove/force
-nl_else_if                      = ignore   # ignore/add/remove/force
-nl_before_if_closing_paren      = ignore   # ignore/add/remove/force
-nl_brace_finally                = ignore   # ignore/add/remove/force
-nl_finally_brace                = ignore   # ignore/add/remove/force
-nl_try_brace                    = ignore   # ignore/add/remove/force
-nl_getset_brace                 = force    # ignore/add/remove/force
-nl_for_brace                    = add      # ignore/add/remove/force
-nl_catch_brace                  = ignore   # ignore/add/remove/force
-nl_oc_catch_brace               = ignore   # ignore/add/remove/force
-nl_brace_catch                  = ignore   # ignore/add/remove/force
-nl_oc_brace_catch               = ignore   # ignore/add/remove/force
-nl_brace_square                 = ignore   # ignore/add/remove/force
-nl_brace_fparen                 = ignore   # ignore/add/remove/force
-nl_while_brace                  = add      # ignore/add/remove/force
-nl_scope_brace                  = ignore   # ignore/add/remove/force
-nl_unittest_brace               = ignore   # ignore/add/remove/force
-nl_version_brace                = ignore   # ignore/add/remove/force
-nl_using_brace                  = ignore   # ignore/add/remove/force
-nl_brace_brace                  = ignore   # ignore/add/remove/force
-nl_do_brace                     = add      # ignore/add/remove/force
-nl_brace_while                  = ignore   # ignore/add/remove/force
-nl_switch_brace                 = add      # ignore/add/remove/force
-nl_synchronized_brace           = ignore   # ignore/add/remove/force
-nl_multi_line_cond              = false    # true/false
-nl_multi_line_define            = true     # true/false
-nl_before_case                  = true     # true/false
-nl_after_case                   = true     # true/false
-nl_case_colon_brace             = ignore   # ignore/add/remove/force
-nl_before_throw                 = ignore   # ignore/add/remove/force
-nl_namespace_brace              = ignore   # ignore/add/remove/force
-nl_template_class               = ignore   # ignore/add/remove/force
-nl_class_brace                  = ignore   # ignore/add/remove/force
-nl_class_init_args              = ignore   # ignore/add/remove/force
-nl_constr_init_args             = ignore   # ignore/add/remove/force
-nl_enum_own_lines               = ignore   # ignore/add/remove/force
-nl_func_type_name               = remove   # ignore/add/remove/force
-nl_func_type_name_class         = ignore   # ignore/add/remove/force
-nl_func_class_scope             = ignore   # ignore/add/remove/force
-nl_func_scope_name              = ignore   # ignore/add/remove/force
-nl_func_proto_type_name         = remove   # ignore/add/remove/force
-nl_func_paren                   = remove   # ignore/add/remove/force
-nl_func_paren_empty             = ignore   # ignore/add/remove/force
-nl_func_def_paren               = remove   # ignore/add/remove/force
-nl_func_def_paren_empty         = ignore   # ignore/add/remove/force
-nl_func_call_paren              = ignore   # ignore/add/remove/force
-nl_func_call_paren_empty        = ignore   # ignore/add/remove/force
-nl_func_decl_start              = remove   # ignore/add/remove/force
-nl_func_def_start               = remove   # ignore/add/remove/force
-nl_func_decl_start_single       = ignore   # ignore/add/remove/force
-nl_func_def_start_single        = ignore   # ignore/add/remove/force
-nl_func_decl_start_multi_line   = false    # true/false
-nl_func_def_start_multi_line    = false    # true/false
-nl_func_decl_args               = add      # ignore/add/remove/force
-nl_func_def_args                = add      # ignore/add/remove/force
-nl_func_decl_args_multi_line    = false    # true/false
-nl_func_def_args_multi_line     = false    # true/false
-nl_func_decl_end                = remove   # ignore/add/remove/force
-nl_func_def_end                 = remove   # ignore/add/remove/force
-nl_func_decl_end_single         = ignore   # ignore/add/remove/force
-nl_func_def_end_single          = ignore   # ignore/add/remove/force
-nl_func_decl_end_multi_line     = false    # true/false
-nl_func_def_end_multi_line      = false    # true/false
-nl_func_decl_empty              = ignore   # ignore/add/remove/force
-nl_func_def_empty               = ignore   # ignore/add/remove/force
-nl_func_call_empty              = ignore   # ignore/add/remove/force
-nl_func_call_start              = ignore   # ignore/add/remove/force
-nl_func_call_start_multi_line   = false    # true/false
-nl_func_call_args_multi_line    = false    # true/false
-nl_func_call_end_multi_line     = false    # true/false
-nl_oc_msg_args                  = false    # true/false
-nl_fdef_brace                   = add      # ignore/add/remove/force
-nl_fdef_brace_cond              = ignore   # ignore/add/remove/force
-nl_cpp_ldef_brace               = ignore   # ignore/add/remove/force
-nl_return_expr                  = ignore   # ignore/add/remove/force
-nl_after_semicolon              = true     # true/false
-nl_paren_dbrace_open            = ignore   # ignore/add/remove/force
-nl_type_brace_init_lst          = ignore   # ignore/add/remove/force
-nl_type_brace_init_lst_open     = ignore   # ignore/add/remove/force
-nl_type_brace_init_lst_close    = ignore   # ignore/add/remove/force
-nl_after_brace_open             = true     # true/false
-nl_after_brace_open_cmt         = false    # true/false
-nl_after_vbrace_open            = false    # true/false
-nl_after_vbrace_open_empty      = false    # true/false
-nl_after_brace_close            = true     # true/false
-nl_after_vbrace_close           = false    # true/false
-nl_brace_struct_var             = ignore   # ignore/add/remove/force
-nl_define_macro                 = false    # true/false
-nl_squeeze_paren_close          = false    # true/false
-nl_squeeze_ifdef                = true     # true/false
-nl_squeeze_ifdef_top_level      = false    # true/false
-nl_before_if                    = force    # ignore/add/remove/force
-nl_after_if                     = force    # ignore/add/remove/force
-nl_before_for                   = force    # ignore/add/remove/force
-nl_after_for                    = force    # ignore/add/remove/force
-nl_before_while                 = force    # ignore/add/remove/force
-nl_after_while                  = force    # ignore/add/remove/force
-nl_before_switch                = force    # ignore/add/remove/force
-nl_after_switch                 = force    # ignore/add/remove/force
-nl_before_synchronized          = ignore   # ignore/add/remove/force
-nl_after_synchronized           = ignore   # ignore/add/remove/force
-nl_before_do                    = force    # ignore/add/remove/force
-nl_after_do                     = force    # ignore/add/remove/force
-nl_before_return                = false    # true/false
-nl_after_return                 = true     # true/false
-nl_ds_struct_enum_cmt           = false    # true/false
-nl_ds_struct_enum_close_brace   = false    # true/false
-nl_class_colon                  = ignore   # ignore/add/remove/force
-nl_constr_colon                 = ignore   # ignore/add/remove/force
-nl_namespace_two_to_one_liner   = false    # true/false
-nl_create_if_one_liner          = false    # true/false
-nl_create_for_one_liner         = false    # true/false
-nl_create_while_one_liner       = false    # true/false
-nl_create_func_def_one_liner    = false    # true/false
-nl_split_if_one_liner           = false    # true/false
-nl_split_for_one_liner          = false    # true/false
-nl_split_while_one_liner        = false    # true/false
-nl_max                          = 4        # unsigned number
-nl_max_blank_in_func            = 0        # unsigned number
-nl_before_func_body_proto       = 0        # unsigned number
-nl_before_func_body_def         = 0        # unsigned number
-nl_before_func_class_proto      = 0        # unsigned number
-nl_before_func_class_def        = 0        # unsigned number
-nl_after_func_proto             = 0        # unsigned number
-nl_after_func_proto_group       = 1        # unsigned number
-nl_after_func_class_proto       = 0        # unsigned number
-nl_after_func_class_proto_group = 0        # unsigned number
-nl_class_leave_one_liner_groups = false    # true/false
-nl_after_func_body              = 0        # unsigned number
-nl_after_func_body_class        = 2        # unsigned number
-nl_after_func_body_one_liner    = 0        # unsigned number
-nl_func_var_def_blk             = 1        # unsigned number
-nl_typedef_blk_start            = 0        # unsigned number
-nl_typedef_blk_end              = 0        # unsigned number
-nl_typedef_blk_in               = 0        # unsigned number
-nl_var_def_blk_start            = 0        # unsigned number
-nl_var_def_blk_end              = 0        # unsigned number
-nl_var_def_blk_in               = 0        # unsigned number
-nl_before_block_comment         = 2        # unsigned number
-nl_before_c_comment             = 0        # unsigned number
-nl_before_cpp_comment           = 0        # unsigned number
-nl_after_multiline_comment      = false    # true/false
-nl_after_label_colon            = false    # true/false
-nl_after_struct                 = 0        # unsigned number
-nl_before_class                 = 0        # unsigned number
-nl_after_class                  = 0        # unsigned number
-nl_before_access_spec           = 0        # unsigned number
-nl_after_access_spec            = 0        # unsigned number
-nl_comment_func_def             = 0        # unsigned number
-nl_after_try_catch_finally      = 0        # unsigned number
-nl_around_cs_property           = 0        # unsigned number
-nl_between_get_set              = 0        # unsigned number
-nl_property_brace               = ignore   # ignore/add/remove/force
-nl_inside_namespace             = 0        # unsigned number
-eat_blanks_after_open_brace     = true     # true/false
-eat_blanks_before_close_brace   = true     # true/false
-nl_remove_extra_newlines        = 0        # unsigned number
-nl_after_annotation             = ignore   # ignore/add/remove/force
-nl_between_annotation           = ignore   # ignore/add/remove/force
-pos_arith                       = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_assign                      = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_bool                        = trail    # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_compare                     = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_conditional                 = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_comma                       = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_enum_comma                  = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_class_comma                 = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_constr_comma                = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_class_colon                 = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-pos_constr_colon                = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
-code_width                      = 0        # unsigned number
-ls_for_split_full               = false    # true/false
-ls_func_split_full              = false    # true/false
-ls_code_width                   = false    # true/false
-align_keep_tabs                 = false    # true/false
-align_with_tabs                 = false    # true/false
-align_on_tabstop                = false    # true/false
-align_number_right              = false    # true/false
-align_keep_extra_space          = false    # true/false
-align_func_params               = false    # true/false
-align_func_params_span          = 0        # unsigned number
-align_func_params_thresh        = 0        # number
-align_func_params_gap           = 0        # unsigned number
-align_constr_value_span         = 0        # unsigned number
-align_constr_value_thresh       = 0        # number
-align_constr_value_gap          = 0        # unsigned number
-align_same_func_call_params     = false    # true/false
-align_same_func_call_params_span = 0        # unsigned number
-align_same_func_call_params_thresh = 0        # number
-align_var_def_span              = 0        # unsigned number
-align_var_def_star_style        = 0        # unsigned number
-align_var_def_amp_style         = 1        # unsigned number
-align_var_def_thresh            = 16       # number
-align_var_def_gap               = 0        # unsigned number
-align_var_def_colon             = false    # true/false
-align_var_def_colon_gap         = 0        # unsigned number
-align_var_def_attribute         = false    # true/false
-align_var_def_inline            = false    # true/false
-align_assign_span               = 0        # unsigned number
-align_assign_func_proto_span    = 0        # unsigned number
-align_assign_thresh             = 12       # number
-align_assign_decl_func          = 0        # unsigned number
-align_enum_equ_span             = 0        # unsigned number
-align_enum_equ_thresh           = 0        # number
-align_var_class_span            = 0        # unsigned number
-align_var_class_thresh          = 0        # number
-align_var_class_gap             = 0        # unsigned number
-align_var_struct_span           = 0        # unsigned number
-align_var_struct_thresh         = 0        # number
-align_var_struct_gap            = 0        # unsigned number
-align_struct_init_span          = 3        # unsigned number
-align_typedef_span              = 5        # unsigned number
-align_typedef_gap               = 3        # unsigned number
-align_typedef_func              = 0        # unsigned number
-align_typedef_star_style        = 1        # unsigned number
-align_typedef_amp_style         = 1        # unsigned number
-align_right_cmt_span            = 3        # unsigned number
-align_right_cmt_gap             = 0        # unsigned number
-align_right_cmt_mix             = false    # true/false
-align_right_cmt_same_level      = false    # true/false
-align_right_cmt_at_col          = 0        # unsigned number
-align_func_proto_span           = 0        # unsigned number
-align_func_proto_thresh         = 0        # number
-align_func_proto_gap            = 0        # unsigned number
-align_on_operator               = false    # true/false
-align_mix_var_proto             = false    # true/false
-align_single_line_func          = false    # true/false
-align_single_line_brace         = false    # true/false
-align_single_line_brace_gap     = 0        # unsigned number
-align_oc_msg_spec_span          = 0        # unsigned number
-align_nl_cont                   = true     # true/false
-align_pp_define_together        = false    # true/false
-align_pp_define_span            = 3        # unsigned number
-align_pp_define_gap             = 4        # unsigned number
-align_left_shift                = true     # true/false
-align_asm_colon                 = false    # true/false
-align_oc_msg_colon_span         = 0        # unsigned number
-align_oc_msg_colon_first        = false    # true/false
-align_oc_decl_colon             = false    # true/false
-cmt_width                       = 0        # unsigned number
-cmt_reflow_mode                 = 0        # unsigned number
-cmt_convert_tab_to_spaces       = false    # true/false
-cmt_indent_multi                = true     # true/false
-cmt_c_group                     = false    # true/false
-cmt_c_nl_start                  = false    # true/false
-cmt_c_nl_end                    = false    # true/false
-cmt_cpp_to_c                    = true     # true/false
-cmt_cpp_group                   = false    # true/false
-cmt_cpp_nl_start                = false    # true/false
-cmt_cpp_nl_end                  = false    # true/false
-cmt_star_cont                   = true     # true/false
-cmt_sp_before_star_cont         = 0        # unsigned number
-cmt_sp_after_star_cont          = 0        # unsigned number
-cmt_multi_check_last            = true     # true/false
-cmt_multi_first_len_minimum     = 4        # unsigned number
-cmt_insert_file_header          = ""         # string
-cmt_insert_file_footer          = ""         # string
-cmt_insert_func_header          = ""         # string
-cmt_insert_class_header         = ""         # string
-cmt_insert_oc_msg_header        = ""         # string
-cmt_insert_before_preproc       = false    # true/false
-cmt_insert_before_inlines       = true     # true/false
-cmt_insert_before_ctor_dtor     = false    # true/false
-mod_full_brace_do               = add      # ignore/add/remove/force
-mod_full_brace_for              = add      # ignore/add/remove/force
-mod_full_brace_function         = ignore   # ignore/add/remove/force
-mod_full_brace_if               = add      # ignore/add/remove/force
-mod_full_brace_if_chain         = false    # true/false
-mod_full_brace_if_chain_only    = false    # true/false
-mod_full_brace_while            = add      # ignore/add/remove/force
-mod_full_brace_using            = ignore   # ignore/add/remove/force
-mod_full_brace_nl               = 0        # unsigned number
-mod_full_brace_nl_block_rem_mlcond = false    # true/false
-mod_paren_on_return             = ignore   # ignore/add/remove/force
-mod_pawn_semicolon              = false    # true/false
-mod_full_paren_if_bool          = true     # true/false
-mod_remove_extra_semicolon      = true     # true/false
-mod_add_long_function_closebrace_comment = 0        # unsigned number
-mod_add_long_namespace_closebrace_comment = 0        # unsigned number
-mod_add_long_class_closebrace_comment = 0        # unsigned number
-mod_add_long_switch_closebrace_comment = 0        # unsigned number
-mod_add_long_ifdef_endif_comment = 10       # unsigned number
-mod_add_long_ifdef_else_comment = 10       # unsigned number
-mod_sort_import                 = false    # true/false
-mod_sort_using                  = false    # true/false
-mod_sort_include                = false    # true/false
-mod_move_case_break             = false    # true/false
-mod_case_brace                  = remove   # ignore/add/remove/force
-mod_remove_empty_return         = true     # true/false
-mod_enum_last_comma             = ignore   # ignore/add/remove/force
-mod_sort_oc_properties          = false    # true/false
-mod_sort_oc_property_class_weight = 0        # number
-mod_sort_oc_property_thread_safe_weight = 0        # number
-mod_sort_oc_property_readwrite_weight = 0        # number
-mod_sort_oc_property_reference_weight = 0        # number
-mod_sort_oc_property_getter_weight = 0        # number
-mod_sort_oc_property_setter_weight = 0        # number
-mod_sort_oc_property_nullability_weight = 0        # number
-pp_indent                       = force    # ignore/add/remove/force
-pp_indent_at_level              = true     # true/false
-pp_indent_count                 = 4        # unsigned number
-pp_space                        = remove   # ignore/add/remove/force
-pp_space_count                  = 0        # unsigned number
-pp_indent_region                = 0        # number
-pp_region_indent_code           = false    # true/false
-pp_indent_if                    = 0        # number
-pp_if_indent_code               = true     # true/false
-pp_define_at_level              = false    # true/false
-pp_ignore_define_body           = false    # true/false
-pp_indent_case                  = true     # true/false
-pp_indent_func_def              = true     # true/false
-pp_indent_extern                = true     # true/false
-pp_indent_brace                 = false    # true/false
-include_category_0              = ""         # string
-include_category_1              = ""         # string
-include_category_2              = ""         # string
-use_indent_func_call_param      = true     # true/false
-use_indent_continue_only_once   = false    # true/false
-indent_cpp_lambda_only_once     = false    # true/false
-use_options_overriding_for_qt_macros = true     # true/false
-warn_level_tabs_found_in_verbatim_string_literals = 2        # unsigned number

.github/workflows/auto-release.yml

@@ -1,126 +0,0 @@
-name: Kernel-Auto-Release
-
-on:
-  workflow_dispatch:
-    inputs:
-      commit_id:
-        description: 'Commit ID'
-        required: true
-        default: 'HEAD'
-      version_number:
-        description: 'Version Number (Ex. 10.4.4)'
-        required: true
-        default: '10.4.4'
-      main_br_version:
-        description: "Version String for task.h on main branch (leave empty to leave as-is)."
-        required: false
-        default: ''
-
-jobs:
-  release-packager:
-    name: Release Packager
-    runs-on: ubuntu-latest
-    steps:
-      # Install python 3
-      - name: Tool Setup
-        uses: actions/setup-python@v2
-        with:
-          architecture:   x64
-        env:
-          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-
-      # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage
-      - name: Checkout FreeRTOS Release Tools
-        uses: actions/checkout@v4.1.1
-        with:
-          repository: FreeRTOS/FreeRTOS
-          path: tools
-
-      # Simpler git auth if we use checkout action and forward the repo to release script
-      - name: Checkout FreeRTOS Kernel
-        uses: actions/checkout@v4.1.1
-        with:
-          path: local_kernel
-          fetch-depth: 0
-
-      - name: Configure git identity
-        env:
-          ACTOR: ${{ github.actor }}
-        run: |
-          git config --global user.name "$ACTOR"
-          git config --global user.email "$ACTOR"@users.noreply.github.com
-
-      - name: create a new branch that references commit id
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-          COMMIT_ID: ${{ github.event.inputs.commit_id }}
-        working-directory: ./local_kernel
-        run: |
-          git checkout -b "$VERSION_NUMBER" "$COMMIT_ID"
-          echo "COMMIT_SHA_1=$(git rev-parse HEAD)" >> $GITHUB_ENV
-
-      - name: Update source files with version info
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-          MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }}
-          COMMIT_SHA_1: ${{ env.COMMIT_SHA_1 }}
-          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-        run: |
-          # Install deps and run
-          pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_1" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
-          exit $?
-
-      - name : Update version number in manifest.yml
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-        working-directory: ./local_kernel
-        run: |
-          ./.github/scripts/manifest_updater.py -v "$VERSION_NUMBER"
-          exit $?
-
-      - name : Commit version number change in manifest.yml
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-        working-directory: ./local_kernel
-        run: |
-          git add .
-          git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml'
-          git push -u origin "$VERSION_NUMBER"
-
-      - name: Generate SBOM
-        uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main
-        with:
-          repo_path: ./local_kernel
-          source_path: ./
-
-      - name: commit SBOM file
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-        working-directory: ./local_kernel
-        run: |
-          git add .
-          git commit -m '[AUTO][RELEASE]: Update SBOM'
-          git push -u origin "$VERSION_NUMBER"
-          echo "COMMIT_SHA_2=$(git rev-parse HEAD)" >> $GITHUB_ENV
-
-      - name: Release
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-          MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }}
-          COMMIT_SHA_2: ${{ env.COMMIT_SHA_2 }}
-          REPO_OWNER: ${{ github.repository_owner }}
-          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-        run: |
-          # Install deps and run
-          pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
-          exit $?
-
-      - name: Cleanup
-        env:
-          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
-        working-directory: ./local_kernel
-        run: |
-          # Delete the branch created for Tag by SBOM generator
-          git push -u origin --delete "$VERSION_NUMBER"

.github/workflows/ci.yml

@@ -1,51 +0,0 @@
-name: CI Checks
-on:
-  push:
-    branches: ["**"]
-  pull_request:
-    branches: [main]
-  workflow_dispatch:
-jobs:
-  formatting:
-    runs-on: ubuntu-20.04
-    steps:
-      - uses: actions/checkout@v4.1.1
-      - name: Check Formatting of FreeRTOS-Kernel Files
-        uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
-        with:
-          exclude-dirs: portable
-
-  spell-check:
-      runs-on: ubuntu-latest
-      steps:
-        - name: Clone This Repo
-          uses: actions/checkout@v4.1.1
-        - name: Run spellings check
-          uses: FreeRTOS/CI-CD-Github-Actions/spellings@main
-          with:
-            path: ./
-            exclude-files: History.txt
-
-  link-verifier:
-    runs-on: ubuntu-latest
-    steps:
-      - name: Clone This Repo
-        uses: actions/checkout@v4.1.1
-      - name: Link Verification
-        uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@main
-        with:
-          allowlist-file: '.github/allowed_urls.txt'
-
-  verify-manifest:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v4.1.1
-        with:
-          submodules: true
-          fetch-depth: 0
-
-      - name: Run manifest verifier
-        uses: FreeRTOS/CI-CD-GitHub-Actions/manifest-verifier@main
-        with:
-          path: ./
-          fail-on-incorrect-version: true

.github/workflows/coverity_scan.yml

@@ -1,127 +0,0 @@
-name: Coverity Scan
-on:
-  # Run on every commit to mainline
-  push:
-    branches: main
-  # Allow manual running of the scan
-  workflow_dispatch:
-
-env:
-  bashPass: \033[32;1mPASSED -
-  bashInfo: \033[33;1mINFO -
-  bashFail: \033[31;1mFAILED -
-  bashEnd:  \033[0m
-
-jobs:
-  Coverity-Scan:
-    if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
-    name: Coverity Scan
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout the Repository
-        uses: actions/checkout@v4.1.1
-
-      - env:
-          stepName: Install Build Essentials
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-          sudo apt-get -y update
-          sudo apt-get -y install build-essential
-
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-      - env:
-          stepName: Install Coverity Build
-          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-          wget -nv -qO- https://scan.coverity.com/download/linux64 --post-data "token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" | tar -zx --one-top-level=cov_scan --strip-components 1
-          echo "cov_scan_path=$(pwd)/cov_scan/bin" >> $GITHUB_ENV
-
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
-
-      - env:
-          stepName: Coverity Build
-          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
-          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-          export PATH="$PATH:${{env.cov_scan_path}}"
-          cmake -S ./examples/cmake_example/ -B build
-          cd build
-          cov-build --dir cov-int make -j
-          # Move the report out of the build directory
-          tar czvf ../gcc_freertos_kernel_sample_build.tgz cov-int
-
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
-
-      - env:
-          stepName: Upload Coverity Report for Scan
-          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
-          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-          COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
-            --form email=${COVERITY_EMAIL} \
-            --form file=@gcc_freertos_kernel_sample_build.tgz \
-            --form version="Mainline" \
-            --form description="FreeRTOS Kernel Commit Scan" \
-            https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
-
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
-          echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
-
-      - env:
-            stepName: Coverity Build for SMP FreeRTOS
-            COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
-            COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
-        shell: bash
-        run: |
-            # ${{ env.stepName }}
-            echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-  
-            export PATH="$PATH:${{env.cov_scan_path}}"
-            cmake -S ./examples/cmake_example/ -B build -DFREERTOS_SMP_EXAMPLE=1
-            cd build
-            cov-build --dir cov-int make -j
-            # Move the report out of the build directory
-            tar czvf ../gcc_freertos_kernel_smp_sample_build.tgz cov-int
-  
-            echo "::endgroup::"
-            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
-
-      - env:
-            stepName: Upload FreeRTOS SMP Coverity Report for Scan
-            COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
-            COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
-        shell: bash
-        run: |
-            # ${{ env.stepName }}
-            echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-  
-            COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
-              --form email=${COVERITY_EMAIL} \
-              --form file=@gcc_freertos_kernel_smp_sample_build.tgz \
-              --form version="Mainline" \
-              --form description="FreeRTOS Kernel SMP Commit Scan" \
-              https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
-  
-            echo "::endgroup::"
-            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
-            echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"

.github/workflows/formatting.yml

@@ -1,25 +0,0 @@
-name: Format Pull Request Files
-
-on:
-  issue_comment:
-    types: [created]
-
-env:
-  bashPass: \033[32;1mPASSED -
-  bashInfo: \033[33;1mINFO -
-  bashFail: \033[31;1mFAILED -
-  bashEnd:  \033[0m
-
-jobs:
-  Formatting:
-    name: Run Formatting Check
-    if: ${{ github.event.issue.pull_request &&
-        ( ( github.event.comment.body == '/bot run uncrustify' ) ||
-          ( github.event.comment.body == '/bot run formatting' ) ) }}
-    runs-on: ubuntu-20.04
-    steps:
-    - name: Apply Formatting Fix
-      id: check-formatting
-      uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
-      with:
-        exclude-dirs: portable

.github/workflows/git-secrets.yml

@@ -1,24 +0,0 @@
-name: git-secrets Check
-on:
-  push:
-  pull_request:
-  workflow_dispatch:
-jobs:
-  git-secrets:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v4.1.1
-        with:
-          submodules: recursive
-      - name: Checkout awslabs/git-secrets
-        uses: actions/checkout@v4.1.1
-        with:
-          repository: awslabs/git-secrets
-          ref: master
-          path: git-secrets
-      - name: Install git-secrets
-        run: cd git-secrets && sudo make install && cd ..
-      - name: Run git-secrets
-        run: |
-          git-secrets --register-aws
-          git-secrets --scan

.github/workflows/kernel-checks.yml

@@ -1,69 +0,0 @@
-name: Kernel-Checker
-
-on: [push, pull_request]
-
-jobs:
-  kernel-checker:
-    name: FreeRTOS Kernel Header Checks
-    runs-on: ubuntu-20.04
-    steps:
-      # Install python 3
-      - name: Tool Setup
-        uses: actions/setup-python@v3
-        env:
-          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-
-      # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker
-      - name: Checkout FreeRTOS Tools
-        uses: actions/checkout@v4.1.1
-        with:
-          repository: FreeRTOS/FreeRTOS
-          sparse-checkout: '.github'
-          ref:  main
-          path: tools
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: inspect
-
-      # Collect all affected files
-      - name: Collecting changed files
-        uses: lots0logs/gh-action-get-changed-files@2.2.2
-        with:
-          token: ${{ secrets.GITHUB_TOKEN }}
-
-      # Run checks
-      - env:
-          bashPass: \033[32;1mPASSED -
-          bashInfo: \033[33;1mINFO -
-          bashFail: \033[31;1mFAILED -
-          bashEnd:  \033[0m
-          stepName: Check File Headers
-        name: ${{ env.stepName }}
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} Install Dependencies ${{ env.bashEnd }}"
-
-          # Copy the common tools from the FreeRTOS/FreeRTOS repo.
-          mv tools/.github/scripts/common inspect/.github/scripts
-
-          # Install the necessary python dependencies
-          pip install -r inspect/.github/scripts/common/requirements.txt
-          cd inspect
-
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-          # Use the python script to check the copyright header of modified files.
-          .github/scripts/kernel_checker.py --json ${HOME}/files_modified.json ${HOME}/files_added.json ${HOME}/files_renamed.json
-          exitStatus=$?
-          echo -e "::endgroup::"
-
-          if [ $exitStatus -eq 0 ]; then
-            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          else
-            echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          fi
-          exit $exitStatus

.github/workflows/kernel-demos.yml

@@ -1,327 +0,0 @@
-name: FreeRTOS-Kernel Demos
-on: [push, pull_request]
-
-env:
-  # The bash escape character is \033
-  bashPass:   \033[32;1mPASSED -
-  bashInfo:   \033[33;1mINFO -
-  bashFail:   \033[31;1mFAILED -
-  bashEnd:    \033[0m
-
-jobs:
-  WIN32-MSVC:
-    name: WIN32 MSVC
-    runs-on: windows-latest
-    steps:
-      - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v4.1.1
-        with:
-          ref: main
-          repository: FreeRTOS/FreeRTOS
-          submodules: 'recursive'
-          fetch-depth: 1
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: ./FreeRTOS/Source
-
-      - name: Add msbuild to PATH
-        uses: microsoft/setup-msbuild@v1.1
-
-      - name: Build WIN32-MSVC Demo
-        working-directory: FreeRTOS/Demo/WIN32-MSVC
-        run: msbuild WIN32.sln -t:rebuild
-
-      - name: Build WIN32-MSVC-Static-Allocation-Only Demo
-        working-directory: FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only
-        run: msbuild WIN32.sln -t:rebuild
-
-  WIN32-MingW:
-    name: WIN32 MingW
-    runs-on: windows-latest
-    steps:
-      - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v4.1.1
-        with:
-          ref: main
-          repository: FreeRTOS/FreeRTOS
-          submodules: 'recursive'
-          fetch-depth: 1
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: ./FreeRTOS/Source
-
-      - name: Build WIN32-MingW Demo
-        working-directory: FreeRTOS/Demo/WIN32-MingW
-        run: |
-          gcc --version
-          make --version
-          make
-
-  POSIX-GCC:
-    name: Native GCC
-    strategy:
-      fail-fast: false
-      matrix:
-        os:
-          - macos-latest
-          - ubuntu-latest
-    runs-on: ${{ matrix.os }}
-    steps:
-      - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v4.1.1
-        with:
-          ref: main
-          repository: FreeRTOS/FreeRTOS
-          submodules: 'recursive'
-          fetch-depth: 1
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: ./FreeRTOS/Source
-
-      - name: Install GCC
-        shell: bash
-        if: matrix.os == 'ubuntu-latest'
-        run: |
-          sudo apt-get -y update
-          sudo apt-get -y install build-essential
-
-      - name: Build Posix_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/Posix_GCC
-        run: make -j
-
-      - name: Build Posix_GCC Demo for Coverage Test
-        shell: bash
-        working-directory: FreeRTOS/Demo/Posix_GCC
-        run: make -j COVERAGE_TEST=1
-
-  CMake-Example:
-    name: CMake Example with Native GCC
-    runs-on: ubuntu-latest
-    steps:
-      # Checkout user pull request changes
-      - name: Checkout Repository
-        uses: actions/checkout@v4.1.1
-
-      - name: Install GCC
-        shell: bash
-        run: |
-          sudo apt-get -y update
-          sudo apt-get -y install build-essential
-
-      - name: Build CMake Example Demo
-        shell: bash
-        working-directory: examples/cmake_example
-        run: |
-          cmake -S . -B build
-          cmake --build build
-
-      - name: Build CMake SMP Example Demo
-        shell: bash
-        working-directory: examples/cmake_example
-        run: |
-          cmake -S . -B build -DFREERTOS_SMP_EXAMPLE=1
-          cmake --build build
-
-  MSP430-GCC:
-    name: GNU MSP430 Toolchain
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v4.1.1
-        with:
-          ref: main
-          repository: FreeRTOS/FreeRTOS
-          submodules: 'recursive'
-          fetch-depth: 1
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: ./FreeRTOS/Source
-
-      - env:
-          stepName: Install MSP430 Toolchain
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          curl -L -O https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
-          sudo apt update -y
-          sudo apt install -y p7zip-full
-          7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
-          chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run
-          sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-      - name: Build msp430_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/msp430_GCC
-        run: make -j CC=/usr/bin/msp430-gcc/bin/msp430-elf-gcc OPT="-Os -I/usr/bin/msp430-gcc/include -L/usr/bin/msp430-gcc/include"
-
-  MicroBlaze-GCC:
-    name: GCC MicroBlaze Toolchain
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v4.1.1
-        with:
-          ref: main
-          repository: FreeRTOS/FreeRTOS
-          fetch-depth: 1
-
-      - env:
-          stepName: Fetch Community-Supported-Demos Submodule
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
-          # This repository contains the microblaze_instructions.h header file
-          git clone https://github.com/Xilinx/embeddedsw.git --branch xilinx_v2023.1
-          echo "::endgroup::"
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: ./FreeRTOS/Source
-
-      - env:
-          stepName: Install Dependancies
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          sudo apt update -y
-          sudo apt upgrade -y
-          sudo apt install -y build-essential m4 debhelper bison texinfo dejagnu flex
-          sudo apt install -y autogen gawk libgmp-dev libmpc-dev libmpfr-dev
-          sudo apt install -y patchutils sharutils zlib1g-dev autoconf2.64
-
-          # Download the mb-gcc toolchain from github
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
-          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
-
-          # Install the packages for the toolchain
-          sudo apt install -y ./binutils-microblaze*.deb;
-          sudo apt install -y ./gcc-microblaze*.deb;
-          sudo apt install -y ./libnewlib-microblaze-dev*.deb;
-          sudo apt install -y ./libnewlib-microblaze-doc*.deb;
-          sudo apt install -y ./libnewlib-microblaze*.deb;
-          sudo apt install -y ./newlib-source*.deb;
-
-          # Validate that the toolchain is in the path and can be called
-          which mb-gcc
-          mb-gcc --version
-
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-      - env:
-          stepName: Compile Microblaze Port
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          # Compile MicroBlazeV9 Port files to validate they build
-          mb-gcc -mcpu=v9.5 -c \
-            FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c \
-            FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S \
-            FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c \
-            FreeRTOS/Source/tasks.c \
-            FreeRTOS/Source/list.c \
-            -I embeddedsw/lib/bsp/standalone/src/microblaze \
-            -I FreeRTOS/Source/portable/GCC/MicroBlazeV9/ \
-            -I FreeRTOS/Source/include \
-            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src \
-            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src \
-            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include \
-            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-
-  ARM-GCC:
-    name: GNU ARM Toolchain
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v4.1.1
-        with:
-          ref: main
-          repository: FreeRTOS/FreeRTOS
-          fetch-depth: 1
-
-      - env:
-          stepName: Fetch Dependencies
-        shell: bash
-        run: |
-          # ${{ env.stepName }}
-          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
-          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace
-          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
-
-      # Checkout user pull request changes
-      - name: Checkout Pull Request
-        uses: actions/checkout@v4.1.1
-        with:
-          path: ./FreeRTOS/Source
-
-      - name: Install GNU ARM Toolchain
-        shell: bash
-        run: |
-          sudo apt-get -y update
-          sudo apt-get -y install gcc-arm-none-eabi build-essential cmake git ninja-build python3-minimal
-
-      - name: Build CORTEX_MPU_M3_MPS2_QEMU_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC
-        run: make -j
-
-      - name: Build CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC
-        run: cmake -S . -B build && make -j -C build all
-
-      - name: Build CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC
-        run: cmake -S . -B build && make -j -C build all
-
-      - name: Build CORTEX_LM3S102_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_LM3S102_GCC
-        run: make -j
-
-      - name: Build CORTEX_LM3S811_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_LM3S811_GCC
-        run: make -j
-
-      - name: Build CORTEX_M0+_RP2040 Demos
-        shell: bash
-        working-directory: FreeRTOS/Demo/ThirdParty/Community-Supported-Demos/CORTEX_M0+_RP2040
-        run: |
-          git clone https://github.com/raspberrypi/pico-sdk.git
-          cmake -B build -DPICO_SDK_PATH=pico-sdk -GNinja
-          ninja -C build --verbose
-
-      - name: Build CORTEX_MPS2_QEMU_IAR_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC
-        run: make -C build/gcc -j

.github/workflows/unit-tests.yml

@@ -1,56 +0,0 @@
-name: CMock Unit Tests
-on: [push, pull_request]
-
-jobs:
-  run:
-    runs-on: ubuntu-20.04
-    steps:
-    - name: Checkout Parent Repository
-      uses: actions/checkout@v4.1.1
-      with:
-        ref: main
-        repository: FreeRTOS/FreeRTOS
-        submodules: 'recursive'
-        fetch-depth: 1
-
-    # Checkout user pull request changes
-    - name: Checkout Pull Request
-      uses: actions/checkout@v4.1.1
-      with:
-        path: ./FreeRTOS/Source
-
-    - name: Setup Python
-      uses: actions/setup-python@master
-      with:
-        python-version: 3.8
-
-    - name: Install packages
-      run: |
-          sudo apt-get install lcov cflow ruby doxygen build-essential unifdef
-    - name: Run Unit Tests with ENABLE_SANITIZER=1
-      run: |
-          make -C FreeRTOS/Test/CMock clean
-          make -C FreeRTOS/Test/CMock ENABLE_SANITIZER=1 run_col_formatted
-    - name: Run Unit Tests for coverage
-      run: |
-          make -C FreeRTOS/Test/CMock clean
-          make -C FreeRTOS/Test/CMock lcovhtml
-          lcov --config-file FreeRTOS/Test/CMock/lcovrc --summary FreeRTOS/Test/CMock/build/cmock_test.info > FreeRTOS/Test/CMock/build/cmock_test_summary.txt
-    - name: Upload coverage to Codecov
-      uses: codecov/codecov-action@v3.1.0
-      with:
-        files: ${{ github.workspace }}/FreeRTOS/Test/CMock/build/cmock_test.info
-        root_dir: ${{ github.workspace }}/FreeRTOS/Source
-        flags: unittests
-        fail_ci_if_error: false
-        verbose: false
-    - name: Archive code coverage data
-      uses: actions/upload-artifact@v4
-      with:
-        name: coverage-data
-        path: FreeRTOS/Test/CMock/build/cmock_test*
-    - name: Archive code coverage html report
-      uses: actions/upload-artifact@v4
-      with:
-        name: coverage-report
-        path: FreeRTOS/Test/CMock/build/coverage

.gitmodules

@@ -1,6 +0,0 @@
-[submodule "ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports"]
-	path = portable/ThirdParty/Partner-Supported-Ports
-	url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports
-[submodule "ThirdParty/FreeRTOS-Kernel-Community-Supported-Ports"]
-	path = portable/ThirdParty/Community-Supported-Ports
-	url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports

CMakeLists.txt

@@ -1,272 +0,0 @@
-cmake_minimum_required(VERSION 3.15)
-
-# User is responsible to one mandatory option:
-#   FREERTOS_PORT, if not specified and native port detected, uses the native compile.
-#
-# User is responsible for one library target:
-#   freertos_config ,typically an INTERFACE library
-#
-# DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now.
-#             May be removed at some point in the future.
-#
-# User can choose which heap implementation to use (either the implementations
-# included with FreeRTOS [1..5] or a custom implementation) by providing the
-# option FREERTOS_HEAP. When dynamic allocation is used, the user must specify a
-# heap implementation. If the option is not set, the cmake will use no heap
-# implementation (e.g. when only static allocation is used).
-
-# `freertos_config` target defines the path to FreeRTOSConfig.h and optionally other freertos based config files
-if(NOT TARGET freertos_config )
-    if (NOT DEFINED FREERTOS_CONFIG_FILE_DIRECTORY )
-
-        message(FATAL_ERROR " freertos_config target not specified.  Please specify a cmake target that defines the include directory for FreeRTOSConfig.h:\n"
-            "  add_library(freertos_config INTERFACE)\n"
-            "  target_include_directories(freertos_config SYSTEM\n"
-            "    INTERFACE\n"
-            "      include) # The config file directory\n"
-            "  target_compile_definitions(freertos_config\n"
-            "    PUBLIC\n"
-            "    projCOVERAGE_TEST=0)\n")
-    else()
-        message(WARNING " Using deprecated 'FREERTOS_CONFIG_FILE_DIRECTORY' - please update your project CMakeLists.txt file:\n"
-            "  add_library(freertos_config INTERFACE)\n"
-            "  target_include_directories(freertos_config SYSTEM\n"
-            "    INTERFACE\n"
-            "      include) # The config file directory\n"
-            "  target_compile_definitions(freertos_config\n"
-            "    PUBLIC\n"
-            "    projCOVERAGE_TEST=0)\n")
-    endif()
-endif()
-
-# FreeRTOS port option
-if(NOT FREERTOS_PORT)
-    message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n"
-        "  set(FREERTOS_PORT GCC_ARM_CM4F CACHE STRING \"\")\n"
-        " or from CMake command line option:\n"
-        "  -DFREERTOS_PORT=GCC_ARM_CM4F\n"
-        " \n"
-        " Available port options:\n"
-        " A_CUSTOM_PORT                    - Compiler: User Defined  Target: User Defined\n"
-        " BCC_16BIT_DOS_FLSH186            - Compiler: BCC           Target: 16 bit DOS Flsh186\n"
-        " BCC_16BIT_DOS_PC                 - Compiler: BCC           Target: 16 bit DOS PC\n"
-        " CCS_ARM_CM3                      - Compiler: CCS           Target: ARM Cortex-M3\n"
-        " CCS_ARM_CM4F                     - Compiler: CCS           Target: ARM Cortex-M4 with FPU\n"
-        " CCS_ARM_CR4                      - Compiler: CCS           Target: ARM Cortex-R4\n"
-        " CCS_MSP430X                      - Compiler: CCS           Target: MSP430X\n"
-        " CODEWARRIOR_COLDFIRE_V1          - Compiler: CoreWarrior   Target: ColdFire V1\n"
-        " CODEWARRIOR_COLDFIRE_V2          - Compiler: CoreWarrior   Target: ColdFire V2\n"
-        " CODEWARRIOR_HCS12                - Compiler: CoreWarrior   Target: HCS12\n"
-        " GCC_ARM_CA9                      - Compiler: GCC           Target: ARM Cortex-A9\n"
-        " GCC_ARM_AARCH64                  - Compiler: GCC           Target: ARM v8-A\n"
-        " GCC_ARM_AARCH64_SRE              - Compiler: GCC           Target: ARM v8-A SRE\n"
-        " GCC_ARM_CM0                      - Compiler: GCC           Target: ARM Cortex-M0\n"
-        " GCC_ARM_CM3                      - Compiler: GCC           Target: ARM Cortex-M3\n"
-        " GCC_ARM_CM3_MPU                  - Compiler: GCC           Target: ARM Cortex-M3 with MPU\n"
-        " GCC_ARM_CM4_MPU                  - Compiler: GCC           Target: ARM Cortex-M4 with MPU\n"
-        " GCC_ARM_CM4F                     - Compiler: GCC           Target: ARM Cortex-M4 with FPU\n"
-        " GCC_ARM_CM7                      - Compiler: GCC           Target: ARM Cortex-M7\n"
-        " GCC_ARM_CM23_NONSECURE           - Compiler: GCC           Target: ARM Cortex-M23 non-secure\n"
-        " GCC_ARM_CM23_SECURE              - Compiler: GCC           Target: ARM Cortex-M23 secure\n"
-        " GCC_ARM_CM23_NTZ_NONSECURE       - Compiler: GCC           Target: ARM Cortex-M23 non-trustzone non-secure\n"
-        " GCC_ARM_CM33_NONSECURE           - Compiler: GCC           Target: ARM Cortex-M33 non-secure\n"
-        " GCC_ARM_CM33_SECURE              - Compiler: GCC           Target: ARM Cortex-M33 secure\n"
-        " GCC_ARM_CM33_NTZ_NONSECURE       - Compiler: GCC           Target: ARM Cortex-M33 non-trustzone non-secure\n"
-        " GCC_ARM_CM33_TFM                 - Compiler: GCC           Target: ARM Cortex-M33 non-secure for TF-M\n"
-        " GCC_ARM_CM35P_NONSECURE          - Compiler: GCC           Target: ARM Cortex-M35P non-secure\n"
-        " GCC_ARM_CM35P_SECURE             - Compiler: GCC           Target: ARM Cortex-M35P secure\n"
-        " GCC_ARM_CM35P_NTZ_NONSECURE      - Compiler: GCC           Target: ARM Cortex-M35P non-trustzone non-secure\n"
-        " GCC_ARM_CM55_NONSECURE           - Compiler: GCC           Target: ARM Cortex-M55 non-secure\n"
-        " GCC_ARM_CM55_SECURE              - Compiler: GCC           Target: ARM Cortex-M55 secure\n"
-        " GCC_ARM_CM55_NTZ_NONSECURE       - Compiler: GCC           Target: ARM Cortex-M55 non-trustzone non-secure\n"
-        " GCC_ARM_CM55_TFM                 - Compiler: GCC           Target: ARM Cortex-M55 non-secure for TF-M\n"
-        " GCC_ARM_CM85_NONSECURE           - Compiler: GCC           Target: ARM Cortex-M85 non-secure\n"
-        " GCC_ARM_CM85_SECURE              - Compiler: GCC           Target: ARM Cortex-M85 secure\n"
-        " GCC_ARM_CM85_NTZ_NONSECURE       - Compiler: GCC           Target: ARM Cortex-M85 non-trustzone non-secure\n"
-        " GCC_ARM_CM85_TFM                 - Compiler: GCC           Target: ARM Cortex-M85 non-secure for TF-M\n"
-        " GCC_ARM_CR5                      - Compiler: GCC           Target: ARM Cortex-R5\n"
-        " GCC_ARM_CRX_MPU                  - Compiler: GCC           Target: ARM Cortex-Rx with MPU\n"
-        " GCC_ARM_CRX_NOGIC                - Compiler: GCC           Target: ARM Cortex-Rx no GIC\n"
-        " GCC_ARM7_AT91FR40008             - Compiler: GCC           Target: ARM7 Atmel AT91R40008\n"
-        " GCC_ARM7_AT91SAM7S               - Compiler: GCC           Target: ARM7 Atmel AT91SAM7S\n"
-        " GCC_ARM7_LPC2000                 - Compiler: GCC           Target: ARM7 LPC2000\n"
-        " GCC_ARM7_LPC23XX                 - Compiler: GCC           Target: ARM7 LPC23xx\n"
-        " GCC_ATMEGA323                    - Compiler: GCC           Target: ATMega323\n"
-        " GCC_AVR32_UC3                    - Compiler: GCC           Target: AVR32 UC3\n"
-        " GCC_COLDFIRE_V2                  - Compiler: GCC           Target: ColdFire V2\n"
-        " GCC_CORTUS_APS3                  - Compiler: GCC           Target: CORTUS APS3\n"
-        " GCC_H8S2329                      - Compiler: GCC           Target: H8S2329\n"
-        " GCC_HCS12                        - Compiler: GCC           Target: HCS12\n"
-        " GCC_IA32_FLAT                    - Compiler: GCC           Target: IA32 flat\n"
-        " GCC_MICROBLAZE                   - Compiler: GCC           Target: MicroBlaze\n"
-        " GCC_MICROBLAZE_V8                - Compiler: GCC           Target: MicroBlaze V8\n"
-        " GCC_MICROBLAZE_V9                - Compiler: GCC           Target: MicroBlaze V9\n"
-        " GCC_MSP430F449                   - Compiler: GCC           Target: MSP430F449\n"
-        " GCC_NIOSII                       - Compiler: GCC           Target: NiosII\n"
-        " GCC_PPC405_XILINX                - Compiler: GCC           Target: Xilinx PPC405\n"
-        " GCC_PPC440_XILINX                - Compiler: GCC           Target: Xilinx PPC440\n"
-        " GCC_RISC_V                       - Compiler: GCC           Target: RISC-V\n"
-        " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiler: GCC           Target: RISC-V Pulpino Vega RV32M1RM\n"
-        " GCC_RISC_V_GENERIC               - Compiler: GCC           Target: RISC-V with FREERTOS_RISCV_EXTENSION\n"
-        " GCC_RL78                         - Compiler: GCC           Target: Renesas RL78\n"
-        " GCC_RX100                        - Compiler: GCC           Target: Renesas RX100\n"
-        " GCC_RX200                        - Compiler: GCC           Target: Renesas RX200\n"
-        " GCC_RX600                        - Compiler: GCC           Target: Renesas RX600\n"
-        " GCC_RX600_V2                     - Compiler: GCC           Target: Renesas RX600 v2\n"
-        " GCC_RX700_V3_DPFPU               - Compiler: GCC           Target: Renesas RX700 v3 with DPFPU\n"
-        " GCC_STR75X                       - Compiler: GCC           Target: STR75x\n"
-        " GCC_TRICORE_1782                 - Compiler: GCC           Target: TriCore 1782\n"
-        " GCC_ARC_EM_HS                    - Compiler: GCC           Target: DesignWare ARC EM HS\n"
-        " GCC_ARC_V1                       - Compiler: GCC           Target: DesignWare ARC v1\n"
-        " GCC_ATMEGA                       - Compiler: GCC           Target: ATmega\n"
-        " GCC_POSIX                        - Compiler: GCC           Target: Posix\n"
-        " GCC_RP2040                       - Compiler: GCC           Target: RP2040 ARM Cortex-M0+\n"
-        " GCC_XTENSA_ESP32                 - Compiler: GCC           Target: Xtensa ESP32\n"
-        " GCC_AVRDX                        - Compiler: GCC           Target: AVRDx\n"
-        " GCC_AVR_MEGA0                    - Compiler: GCC           Target: AVR Mega0\n"
-        " IAR_78K0K                        - Compiler: IAR           Target: Renesas 78K0K\n"
-        " IAR_ARM_CA5_NOGIC                - Compiler: IAR           Target: ARM Cortex-A5 no GIC\n"
-        " IAR_ARM_CA9                      - Compiler: IAR           Target: ARM Cortex-A9\n"
-        " IAR_ARM_CM0                      - Compiler: IAR           Target: ARM Cortex-M0\n"
-        " IAR_ARM_CM3                      - Compiler: IAR           Target: ARM Cortex-M3\n"
-        " IAR_ARM_CM4F                     - Compiler: IAR           Target: ARM Cortex-M4 with FPU\n"
-        " IAR_ARM_CM4F_MPU                 - Compiler: IAR           Target: ARM Cortex-M4 with FPU and MPU\n"
-        " IAR_ARM_CM7                      - Compiler: IAR           Target: ARM Cortex-M7\n"
-        " IAR_ARM_CM23_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M23 non-secure\n"
-        " IAR_ARM_CM23_SECURE              - Compiler: IAR           Target: ARM Cortex-M23 secure\n"
-        " IAR_ARM_CM23_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M23 non-trustzone non-secure\n"
-        " IAR_ARM_CM33_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M33 non-secure\n"
-        " IAR_ARM_CM33_SECURE              - Compiler: IAR           Target: ARM Cortex-M33 secure\n"
-        " IAR_ARM_CM33_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M33 non-trustzone non-secure\n"
-        " IAR_ARM_CM33_TFM                 - Compiler: IAR           Target: ARM Cortex-M33 non-secure for TF-M\n"
-        " IAR_ARM_CM35P_NONSECURE          - Compiler: IAR           Target: ARM Cortex-M35P non-secure\n"
-        " IAR_ARM_CM35P_SECURE             - Compiler: IAR           Target: ARM Cortex-M35P secure\n"
-        " IAR_ARM_CM35P_NTZ_NONSECURE      - Compiler: IAR           Target: ARM Cortex-M35P non-trustzone non-secure\n"
-        " IAR_ARM_CM55_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M55 non-secure\n"
-        " IAR_ARM_CM55_SECURE              - Compiler: IAR           Target: ARM Cortex-M55 secure\n"
-        " IAR_ARM_CM55_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M55 non-trustzone non-secure\n"
-        " IAR_ARM_CM55_TFM                 - Compiler: IAR           Target: ARM Cortex-M55 non-secure for TF-M\n"
-        " IAR_ARM_CM85_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M85 non-secure\n"
-        " IAR_ARM_CM85_SECURE              - Compiler: IAR           Target: ARM Cortex-M85 secure\n"
-        " IAR_ARM_CM85_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M85 non-trustzone non-secure\n"
-        " IAR_ARM_CM85_TFM                 - Compiler: IAR           Target: ARM Cortex-M85 non-secure for TF-M\n"
-        " IAR_ARM_CRX_NOGIC                - Compiler: IAR           Target: ARM Cortex-Rx no GIC\n"
-        " IAR_ATMEGA323                    - Compiler: IAR           Target: ATMega323\n"
-        " IAR_ATMEL_SAM7S64                - Compiler: IAR           Target: Atmel SAM7S64\n"
-        " IAR_ATMEL_SAM9XE                 - Compiler: IAR           Target: Atmel SAM9XE\n"
-        " IAR_AVR_AVRDX                    - Compiler: IAR           Target: AVRDx\n"
-        " IAR_AVR_MEGA0                    - Compiler: IAR           Target: AVR Mega0\n"
-        " IAR_AVR32_UC3                    - Compiler: IAR           Target: AVR32 UC3\n"
-        " IAR_LPC2000                      - Compiler: IAR           Target: LPC2000\n"
-        " IAR_MSP430                       - Compiler: IAR           Target: MSP430\n"
-        " IAR_MSP430X                      - Compiler: IAR           Target: MSP430X\n"
-        " IAR_RISC_V                       - Compiler: IAR           Target: RISC-V\n"
-        " IAR_RISC_V_GENERIC               - Compiler: IAR           Target: RISC-V with FREERTOS_RISCV_EXTENSION\n"
-        " IAR_RL78                         - Compiler: IAR           Target: Renesas RL78\n"
-        " IAR_RX100                        - Compiler: IAR           Target: Renesas RX100\n"
-        " IAR_RX600                        - Compiler: IAR           Target: Renesas RX600\n"
-        " IAR_RX700_V3_DPFPU               - Compiler: IAR           Target: Renesas RX700 v3 with DPFPU\n"
-        " IAR_RX_V2                        - Compiler: IAR           Target: Renesas RX v2\n"
-        " IAR_STR71X                       - Compiler: IAR           Target: STR71x\n"
-        " IAR_STR75X                       - Compiler: IAR           Target: STR75x\n"
-        " IAR_STR91X                       - Compiler: IAR           Target: STR91x\n"
-        " IAR_V850ES_FX3                   - Compiler: IAR           Target: Renesas V850ES/Fx3\n"
-        " IAR_V850ES_HX3                   - Compiler: IAR           Target: Renesas V850ES/Hx3\n"
-        " MIKROC_ARM_CM4F                  - Compiler: MikroC        Target: ARM Cortex-M4 with FPU\n"
-        " MPLAB_PIC18F                     - Compiler: MPLAB         Target: PIC18F\n"
-        " MPLAB_PIC24                      - Compiler: MPLAB         Target: PIC24\n"
-        " MPLAB_PIC32MEC14XX               - Compiler: MPLAB         Target: PIC32MEC14xx\n"
-        " MPLAB_PIC32MX                    - Compiler: MPLAB         Target: PIC32MX\n"
-        " MPLAB_PIC32MZ                    - Compiler: MPLAB         Target: PIC32MZ\n"
-        " MSVC_MINGW                       - Compiler: MSVC or MinGW Target: x86\n"
-        " OWATCOM_16BIT_DOS_FLSH186        - Compiler: Open Watcom   Target: 16 bit DOS Flsh186\n"
-        " OWATCOM_16BIT_DOS_PC             - Compiler: Open Watcom   Target: 16 bit DOS PC\n"
-        " PARADIGM_TERN_EE_LARGE           - Compiler: Paradigm      Target: Tern EE large\n"
-        " PARADIGM_TERN_EE_SMALL           - Compiler: Paradigm      Target: Tern EE small\n"
-        " RENESAS_RX100                    - Compiler: Renesas       Target: RX100\n"
-        " RENESAS_RX200                    - Compiler: Renesas       Target: RX200\n"
-        " RENESAS_RX600                    - Compiler: Renesas       Target: RX600\n"
-        " RENESAS_RX600_V2                 - Compiler: Renesas       Target: RX600 v2\n"
-        " RENESAS_RX700_V3_DPFPU           - Compiler: Renesas       Target: RX700 v3 with DPFPU\n"
-        " RENESAS_SH2A_FPU                 - Compiler: Renesas       Target: SH2A with FPU\n"
-        " ROWLEY_MSP430F449                - Compiler: Rowley        Target: MSP430F449\n"
-        " RVDS_ARM_CA9                     - Compiler: RVDS          Target: ARM Cortex-A9\n"
-        " RVDS_ARM_CM0                     - Compiler: RVDS          Target: ARM Cortex-M0\n"
-        " RVDS_ARM_CM3                     - Compiler: RVDS          Target: ARM Cortex-M3\n"
-        " RVDS_ARM_CM4_MPU                 - Compiler: RVDS          Target: ARM Cortex-M4 with MPU\n"
-        " RVDS_ARM_CM4F                    - Compiler: RVDS          Target: ARM Cortex-M4 with FPU\n"
-        " RVDS_ARM_CM7                     - Compiler: RVDS          Target: ARM Cortex-M7\n"
-        " RVDS_ARM7_LPC21XX                - Compiler: RVDS          Target: ARM7 LPC21xx\n"
-        " SDCC_CYGNAL                      - Compiler: SDCC          Target: Cygnal\n"
-        " SOFTUNE_MB91460                  - Compiler: Softune       Target: MB91460\n"
-        " SOFTUNE_MB96340                  - Compiler: Softune       Target: MB96340\n"
-        " TASKING_ARM_CM4F                 - Compiler: Tasking       Target: ARM Cortex-M4 with FPU\n"
-        " TEMPLATE                         - Compiler: HOST          Target: None\n"
-        " CDK_THEAD_CK802                  - Compiler: CDK           Target: T-head CK802\n"
-        " XCC_XTENSA                       - Compiler: XCC           Target: Xtensa\n"
-        " WIZC_PIC18                       - Compiler: WizC          Target: PIC18")
-    # Native FREERTOS_PORT for Linux and Windows MINGW builds
-    if(UNIX)
-        message(STATUS " Auto-Detected Unix, setting FREERTOS_PORT=GCC_POSIX")
-        set(FREERTOS_PORT GCC_POSIX CACHE STRING "FreeRTOS port name")
-    elseif(MINGW)
-        message(STATUS " Auto-Detected MINGW, setting FREERTOS_PORT=MSVC_MINGW")
-        set(FREERTOS_PORT MSVC_MINGW CACHE STRING "FreeRTOS port name")
-    endif()
-elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_port) )
-    message(FATAL_ERROR " FREERTOS_PORT is set to A_CUSTOM_PORT. Please specify the custom port target with all necessary files. For example:\n"
-    " Assuming a directory of:\n"
-    "  FreeRTOSCustomPort/\n"
-    "    CMakeLists.txt\n"
-    "    port.c\n"
-    "    portmacro.h\n"
-    " Where FreeRTOSCustomPort/CMakeLists.txt is a modified version of:\n"
-    "   add_library(freertos_kernel_port OBJECT)\n"
-    "   target_sources(freertos_kernel_port\n"
-    "     PRIVATE\n"
-    "       port.c\n"
-    "       portmacro.h)\n"
-    "   add_library(freertos_kernel_port_headers INTERFACE)\n"
-    "     target_include_directories(freertos_kernel_port_headers INTERFACE \n"
-    "      .)\n"
-    "   target_link_libraries(freertos_kernel_port\n"
-    "     PRIVATE\n"
-    "       freertos_kernel_port_headers\n"
-    "       freertos_kernel_include)")
-endif()
-
-add_library(freertos_kernel STATIC)
-
-########################################################################
-add_subdirectory(include)
-add_subdirectory(portable)
-
-target_sources(freertos_kernel PRIVATE
-    croutine.c
-    event_groups.c
-    list.c
-    queue.c
-    stream_buffer.c
-    tasks.c
-    timers.c
-)
-
-if (DEFINED FREERTOS_HEAP )
-    # User specified a heap implementation add heap implementation to freertos_kernel.
-    target_sources(freertos_kernel PRIVATE
-        # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
-        $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
-    )
-endif()
-
-
-target_link_libraries(freertos_kernel
-    PUBLIC
-        freertos_kernel_include
-        freertos_kernel_port_headers
-    PRIVATE
-        freertos_kernel_port
-
-)
-
-########################################################################

Demo/ARM7_AT91FR40008_GCC/AT91R40008.h

@@ -0,0 +1,707 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+//  The software is delivered "AS IS" without warranty or condition of any
+//  kind, either express, implied or statutory. This includes without
+//  limitation any warranty or condition with respect to merchantability or
+//  fitness for any particular purpose, or against the infringements of
+//  intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name           : AT91R40008.h
+// Object              : AT91R40008 definitions
+// Generated           : AT91 SW Application Group  02/19/2003 (11:13:31)
+// 
+// CVS Reference       : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002//
+// CVS Reference       : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//
+// CVS Reference       : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//
+// CVS Reference       : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002//
+// CVS Reference       : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//
+// CVS Reference       : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//
+// CVS Reference       : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//
+// CVS Reference       : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//
+// CVS Reference       : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002//
+// CVS Reference       : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91R40008_H
+#define AT91R40008_H
+
+/* AT91 Register type */
+typedef volatile unsigned int AT91_REG;  // Hardware register definition
+typedef volatile unsigned int at91_reg;
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode egister
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector egister
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command egister
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Interface
+// *****************************************************************************
+typedef struct _AT91S_WD {
+	AT91_REG	 WD_OMR; 	// Overflow Mode Register
+	AT91_REG	 WD_CMR; 	// Clock Mode Register
+	AT91_REG	 WD_CR; 	// Control Register
+	AT91_REG	 WD_SR; 	// Status Register
+} AT91S_WD, *AT91PS_WD;
+
+// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- 
+#define AT91C_WD_WDEN         ((unsigned int) 0x1 <<  0) // (WD) Watchdog Enable
+#define AT91C_WD_RSTEN        ((unsigned int) 0x1 <<  1) // (WD) Reset Enable
+#define AT91C_WD_IRQEN        ((unsigned int) 0x1 <<  2) // (WD) Interrupt Enable
+#define AT91C_WD_EXTEN        ((unsigned int) 0x1 <<  3) // (WD) External Signal Enable
+#define AT91C_WD_OKEY         ((unsigned int) 0xFFF <<  4) // (WD) Watchdog Enable
+// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- 
+#define AT91C_WD_WDCLKS       ((unsigned int) 0x3 <<  0) // (WD) Clock Selection
+#define 	AT91C_WD_WDCLKS_MCK32                ((unsigned int) 0x0) // (WD) Master Clock divided by 32
+#define 	AT91C_WD_WDCLKS_MCK128               ((unsigned int) 0x1) // (WD) Master Clock divided by 128
+#define 	AT91C_WD_WDCLKS_MCK1024              ((unsigned int) 0x2) // (WD) Master Clock divided by 1024
+#define 	AT91C_WD_WDCLKS_MCK4096              ((unsigned int) 0x3) // (WD) Master Clock divided by 4096
+#define AT91C_WD_HPCV         ((unsigned int) 0xF <<  2) // (WD) High Pre-load Counter Value
+#define AT91C_WD_CKEY         ((unsigned int) 0x1FF <<  7) // (WD) Clock Access Key
+// -------- WD_CR : (WD Offset: 0x8) Control Register -------- 
+#define AT91C_WD_RSTKEY       ((unsigned int) 0xFFFF <<  0) // (WD) Restart Key
+// -------- WD_SR : (WD Offset: 0xc) Status Register -------- 
+#define AT91C_WD_WDOVF        ((unsigned int) 0x1 <<  0) // (WD) Watchdog Overflow
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Saving Controler
+// *****************************************************************************
+typedef struct _AT91S_PS {
+	AT91_REG	 PS_CR; 	// Control Register
+	AT91_REG	 PS_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PS_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PS_PCSR; 	// Peripheral Clock Status Register
+} AT91S_PS, *AT91PS_PS;
+
+// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register -------- 
+#define AT91C_PS_US0          ((unsigned int) 0x1 <<  2) // (PS) Usart 0 Clock
+#define AT91C_PS_US1          ((unsigned int) 0x1 <<  3) // (PS) Usart 1 Clock
+#define AT91C_PS_TC0          ((unsigned int) 0x1 <<  4) // (PS) Timer Counter 0 Clock
+#define AT91C_PS_TC1          ((unsigned int) 0x1 <<  5) // (PS) Timer Counter 1 Clock
+#define AT91C_PS_TC2          ((unsigned int) 0x1 <<  6) // (PS) Timer Counter 2 Clock
+#define AT91C_PS_PIO          ((unsigned int) 0x1 <<  8) // (PS) PIO Clock
+// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register -------- 
+// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+} AT91S_PDC, *AT91PS_PDC;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (USART) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (USART) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (USART) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (USART) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (USART) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (USART) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (USART) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (USART) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (USART) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (USART) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (USART) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (USART) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (USART) Multi-drop mode
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (USART) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (USART) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (USART) TXRDY Interrupt
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (USART) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (USART) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (USART) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (USART) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (USART) Parity Error Interrupt
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (USART) TXEMPTY Interrupt
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Special Function Interface
+// *****************************************************************************
+typedef struct _AT91S_SF {
+	AT91_REG	 SF_CIDR; 	// Chip ID Register
+	AT91_REG	 SF_EXID; 	// Chip ID Extension Register
+	AT91_REG	 SF_RSR; 	// Reset Status Register
+	AT91_REG	 SF_MMR; 	// Memory Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SF_PMR; 	// Protect Mode Register
+} AT91S_SF, *AT91PS_SF;
+
+// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- 
+#define AT91C_SF_VERSION      ((unsigned int) 0x1F <<  0) // (SF) Version of the chip
+#define AT91C_SF_BIT5         ((unsigned int) 0x1 <<  5) // (SF) Hardwired at 0
+#define AT91C_SF_BIT6         ((unsigned int) 0x1 <<  6) // (SF) Hardwired at 1
+#define AT91C_SF_BIT7         ((unsigned int) 0x1 <<  7) // (SF) Hardwired at 0
+#define AT91C_SF_NVPSIZ       ((unsigned int) 0xF <<  8) // (SF) Nonvolatile Program Memory Size
+#define 	AT91C_SF_NVPSIZ_NONE                 ((unsigned int) 0x0 <<  8) // (SF) None
+#define 	AT91C_SF_NVPSIZ_32K                  ((unsigned int) 0x3 <<  8) // (SF) 32K Bytes
+#define 	AT91C_SF_NVPSIZ_64K                  ((unsigned int) 0x5 <<  8) // (SF) 64K Bytes
+#define 	AT91C_SF_NVPSIZ_128K                 ((unsigned int) 0x7 <<  8) // (SF) 128K Bytes
+#define 	AT91C_SF_NVPSIZ_256K                 ((unsigned int) 0x11 <<  8) // (SF) 256K Bytes
+#define AT91C_SF_NVDSIZ       ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size
+#define 	AT91C_SF_NVDSIZ_NONE                 ((unsigned int) 0x0 << 12) // (SF) None
+#define AT91C_SF_VDSIZ        ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size
+#define 	AT91C_SF_VDSIZ_NONE                 ((unsigned int) 0x0 << 16) // (SF) None
+#define 	AT91C_SF_VDSIZ_1K                   ((unsigned int) 0x3 << 16) // (SF) 1K Bytes
+#define 	AT91C_SF_VDSIZ_2K                   ((unsigned int) 0x5 << 16) // (SF) 2K Bytes
+#define 	AT91C_SF_VDSIZ_4K                   ((unsigned int) 0x7 << 16) // (SF) 4K Bytes
+#define 	AT91C_SF_VDSIZ_8K                   ((unsigned int) 0x11 << 16) // (SF) 8K Bytes
+#define AT91C_SF_ARCH         ((unsigned int) 0xFF << 20) // (SF) Chip Architecture
+#define 	AT91C_SF_ARCH_AT91x40              ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy
+#define 	AT91C_SF_ARCH_AT91x55              ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy
+#define 	AT91C_SF_ARCH_AT91x63              ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy
+#define AT91C_SF_NVPTYP       ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type
+#define 	AT91C_SF_NVPTYP_NVPTYP_M             ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series
+#define 	AT91C_SF_NVPTYP_NVPTYP_R             ((unsigned int) 0x4 << 28) // (SF) 'R' Series
+#define AT91C_SF_EXT          ((unsigned int) 0x1 << 31) // (SF) Extension Flag
+// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- 
+#define AT91C_SF_RESET        ((unsigned int) 0xFF <<  0) // (SF) Cause of Reset
+#define 	AT91C_SF_RESET_WD                   ((unsigned int) 0x35) // (SF) Internal Watchdog
+#define 	AT91C_SF_RESET_EXT                  ((unsigned int) 0x6C) // (SF) External Pin
+// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register -------- 
+#define AT91C_SF_RAMWU        ((unsigned int) 0x1 <<  0) // (SF) Internal Extended RAM Write Detection
+// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- 
+#define AT91C_SF_AIC          ((unsigned int) 0x1 <<  5) // (SF) AIC Protect Mode Enable
+#define AT91C_SF_PMRKEY       ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR External Bus Interface
+// *****************************************************************************
+typedef struct _AT91S_EBI {
+	AT91_REG	 EBI_CSR[8]; 	// Chip-select Register
+	AT91_REG	 EBI_RCR; 	// Remap Control Register
+	AT91_REG	 EBI_MCR; 	// Memory Control Register
+} AT91S_EBI, *AT91PS_EBI;
+
+// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- 
+#define AT91C_EBI_DBW         ((unsigned int) 0x3 <<  0) // (EBI) Data Bus Width
+#define 	AT91C_EBI_DBW_16                   ((unsigned int) 0x1) // (EBI) 16-bit data bus width
+#define 	AT91C_EBI_DBW_8                    ((unsigned int) 0x2) // (EBI) 8-bit data bus width
+#define AT91C_EBI_NWS         ((unsigned int) 0x7 <<  2) // (EBI) Number of wait states
+#define 	AT91C_EBI_NWS_1                    ((unsigned int) 0x0 <<  2) // (EBI) 1 wait state
+#define 	AT91C_EBI_NWS_2                    ((unsigned int) 0x1 <<  2) // (EBI) 2 wait state
+#define 	AT91C_EBI_NWS_3                    ((unsigned int) 0x2 <<  2) // (EBI) 3 wait state
+#define 	AT91C_EBI_NWS_4                    ((unsigned int) 0x3 <<  2) // (EBI) 4 wait state
+#define 	AT91C_EBI_NWS_5                    ((unsigned int) 0x4 <<  2) // (EBI) 5 wait state
+#define 	AT91C_EBI_NWS_6                    ((unsigned int) 0x5 <<  2) // (EBI) 6 wait state
+#define 	AT91C_EBI_NWS_7                    ((unsigned int) 0x6 <<  2) // (EBI) 7 wait state
+#define 	AT91C_EBI_NWS_8                    ((unsigned int) 0x7 <<  2) // (EBI) 8 wait state
+#define AT91C_EBI_WSE         ((unsigned int) 0x1 <<  5) // (EBI) Wait State Enable
+#define AT91C_EBI_PAGES       ((unsigned int) 0x3 <<  7) // (EBI) Pages Size
+#define 	AT91C_EBI_PAGES_1M                   ((unsigned int) 0x0 <<  7) // (EBI) 1M Byte
+#define 	AT91C_EBI_PAGES_4M                   ((unsigned int) 0x1 <<  7) // (EBI) 4M Byte
+#define 	AT91C_EBI_PAGES_16M                  ((unsigned int) 0x2 <<  7) // (EBI) 16M Byte
+#define 	AT91C_EBI_PAGES_64M                  ((unsigned int) 0x3 <<  7) // (EBI) 64M Byte
+#define AT91C_EBI_TDF         ((unsigned int) 0x7 <<  9) // (EBI) Data Float Output Time
+#define 	AT91C_EBI_TDF_0                    ((unsigned int) 0x0 <<  9) // (EBI) 1 TDF
+#define 	AT91C_EBI_TDF_1                    ((unsigned int) 0x1 <<  9) // (EBI) 2 TDF
+#define 	AT91C_EBI_TDF_2                    ((unsigned int) 0x2 <<  9) // (EBI) 3 TDF
+#define 	AT91C_EBI_TDF_3                    ((unsigned int) 0x3 <<  9) // (EBI) 4 TDF
+#define 	AT91C_EBI_TDF_4                    ((unsigned int) 0x4 <<  9) // (EBI) 5 TDF
+#define 	AT91C_EBI_TDF_5                    ((unsigned int) 0x5 <<  9) // (EBI) 6 TDF
+#define 	AT91C_EBI_TDF_6                    ((unsigned int) 0x6 <<  9) // (EBI) 7 TDF
+#define 	AT91C_EBI_TDF_7                    ((unsigned int) 0x7 <<  9) // (EBI) 8 TDF
+#define AT91C_EBI_BAT         ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type
+#define AT91C_EBI_CSEN        ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable
+#define AT91C_EBI_BA          ((unsigned int) 0xFFF << 20) // (EBI) Base Address
+// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register -------- 
+#define AT91C_EBI_RCB         ((unsigned int) 0x1 <<  0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
+// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register -------- 
+#define AT91C_EBI_ALE         ((unsigned int) 0x7 <<  0) // (EBI) Address Line Enable
+#define 	AT91C_EBI_ALE_16M                  ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23  Max Addressable Space = 16M Bytes Valid Chip Select=None 
+#define 	AT91C_EBI_ALE_8M                   ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22  Max Addressable Space = 8M Bytes Valid Chip Select = CS4 
+#define 	AT91C_EBI_ALE_4M                   ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21  Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5 
+#define 	AT91C_EBI_ALE_2M                   ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20  Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6 
+#define 	AT91C_EBI_ALE_1M                   ((unsigned int) 0x7) // (EBI) Valid Address Bits = None  Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7 
+#define AT91C_EBI_DRP         ((unsigned int) 0x1 <<  4) // (EBI) 
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91R40008
+// *****************************************************************************
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector egister
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode egister
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command egister
+// ========== Register definition for WD peripheral ========== 
+#define AT91C_WD_SR     ((AT91_REG *) 	0xFFFF800C) // (WD) Status Register
+#define AT91C_WD_CMR    ((AT91_REG *) 	0xFFFF8004) // (WD) Clock Mode Register
+#define AT91C_WD_CR     ((AT91_REG *) 	0xFFFF8008) // (WD) Control Register
+#define AT91C_WD_OMR    ((AT91_REG *) 	0xFFFF8000) // (WD) Overflow Mode Register
+// ========== Register definition for PS peripheral ========== 
+#define AT91C_PS_PCDR   ((AT91_REG *) 	0xFFFF4008) // (PS) Peripheral Clock Disable Register
+#define AT91C_PS_CR     ((AT91_REG *) 	0xFFFF4000) // (PS) Control Register
+#define AT91C_PS_PCSR   ((AT91_REG *) 	0xFFFF400C) // (PS) Peripheral Clock Status Register
+#define AT91C_PS_PCER   ((AT91_REG *) 	0xFFFF4004) // (PS) Peripheral Clock Enable Register
+// ========== Register definition for PIO peripheral ========== 
+#define AT91C_PIO_MDSR  ((AT91_REG *) 	0xFFFF0058) // (PIO) Multi-driver Status Register
+#define AT91C_PIO_IFSR  ((AT91_REG *) 	0xFFFF0028) // (PIO) Input Filter Status Register
+#define AT91C_PIO_IFER  ((AT91_REG *) 	0xFFFF0020) // (PIO) Input Filter Enable Register
+#define AT91C_PIO_OSR   ((AT91_REG *) 	0xFFFF0018) // (PIO) Output Status Register
+#define AT91C_PIO_OER   ((AT91_REG *) 	0xFFFF0010) // (PIO) Output Enable Register
+#define AT91C_PIO_PSR   ((AT91_REG *) 	0xFFFF0008) // (PIO) PIO Status Register
+#define AT91C_PIO_PDSR  ((AT91_REG *) 	0xFFFF003C) // (PIO) Pin Data Status Register
+#define AT91C_PIO_CODR  ((AT91_REG *) 	0xFFFF0034) // (PIO) Clear Output Data Register
+#define AT91C_PIO_IFDR  ((AT91_REG *) 	0xFFFF0024) // (PIO) Input Filter Disable Register
+#define AT91C_PIO_MDER  ((AT91_REG *) 	0xFFFF0050) // (PIO) Multi-driver Enable Register
+#define AT91C_PIO_IMR   ((AT91_REG *) 	0xFFFF0048) // (PIO) Interrupt Mask Register
+#define AT91C_PIO_IER   ((AT91_REG *) 	0xFFFF0040) // (PIO) Interrupt Enable Register
+#define AT91C_PIO_ODSR  ((AT91_REG *) 	0xFFFF0038) // (PIO) Output Data Status Register
+#define AT91C_PIO_SODR  ((AT91_REG *) 	0xFFFF0030) // (PIO) Set Output Data Register
+#define AT91C_PIO_PER   ((AT91_REG *) 	0xFFFF0000) // (PIO) PIO Enable Register
+#define AT91C_PIO_MDDR  ((AT91_REG *) 	0xFFFF0054) // (PIO) Multi-driver Disable Register
+#define AT91C_PIO_ISR   ((AT91_REG *) 	0xFFFF004C) // (PIO) Interrupt Status Register
+#define AT91C_PIO_IDR   ((AT91_REG *) 	0xFFFF0044) // (PIO) Interrupt Disable Register
+#define AT91C_PIO_PDR   ((AT91_REG *) 	0xFFFF0004) // (PIO) PIO Disable Register
+#define AT91C_PIO_ODR   ((AT91_REG *) 	0xFFFF0014) // (PIO) Output Disable Registerr
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFE00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFE00A0) // (TC2) Status Register
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFE0098) // (TC2) Register B
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFE0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFE0080) // (TC2) Channel Control Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFE00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFE00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFE009C) // (TC2) Register C
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFE0094) // (TC2) Register A
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFE0084) // (TC2) Channel Mode Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFE0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFE0060) // (TC1) Status Register
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFE0058) // (TC1) Register B
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFE0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFE0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFE006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFE0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFE005C) // (TC1) Register C
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFE0054) // (TC1) Register A
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFE0044) // (TC1) Channel Mode Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFE0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFE0020) // (TC0) Status Register
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFE0018) // (TC0) Register B
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFE0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFE0000) // (TC0) Channel Control Register
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFE002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFE0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFE001C) // (TC0) Register C
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFE0014) // (TC0) Register A
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFE0004) // (TC0) Channel Mode Register
+// ========== Register definition for TCB0 peripheral ========== 
+#define AT91C_TCB0_BCR  ((AT91_REG *) 	0xFFFE00C0) // (TCB0) TC Block Control Register
+#define AT91C_TCB0_BMR  ((AT91_REG *) 	0xFFFE00C4) // (TCB0) TC Block Mode Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4038) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4030) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC403C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4034) // (PDC_US1) Receive Counter Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFCC024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFCC01C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFCC014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFCC00C) // (US1) Interrupt Disable Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFCC004) // (US1) Mode Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFCC028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFCC020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFCC018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFCC010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFCC008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFCC000) // (US1) Control Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0038) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0030) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC003C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0034) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFD0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFD001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFD0014) // (US0) Channel Status Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFD000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFD0004) // (US0) Mode Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFD0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFD0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFD0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFD0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFD0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFD0000) // (US0) Control Register
+// ========== Register definition for SF peripheral ========== 
+#define AT91C_SF_PMR    ((AT91_REG *) 	0xFFF00018) // (SF) Protect Mode Register
+#define AT91C_SF_RSR    ((AT91_REG *) 	0xFFF00008) // (SF) Reset Status Register
+#define AT91C_SF_CIDR   ((AT91_REG *) 	0xFFF00000) // (SF) Chip ID Register
+#define AT91C_SF_MMR    ((AT91_REG *) 	0xFFF0000C) // (SF) Memory Mode Register
+#define AT91C_SF_EXID   ((AT91_REG *) 	0xFFF00004) // (SF) Chip ID Extension Register
+// ========== Register definition for EBI peripheral ========== 
+#define AT91C_EBI_RCR   ((AT91_REG *) 	0xFFE00020) // (EBI) Remap Control Register
+#define AT91C_EBI_CSR   ((AT91_REG *) 	0xFFE00000) // (EBI) Chip-select Register
+#define AT91C_EBI_MCR   ((AT91_REG *) 	0xFFE00024) // (EBI) Memory Control Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91R40008
+// *****************************************************************************
+#define AT91C_PIO_P0         ((unsigned int) 1 <<  0) // Pin Controlled by P0
+#define AT91C_P0_TCLK0    ((unsigned int) AT91C_PIO_P0) //  Timer 0 Clock signal
+#define AT91C_PIO_P1         ((unsigned int) 1 <<  1) // Pin Controlled by P1
+#define AT91C_P1_TIOA0    ((unsigned int) AT91C_PIO_P1) //  Timer 0 Signal A
+#define AT91C_PIO_P10        ((unsigned int) 1 << 10) // Pin Controlled by P10
+#define AT91C_P10_IRQ1     ((unsigned int) AT91C_PIO_P10) //  External Interrupt 1
+#define AT91C_PIO_P11        ((unsigned int) 1 << 11) // Pin Controlled by P11
+#define AT91C_P11_IRQ2     ((unsigned int) AT91C_PIO_P11) //  External Interrupt 2
+#define AT91C_PIO_P12        ((unsigned int) 1 << 12) // Pin Controlled by P12
+#define AT91C_P12_FIQ      ((unsigned int) AT91C_PIO_P12) //  Fast External Interrupt
+#define AT91C_PIO_P13        ((unsigned int) 1 << 13) // Pin Controlled by P13
+#define AT91C_P13_SCK0     ((unsigned int) AT91C_PIO_P13) //  USART 0 Serial Clock
+#define AT91C_PIO_P14        ((unsigned int) 1 << 14) // Pin Controlled by P14
+#define AT91C_P14_TXD0     ((unsigned int) AT91C_PIO_P14) //  USART 0 Transmit Data
+#define AT91C_PIO_P15        ((unsigned int) 1 << 15) // Pin Controlled by P15
+#define AT91C_P15_RXD0     ((unsigned int) AT91C_PIO_P15) //  USART 0 Receive Data
+#define AT91C_PIO_P16        ((unsigned int) 1 << 16) // Pin Controlled by P16
+#define AT91C_PIO_P17        ((unsigned int) 1 << 17) // Pin Controlled by P17
+#define AT91C_PIO_P18        ((unsigned int) 1 << 18) // Pin Controlled by P18
+#define AT91C_PIO_P19        ((unsigned int) 1 << 19) // Pin Controlled by P19
+#define AT91C_PIO_P2         ((unsigned int) 1 <<  2) // Pin Controlled by P2
+#define AT91C_P2_TIOB0    ((unsigned int) AT91C_PIO_P2) //  Timer 0 Signal B
+#define AT91C_PIO_P20        ((unsigned int) 1 << 20) // Pin Controlled by P20
+#define AT91C_P20_SCK1     ((unsigned int) AT91C_PIO_P20) //  USART 1 Serial Clock
+#define AT91C_PIO_P21        ((unsigned int) 1 << 21) // Pin Controlled by P21
+#define AT91C_P21_TXD1     ((unsigned int) AT91C_PIO_P21) //  USART 1 Transmit Data
+#define AT91C_P21_NTRI     ((unsigned int) AT91C_PIO_P21) //  Tri-state Mode
+#define AT91C_PIO_P22        ((unsigned int) 1 << 22) // Pin Controlled by P22
+#define AT91C_P22_RXD1     ((unsigned int) AT91C_PIO_P22) //  USART 1 Receive Data
+#define AT91C_PIO_P23        ((unsigned int) 1 << 23) // Pin Controlled by P23
+#define AT91C_PIO_P24        ((unsigned int) 1 << 24) // Pin Controlled by P24
+#define AT91C_P24_BMS      ((unsigned int) AT91C_PIO_P24) //  Boot Mode Select
+#define AT91C_PIO_P25        ((unsigned int) 1 << 25) // Pin Controlled by P25
+#define AT91C_P25_MCKO     ((unsigned int) AT91C_PIO_P25) //  Master Clock Out
+#define AT91C_PIO_P26        ((unsigned int) 1 << 26) // Pin Controlled by P26
+#define AT91C_P26_NCS2     ((unsigned int) AT91C_PIO_P26) //  Chip Select 2
+#define AT91C_PIO_P27        ((unsigned int) 1 << 27) // Pin Controlled by P27
+#define AT91C_P27_NCS3     ((unsigned int) AT91C_PIO_P27) //  Chip Select 3
+#define AT91C_PIO_P28        ((unsigned int) 1 << 28) // Pin Controlled by P28
+#define AT91C_P28_A20      ((unsigned int) AT91C_PIO_P28) //  Address line A20
+#define AT91C_P28_NCS7     ((unsigned int) AT91C_PIO_P28) //  Chip Select 7
+#define AT91C_PIO_P29        ((unsigned int) 1 << 29) // Pin Controlled by P29
+#define AT91C_P29_A21      ((unsigned int) AT91C_PIO_P29) //  Address line A21
+#define AT91C_P29_NCS6     ((unsigned int) AT91C_PIO_P29) //  Chip Select 6
+#define AT91C_PIO_P3         ((unsigned int) 1 <<  3) // Pin Controlled by P3
+#define AT91C_P3_TCLK1    ((unsigned int) AT91C_PIO_P3) //  Timer 1 Clock signal
+#define AT91C_PIO_P30        ((unsigned int) 1 << 30) // Pin Controlled by P30
+#define AT91C_P30_A22      ((unsigned int) AT91C_PIO_P30) //  Address line A22
+#define AT91C_P30_NCS5     ((unsigned int) AT91C_PIO_P30) //  Chip Select 5
+#define AT91C_PIO_P31        ((unsigned int) 1 << 31) // Pin Controlled by P31
+#define AT91C_P31_A23      ((unsigned int) AT91C_PIO_P31) //  Address line A23
+#define AT91C_P31_NCS4     ((unsigned int) AT91C_PIO_P31) //  Chip Select 4
+#define AT91C_PIO_P4         ((unsigned int) 1 <<  4) // Pin Controlled by P4
+#define AT91C_P4_TIOA1    ((unsigned int) AT91C_PIO_P4) //  Timer 1 Signal A
+#define AT91C_PIO_P5         ((unsigned int) 1 <<  5) // Pin Controlled by P5
+#define AT91C_P5_TIOB1    ((unsigned int) AT91C_PIO_P5) //  Timer 1 Signal B
+#define AT91C_PIO_P6         ((unsigned int) 1 <<  6) // Pin Controlled by P6
+#define AT91C_P6_TCLK2    ((unsigned int) AT91C_PIO_P6) //  Timer 2 Clock signal
+#define AT91C_PIO_P7         ((unsigned int) 1 <<  7) // Pin Controlled by P7
+#define AT91C_P7_TIOA2    ((unsigned int) AT91C_PIO_P7) //  Timer 2 Signal A
+#define AT91C_PIO_P8         ((unsigned int) 1 <<  8) // Pin Controlled by P8
+#define AT91C_P8_TIOB2    ((unsigned int) AT91C_PIO_P8) //  Timer 2 Signal B
+#define AT91C_PIO_P9         ((unsigned int) 1 <<  9) // Pin Controlled by P9
+#define AT91C_P9_IRQ0     ((unsigned int) AT91C_PIO_P9) //  External Interrupt 0
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91R40008
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // SWI
+#define AT91C_ID_US0    ((unsigned int)  2) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  3) // USART 1
+#define AT91C_ID_TC0    ((unsigned int)  4) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int)  5) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int)  6) // Timer Counter 2
+#define AT91C_ID_WD     ((unsigned int)  7) // Watchdog Timer
+#define AT91C_ID_PIO    ((unsigned int)  8) // Parallel IO Controller
+#define AT91C_ID_IRQ0   ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2   ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91R40008
+// *****************************************************************************
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_WD        ((AT91PS_WD) 	0xFFFF8000) // (WD) Base Address
+#define AT91C_BASE_PS        ((AT91PS_PS) 	0xFFFF4000) // (PS) Base Address
+#define AT91C_BASE_PIO       ((AT91PS_PIO) 	0xFFFF0000) // (PIO) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFE0080) // (TC2) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFE0040) // (TC1) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFE0000) // (TC0) Base Address
+#define AT91C_BASE_TCB0      ((AT91PS_TCB) 	0xFFFE0000) // (TCB0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4030) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFCC000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0030) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFD0000) // (US0) Base Address
+#define AT91C_BASE_SF        ((AT91PS_SF) 	0xFFF00000) // (SF) Base Address
+#define AT91C_BASE_EBI       ((AT91PS_EBI) 	0xFFE00000) // (EBI) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91R40008
+// *****************************************************************************
+#define AT91C_SRAM_BEFORE_REMAP	 ((char *) 	0x00300000) // Internal SRAM before remap base address
+#define AT91C_SRAM_BEFORE_REMAP_SIZE	 ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
+#define AT91C_SRAM_AFTER_REMAP	 ((char *) 	0x00000000) // Internal SRAM after remap base address
+#define AT91C_SRAM_AFTER_REMAP_SIZE	 ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)
+
+#endif

Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg

@@ -0,0 +1,24 @@
+[SETUP]
+CpuVendor=Atmel
+CpuChip=AT91R40807
+FlashVendor=Atmel
+FlashChip=AT49BV/F1614A
+RamAddress=$00000000
+RamSupport=1
+FlashAddress=$01000000
+FlashWidth=16
+FlashChipsPerSector=1
+LittleEndian=0
+SectStart=0
+SectEnd=38
+AutoErase=0
+AutoVerify=1
+CpuEndian=LITTLE
+SimCount=3
+MemoryCount=0
+ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex
+UploadFile=c:\EB40_Lower.bin
+Format=Intel Hex
+Sim3=EBI_RCR:$00000001
+Sim2=EBI_CSR1:$02002122
+Sim1=EBI_CSR0:$01002539

Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h

@@ -0,0 +1,79 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <AT91R40008.h>
+
+#define configFLASH_SPEED_NSEC	100       /* External flash access speed (for ROM builds) */
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 66000000 ) /* = 66.000MHz clk gen */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 128 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 25 * 1024 ) )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */

Demo/ARM7_AT91FR40008_GCC/Makefile

@@ -0,0 +1,99 @@
+#	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+#
+#	This file is part of the FreeRTOS.org distribution.
+#
+#	FreeRTOS.org is free software; you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation; either version 2 of the License, or
+#	(at your option) any later version.
+#
+#	FreeRTOS.org is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with FreeRTOS.org; if not, write to the Free Software
+#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#	A special exception to the GPL can be applied should you wish to distribute
+#	a combined work that includes FreeRTOS.org, without being obliged to provide
+#	the source code for any proprietary components.  See the licensing section 
+#	of http://www.FreeRTOS.org for full details of how and when the exception
+#	can be applied.
+#
+#	***************************************************************************
+#	See http://www.FreeRTOS.org for documentation, latest information, license 
+#	and contact details.  Please ensure to read the configuration and relevant 
+#	port sections of the online documentation.
+#	***************************************************************************
+
+CC=arm-elf-gcc
+OBJCOPY=arm-elf-objcopy
+ARCH=arm-elf-ar
+CRT0=boot.s
+
+#
+# CFLAGS common to both the THUMB and ARM mode builds
+#
+CFLAGS=-Wall -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \
+		-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
+		-Wcast-align $(OPTIM) -fomit-frame-pointer
+
+ifeq ($(USE_THUMB_MODE),YES)
+	CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
+	THUMB_FLAGS=-mthumb
+endif
+
+
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
+
+#
+# Source files that can be built to THUMB mode.
+#
+THUMB_SRC = \
+main.c \
+serial/serial.c \
+ParTest/ParTest.c \
+../Common/Minimal/integer.c \
+../Common/Minimal/flash.c \
+../Common/Minimal/PollQ.c \
+../Common/Minimal/comtest.c \
+../Common/Minimal/flop.c \
+../Common/Minimal/semtest.c \
+../Common/Minimal/dynamic.c \
+../Common/Minimal/BlockQ.c \
+../../Source/tasks.c \
+../../Source/queue.c \
+../../Source/list.c \
+../../Source/portable/MemMang/heap_2.c \
+../../Source/portable/GCC/ARM7_AT91FR40008/port.c
+
+#
+# Source files that must be built to ARM mode.
+#
+ARM_SRC = \
+../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \
+serial/serialISR.c
+
+#
+# Define all object files.
+#
+ARM_OBJ = $(ARM_SRC:.c=.o)
+THUMB_OBJ = $(THUMB_SRC:.c=.o)
+
+rtosdemo.hex : rtosdemo.elf
+	$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
+
+rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
+	$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
+
+$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
+	$(CC) -c $(CFLAGS) $< -o $@
+
+clean :
+	touch Makefile
+

Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c

@@ -0,0 +1,120 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "portable.h"
+
+/* Demo app includes. */
+#include "partest.h"
+
+/* Hardware specific definitions. */
+#include "AT91R40008.h"
+#include "pio.h"
+#include "aic.h"
+
+#define partstNUM_LEDS			( 8 )
+#define partstALL_OUTPUTS_OFF	( ( unsigned portLONG ) ~(0xFFFFFFFF << partstNUM_LEDS) )
+
+static unsigned portLONG ulLEDReg;
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines.
+ *-----------------------------------------------------------*/
+
+static void SetLeds (unsigned int leds)
+{
+unsigned portLONG ulPIOSetReg, ulPIOClearReg;
+
+	/* LEDs are grouped in different port bits: P3-P6 and P16-P19.
+	A port bit set to '0' turns an LED on, '1' turns it off. */
+
+	ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 );
+	ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078;
+
+	AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg;
+	AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg;
+}
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* This is performed from main() as the io bits are shared with other setup
+	functions.  Ensure the outputs are off to start. */
+	ulLEDReg = partstALL_OUTPUTS_OFF;  
+
+	/* Enable clock to PIO... */
+	AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO;
+
+	/* Enable all 8 LEDs and the four switches to be controlled by PIO... */
+	AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12;
+
+	/* Configure all LED PIO lines for output... */
+	AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19;
+
+	/* Configure all switch PIO lines for input... */
+	AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12;
+
+	/* Set initial state of LEDs. */
+	SetLeds( ulLEDReg );
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	/* Switch an LED on or off as requested. */
+	if (uxLED < partstNUM_LEDS)
+	{
+		if( xValue )
+		{
+			ulLEDReg &= ~(1 << uxLED);
+		}
+		else
+		{
+			ulLEDReg |= (1 << uxLED);
+		}
+
+		SetLeds( ulLEDReg );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	/* Toggle the state of the requested LED. */
+	if (uxLED < partstNUM_LEDS)
+	{
+		ulLEDReg ^= ( 1 << uxLED );
+		SetLeds( ulLEDReg );
+	}
+}
+

Demo/ARM7_AT91FR40008_GCC/aic.h

@@ -0,0 +1,81 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : aic.h
+//* Object              : Advanced Interrupt Controller Definition File.
+//*
+//* 1.0 01/04/00 JCZ    : Creation
+//*----------------------------------------------------------------------------
+
+#ifndef aic_h
+#define aic_h
+
+//#include    "periph/stdc/std_c.h"
+
+/*-----------------------------------------*/
+/* AIC User Interface Structure Definition */
+/*-----------------------------------------*/
+
+typedef struct
+{
+    at91_reg        AIC_SMR[32] ;       /* Source Mode Register */
+    at91_reg        AIC_SVR[32] ;       /* Source Vector Register */
+    at91_reg        AIC_IVR ;           /* IRQ Vector Register */
+    at91_reg        AIC_FVR ;           /* FIQ Vector Register */
+    at91_reg        AIC_ISR ;           /* Interrupt Status Register */
+    at91_reg        AIC_IPR ;           /* Interrupt Pending Register */
+    at91_reg        AIC_IMR ;           /* Interrupt Mask Register */
+    at91_reg        AIC_CISR ;          /* Core Interrupt Status Register */
+    at91_reg        reserved0 ;
+    at91_reg        reserved1 ;
+    at91_reg        AIC_IECR ;          /* Interrupt Enable Command Register */
+    at91_reg        AIC_IDCR ;          /* Interrupt Disable Command Register */
+    at91_reg        AIC_ICCR ;          /* Interrupt Clear Command Register */
+    at91_reg        AIC_ISCR ;          /* Interrupt Set Command Register */
+    at91_reg        AIC_EOICR ;         /* End of Interrupt Command Register */
+    at91_reg        AIC_SPU ;           /* Spurious Vector Register */
+} StructAIC ;
+
+/*--------------------------------------------*/
+/* AIC_SMR[]: Interrupt Source Mode Registers */
+/*--------------------------------------------*/
+
+#define AIC_PRIOR                       0x07    /* Priority */
+
+#define AIC_SRCTYPE                     0x60    /* Source Type Definition */
+
+/* Internal Interrupts */
+#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00    /* Level Sensitive */
+#define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x20    /* Edge Triggered */
+
+/* External Interrupts */
+#define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00    /* Low Level */
+#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x20    /* Negative Edge */
+#define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x40    /* High Level */
+#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x60    /* Positive Edge */
+
+/*------------------------------------*/
+/* AIC_ISR: Interrupt Status Register */
+/*------------------------------------*/
+
+#define AIC_IRQID                       0x1F    /* Current source interrupt */
+
+/*------------------------------------------*/
+/* AIC_CISR: Interrupt Core Status Register */
+/*------------------------------------------*/
+
+#define AIC_NFIQ                        0x01    /* Core FIQ Status */
+#define AIC_NIRQ                        0x02    /* Core IRQ Status */
+
+/*-------------------------------*/
+/* Advanced Interrupt Controller */
+/*-------------------------------*/
+#define AIC_BASE                        ((StructAIC *)0xFFFFF000)
+
+#endif /* aic_h */

Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld

@@ -0,0 +1,48 @@
+MEMORY 
+{
+	ram		: ORIGIN = 0x00000000, LENGTH = 256K
+}
+
+__stack_end__ = 0x00000000 + 256K - 4;
+
+SECTIONS 
+{
+	. = 0;
+	startup : { *(.startup)} >ram
+
+	prog : 
+	{
+		*(.text)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+	} >ram
+
+	__end_of_text__ = .;
+
+	.data : 
+	{
+		__data_beg__ = .;
+		__data_beg_src__ = __end_of_text__;
+		*(.data)
+		__data_end__ = .;
+	} >ram
+
+	.bss : 
+	{
+		__bss_beg__ = .;
+		*(.bss)
+	} >ram
+
+	/* Align here to ensure that the .bss section occupies space up to
+	_end.  Align after .bss to ensure correct alignment even if the
+	.bss section disappears because there are no input sections.  */
+	. = ALIGN(32 / 8);
+}
+	. = ALIGN(32 / 8);
+	_end = .;
+	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+	PROVIDE (end = .);
+
+

Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld

@@ -0,0 +1,49 @@
+MEMORY 
+{
+	flash	: ORIGIN = 0x00000000, LENGTH = 2048K
+	ram		: ORIGIN = 0x00300000, LENGTH = 256K
+}
+
+__stack_end__ = 0x00300000 + 256K - 4;
+
+SECTIONS 
+{
+	. = 0;
+	startup : { *(.startup)} >flash
+
+	prog : 
+	{
+		*(.text)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+	} >flash
+
+	__end_of_text__ = .;
+
+	.data : 
+	{
+		__data_beg__ = .;
+		__data_beg_src__ = __end_of_text__;
+		*(.data)
+		__data_end__ = .;
+	} >ram AT>flash
+
+	.bss : 
+	{
+		__bss_beg__ = .;
+		*(.bss)
+	} >ram
+
+	/* Align here to ensure that the .bss section occupies space up to
+	_end.  Align after .bss to ensure correct alignment even if the
+	.bss section disappears because there are no input sections.  */
+	. = ALIGN(32 / 8);
+}
+	. = ALIGN(32 / 8);
+	_end = .;
+	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+	PROVIDE (end = .);
+
+

Demo/ARM7_AT91FR40008_GCC/boot.s

@@ -0,0 +1,157 @@
+	/* Sample initialization file */
+
+	.extern main
+	.extern exit
+
+	.text
+	.code 32
+
+
+	.align  0
+
+	.extern __bss_beg__
+	.extern __bss_end__
+	.extern __stack_end__
+	.extern __data_beg__
+	.extern __data_end__
+	.extern __data+beg_src__
+
+	.global start
+	.global endless_loop
+
+	/* Stack Sizes */
+    .set  UND_STACK_SIZE, 0x00000004
+    .set  ABT_STACK_SIZE, 0x00000004
+    .set  FIQ_STACK_SIZE, 0x00000004
+    .set  IRQ_STACK_SIZE, 0X00000400
+    .set  SVC_STACK_SIZE, 0x00000400
+
+	/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+    .set  MODE_USR, 0x10            /* User Mode */
+    .set  MODE_FIQ, 0x11            /* FIQ Mode */
+    .set  MODE_IRQ, 0x12            /* IRQ Mode */
+    .set  MODE_SVC, 0x13            /* Supervisor Mode */
+    .set  MODE_ABT, 0x17            /* Abort Mode */
+    .set  MODE_UND, 0x1B            /* Undefined Mode */
+    .set  MODE_SYS, 0x1F            /* System Mode */
+
+    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
+    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
+
+
+start:
+_start:
+_mainCRTStartup:
+
+	/* Setup a stack for each mode - note that this only sets up a usable stack
+	for system/user, SWI and IRQ modes.   Also each mode is setup with
+	interrupts initially disabled. */
+    ldr   r0, .LC6
+    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
+    mov   sp, r0
+    sub   r0, r0, #UND_STACK_SIZE
+    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
+    mov   sp, r0
+    sub   r0, r0, #ABT_STACK_SIZE
+    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #FIQ_STACK_SIZE
+    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #IRQ_STACK_SIZE
+    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
+    mov   sp, r0
+    sub   r0, r0, #SVC_STACK_SIZE
+    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
+    mov   sp, r0
+
+	/* We want to start in supervisor mode.  Operation will switch to system
+	mode when the first task starts. */
+	msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
+
+	/* Clear BSS. */
+
+	mov     a2, #0			/* Fill value */
+	mov		fp, a2			/* Null frame pointer */
+	mov		r7, a2			/* Null frame pointer for Thumb */
+
+	ldr		r1, .LC1		/* Start of memory block */
+	ldr		r3, .LC2		/* End of memory block */
+	subs	r3, r3, r1      /* Length of block */
+	beq		.end_clear_loop
+	mov		r2, #0
+
+.clear_loop:
+	strb	r2, [r1], #1
+	subs	r3, r3, #1
+	bgt		.clear_loop
+
+.end_clear_loop:
+
+	/* Initialise data. */
+
+	ldr		r1, .LC3		/* Start of memory block */
+	ldr		r2, .LC4		/* End of memory block */
+	ldr		r3, .LC5
+	subs	r3, r3, r1		/* Length of block */
+	beq		.end_set_loop
+
+.set_loop:
+	ldrb	r4, [r2], #1
+	strb	r4, [r1], #1
+	subs	r3, r3, #1
+	bgt		.set_loop
+
+.end_set_loop:
+
+	mov		r0, #0          /* no arguments  */
+	mov		r1, #0          /* no argv either */
+
+	bl		main
+
+endless_loop:
+	b               endless_loop
+
+
+	.align 0
+
+	.LC1:
+	.word   __bss_beg__
+	.LC2:
+	.word   __bss_end__
+	.LC3:
+	.word   __data_beg__
+	.LC4:
+	.word   __data_beg_src__
+	.LC5:
+	.word   __data_end__
+	.LC6:
+	.word   __stack_end__
+
+
+	/* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
+	a null loop. */
+
+.section .startup,"ax"
+         .code 32
+         .align 0
+
+	b     _start						/* reset - _start			*/
+	ldr   pc, _undf						/* undefined - _undf		*/
+	ldr   pc, _swi						/* SWI - _swi				*/
+	ldr   pc, _pabt						/* program abort - _pabt	*/
+	ldr   pc, _dabt						/* data abort - _dabt		*/
+	nop									/* reserved					*/
+	ldr   pc, [pc,#-0xF20]				/* IRQ - read the AIC		*/
+	ldr   pc, _fiq						/* FIQ - _fiq				*/
+
+_undf:  .word __undf                    /* undefined				*/
+_swi:   .word vPortYieldProcessor       /* SWI						*/
+_pabt:  .word __pabt                    /* program abort			*/
+_dabt:  .word __dabt                    /* data abort				*/
+_fiq:   .word __fiq                     /* FIQ						*/
+
+__undf: b     .                         /* undefined				*/
+__pabt: b     .                         /* program abort			*/
+__dabt: b     .                         /* data abort				*/
+__fiq:  b     .                         /* FIQ						*/

Demo/ARM7_AT91FR40008_GCC/ebi.h

@@ -0,0 +1,121 @@
+//*-----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*-----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*-----------------------------------------------------------------------------
+//* File Name           : ebi.h
+//* Object              : External Bus Interface Definition File
+//* Translator          : ARM Software Development Toolkit V2.11a
+//*
+//* 1.0 03/11/97 JCZ    : Creation
+//* 2.0 21/10/98 JCZ    : Clean up
+//*-----------------------------------------------------------------------------
+
+#ifndef ebi_h
+#define ebi_h
+
+/*----------------------------------------*/
+/* Memory Controller Interface Definition */
+/*----------------------------------------*/
+
+typedef struct
+{
+    at91_reg        EBI_CSR[8] ;        /* Chip Select Register */
+    at91_reg        EBI_RCR ;           /* Remap Control Register */
+    at91_reg        EBI_MCR ;           /* Memory Control Register */
+} StructEBI ;
+
+/*-----------------------*/
+/* Chip Select Registers */
+/*-----------------------*/
+
+/* Data Bus Width */
+#define DataBus16               (1<<0)
+#define DataBus8                (2<<0)
+#define DBW                     (3<<0)
+
+/* Number of Wait States */
+#define B_NWS                   2
+#define WaitState1              (0<<B_NWS)
+#define WaitState2              (1<<B_NWS)
+#define WaitState3              (2<<B_NWS)
+#define WaitState4              (3<<B_NWS)
+#define WaitState5              (4<<B_NWS)
+#define WaitState6              (5<<B_NWS)
+#define WaitState7              (6<<B_NWS)
+#define WaitState8              (7<<B_NWS)
+#define NWS                     (7<<B_NWS)
+
+/* Wait State Enable */
+#define WaitStateDisable        (0<<5)
+#define WaitStateEnable         (1<<5)
+#define WSE                     (1<<5)
+
+/* Page size */
+#define PageSize1M              (0<<7)
+#define PageSize4M              (1<<7)
+#define PageSize16M             (2<<7)
+#define PageSize64M             (3<<7)
+#define PAGES                   (3<<7)
+
+/* Number of Data Float Output Time Clock Cycle */
+#define B_TDF                   9
+#define tDF_0cycle              (0<<B_TDF)
+#define tDF_1cycle              (1<<B_TDF)
+#define tDF_2cycle              (2<<B_TDF)
+#define tDF_3cycle              (3<<B_TDF)
+#define tDF_4cycle              (4<<B_TDF)
+#define tDF_5cycle              (5<<B_TDF)
+#define tDF_6cycle              (6<<B_TDF)
+#define tDF_7cycle              (7<<B_TDF)
+#define TDF                     (7<<B_TDF)
+
+/* Byte Access Type */
+#define ByteWriteAccessType (0<<12)
+#define ByteSelectAccessType    (1<<12)
+#define BAT                     1<<12)
+
+/* Chip Select Enable */
+#define CSEnable                (1<<13)
+#define CSDisable               (0<<13)
+#define CSE                     (1<<13)
+
+#define BA                      ((u_int)(0xFFF)<<20)
+
+/*-------------------------*/
+/* Memory Control Register */
+/*-------------------------*/
+
+/* Address Line Enable */
+#define ALE                     (7<<0)
+#define BankSize16M             (0<<0)
+#define BankSize8M              (4<<0)
+#define BankSize4M              (5<<0)
+#define BankSize2M              (6<<0)
+#define BankSize1M              (7<<0)
+
+/* Data Read Protocol */
+#define StandardReadProtocol    (0<<4)
+#define EarlyReadProtocol       (1<<4)
+#define DRP                     (1<<4)
+
+/*------------------------*/
+/* Remap Control Register */
+/*------------------------*/
+
+#define RCB                     (1<<0)
+
+/*--------------------------------*/
+/* Device Dependancies Definition */
+/*--------------------------------*/
+
+#ifdef AT91M40400
+/* External Bus Interface User Interface BAse Address */
+#define EBI_BASE            ((StructEBI *) 0xFFE00000)
+#endif
+
+#endif /* ebi_h */

Demo/ARM7_AT91FR40008_GCC/main.c

@@ -0,0 +1,469 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ * 
+ * Main.c also creates a task called "Check".  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.
+ * Each task (other than the "flash" tasks) maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * check task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles the onboard LED.  Should any task contain an error at any time 
+ * the LED toggle rate will change from 3 seconds to 500ms.
+ *
+ * To check the operation of the memory allocator the check task also 
+ * dynamically creates a task before delaying, and deletes it again when it 
+ * wakes.  If memory cannot be allocated for the new task the call to xTaskCreate
+ * will fail and an error is signalled.  The dynamically created task itself
+ * allocates and frees memory just to give the allocator a bit more exercise.
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "integer.h"
+#include "PollQ.h"
+#include "comtest2.h"
+#include "semtest.h"
+#include "flop.h"
+#include "dynamic.h"
+#include "BlockQ.h"
+#include "serial.h"
+
+/* Hardware specific definitions. */
+#include "aic.h"
+#include "ebi.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants for the ComTest tasks. */
+#define mainCOM_TEST_BAUD_RATE	( ( unsigned portLONG ) 115200 )
+#define mainCOM_TEST_LED		( 5 )
+
+/* Priorities for the demo application tasks. */
+#define mainLED_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 2 )
+
+/* The rate at which the on board LED will toggle when there is/is not an 
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+#define mainON_BOARD_LED_BIT		( ( unsigned portLONG ) 7 )
+
+/* Constants used by the vMemCheckTask() task. */
+#define mainCOUNT_INITIAL_VALUE		( ( unsigned portLONG ) 0 )
+#define mainNO_TASK					( 0 )
+
+/* The size of the memory blocks allocated by the vMemCheckTask() task. */
+#define mainMEM_CHECK_SIZE_1		( ( size_t ) 51 )
+#define mainMEM_CHECK_SIZE_2		( ( size_t ) 52 )
+#define mainMEM_CHECK_SIZE_3		( ( size_t ) 151 )
+
+#define MAX_WAIT_STATES  8
+static const unsigned portLONG ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] =
+{
+	WaitState1,/* There is no "zero wait state" value, so use one wait state */
+	WaitState1,
+	WaitState2,
+	WaitState3,
+	WaitState4,
+	WaitState5,
+	WaitState6,
+	WaitState7,
+	WaitState8
+};
+/*-----------------------------------------------------------*/
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );
+
+/*
+ * The task that executes at the highest priority and calls 
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Dynamically created and deleted during each cycle of the vErrorChecks()
+ * task.  This is done to check the operation of the memory allocator.
+ * See the top of vErrorChecks for more details.
+ */
+static void vMemCheckTask( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Olimex demo board.  This includes
+ * setup for the I/O, system clock, and access timings.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler. 
+ */
+int main( void )
+{
+	/* Setup the hardware for use with the Olimex demo board. */
+	prvSetupHardware();
+
+	/* Start the demo/test application tasks. */
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartMathTasks( tskIDLE_PRIORITY );
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartDynamicPriorityTasks();	
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */
+	xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Now all the tasks have been started - start the scheduler.
+
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here. */
+	vTaskStartScheduler();
+
+	/* Should never reach here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+unsigned portLONG ulMemCheckTaskRunningCount;
+xTaskHandle xCreatedTask;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the on board LED flash rate will increase. 
+	
+	In addition to the standard tests the memory allocator is tested through
+	the dynamic creation and deletion of a task each cycle.  Each time the 
+	task is created memory must be allocated for its stack.  When the task is
+	deleted this memory is returned to the heap.  If the task cannot be created 
+	then it is likely that the memory allocation failed. */
+
+	for( ;; )
+	{
+		/* Reset xCreatedTask.  This is modified by the task about to be 
+		created so we can tell if it is executing correctly or not. */
+		xCreatedTask = mainNO_TASK;
+
+		/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a 
+		parameter. */
+		ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;		
+		if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
+		{
+			/* Could not create the task - we have probably run out of heap. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		/* Delay until it is time to execute again. */
+		vTaskDelay( xDelayPeriod );
+
+		/* Delete the dynamically created task. */
+		if( xCreatedTask != mainNO_TASK )
+		{
+			vTaskDelete( xCreatedTask );
+		}
+
+		/* Check all the standard demo application tasks are executing without 
+		error.  ulMemCheckTaskRunningCount is checked to ensure it was
+		modified by the task just deleted. */
+		if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		/* The toggle rate of the LED depends on how long this task delays for.
+		An error reduces the delay period and so increases the toggle rate. */
+		vParTestToggleLED( mainON_BOARD_LED_BIT );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+portLONG lCount;
+
+	#ifdef RUN_FROM_ROM
+	{
+	portFLOAT nsecsPerClockTick;
+	portLONG lNumWaitStates;
+	unsigned portLONG ulCSRWaitValue;
+
+		/* We are compiling to run from ROM (either on-chip or off-chip flash).
+		Leave the RAM/flash mapped the way they are on reset
+		(flash @ 0x00000000, RAM @ 0x00300000), and set up the
+		proper flash wait states (starts out at the maximum number
+		of wait states on reset, so we should be able to reduce it).
+		Most of this code will probably get removed by the compiler
+		if optimization is enabled, since these calculations are
+		based on constants.  But the compiler should still produce
+		a correct wait state register value. */
+		nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ;
+		lNumWaitStates = ( portLONG )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1;
+
+		if( lNumWaitStates < 0 )
+		{
+			lNumWaitStates = 0;
+		}
+
+		if( lNumWaitStates > MAX_WAIT_STATES )
+		{
+			lNumWaitStates = MAX_WAIT_STATES;
+		}
+
+		ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ];
+		ulCSRWaitValue = WaitState5;
+
+		AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable
+									   | PageSize1M | tDF_0cycle 
+									   | ByteWriteAccessType | CSEnable
+									   | 0x00000000 /* Base Address */;
+	}
+	#else  /* else we are compiling to run from on-chip RAM */
+	{
+		/* If compiling to run from RAM, we expect the on-chip RAM to already
+		be mapped at 0x00000000.  This is typically done with an initialization
+		script for the JTAG emulator you are using to download and run the
+		demo application. So there is nothing to do here in this case. */
+	}
+	#endif
+
+	/* Disable all interrupts at the AIC level initially... */
+	AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
+
+	/* Set all SVR and SMR entries to default values (start with a clean slate)... */
+	for( lCount = 0; lCount < 32; lCount++ )
+	{
+		AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0;
+		AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
+	}
+
+	/* Disable clocks to all peripherals initially... */
+	AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF;
+
+	/* Clear all interrupts at the AIC level initially... */
+	AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
+
+	/* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out 
+	nIRQ */
+	for( lCount = 0; lCount < 8; lCount++ )
+	{
+		AT91C_BASE_AIC->AIC_EOICR = 0;
+	}
+
+	/* Initialise LED outputs. */
+	vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
+	{
+		/* The vMemCheckTask did not increment the counter - it must
+		have failed. */
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void vMemCheckTask( void *pvParameters )
+{
+unsigned portLONG *pulMemCheckTaskRunningCounter;
+void *pvMem1, *pvMem2, *pvMem3;
+static portLONG lErrorOccurred = pdFALSE;
+
+	/* This task is dynamically created then deleted during each cycle of the
+	vErrorChecks task to check the operation of the memory allocator.  Each time
+	the task is created memory is allocated for the stack and TCB.  Each time
+	the task is deleted this memory is returned to the heap.  This task itself
+	exercises the allocator by allocating and freeing blocks. 
+	
+	The task executes at the idle priority so does not require a delay. 
+	
+	pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
+	vErrorChecks() task that this task is still executing without error. */
+
+	pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;
+
+	for( ;; )
+	{
+		if( lErrorOccurred == pdFALSE )
+		{
+			/* We have never seen an error so increment the counter. */
+			( *pulMemCheckTaskRunningCounter )++;
+		}
+		else
+		{
+			/* There has been an error so reset the counter so the check task 
+			can tell that an error occurred. */
+			*pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;
+		}
+
+		/* Allocate some memory - just to give the allocator some extra 
+		exercise.  This has to be in a critical section to ensure the
+		task does not get deleted while it has memory allocated. */
+		vTaskSuspendAll();
+		{
+			pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
+			if( pvMem1 == NULL )
+			{
+				lErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
+				vPortFree( pvMem1 );
+			}
+		}
+		xTaskResumeAll();
+
+		/* Again - with a different size block. */
+		vTaskSuspendAll();
+		{
+			pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
+			if( pvMem2 == NULL )
+			{
+				lErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
+				vPortFree( pvMem2 );
+			}
+		}
+		xTaskResumeAll();
+
+		/* Again - with a different size block. */
+		vTaskSuspendAll();
+		{
+			pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
+			if( pvMem3 == NULL )
+			{
+				lErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
+				vPortFree( pvMem3 );
+			}
+		}
+		xTaskResumeAll();
+	}
+}
+

Demo/ARM7_AT91FR40008_GCC/pio.h

@@ -0,0 +1,149 @@
+//*---------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*---------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*-----------------------------------------------------------------------------
+//* File Name           : pio.h
+//* Object              : Parallel I/O Definition File
+//* Translator          : ARM Software Development Toolkit V2.11a
+//*
+//* 1.0 20/10/97 JCZ    : Creation
+//* 2.0 21/10/98 JCZ    : Clean up
+//*---------------------------------------------------------------------------
+
+#ifndef pio_h
+#define pio_h
+
+/*---------------------------------------------*/
+/* Parallel I/O Interface Structure Definition */
+/*---------------------------------------------*/
+
+typedef struct
+{
+    at91_reg        PIO_PER ;           /* PIO Enable Register */
+    at91_reg        PIO_PDR ;           /* PIO Disable Register */
+    at91_reg        PIO_PSR ;           /* PIO Status Register */
+    at91_reg        Reserved0 ;
+    at91_reg        PIO_OER ;           /* Output Enable Register */
+    at91_reg        PIO_ODR ;           /* Output Disable Register */
+    at91_reg        PIO_OSR ;           /* Output Status Register */
+    at91_reg        Reserved1 ;
+    at91_reg        PIO_IFER ;          /* Input Filter Enable Register */
+    at91_reg        PIO_IFDR ;          /* Input Filter Disable Register */
+    at91_reg        PIO_IFSR ;          /* Input Filter Status Register */
+    at91_reg        Reserved2 ;
+    at91_reg        PIO_SODR ;          /* Set Output Data Register */
+    at91_reg        PIO_CODR ;          /* Clear Output Data Register */
+    at91_reg        PIO_ODSR ;          /* Output Data Status Register */
+    at91_reg        PIO_PDSR ;          /* Pin Data Status Register */
+    at91_reg        PIO_IER ;           /* Interrupt Enable Register */
+    at91_reg        PIO_IDR ;           /* Interrupt Disable Register */
+    at91_reg        PIO_IMR ;           /* Interrupt Mask Register */
+    at91_reg        PIO_ISR ;           /* Interrupt Status Register */
+} StructPIO ;
+
+/*-----------------------------*/
+/* PIO Handler type definition */
+/*-----------------------------*/
+
+//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
+
+/*--------------------------------*/
+/* Device Dependancies Definition */
+/*--------------------------------*/
+
+/* Number of PIO Controller */
+#define NB_PIO_CTRL     1
+/* Base Address */
+#define PIO_BASE        ((StructPIO *) 0xFFFF0000 )
+/* Number of PIO Lines */
+#define NB_PIO          32
+
+/* Parallel I/O Bits Definition */
+#define P0              (1<<0)
+#define P1              (1<<1)
+#define P2              (1<<2)
+#define P3              (1<<3)
+#define P4              (1<<4)
+#define P5              (1<<5)
+#define P6              (1<<6)
+#define P7              (1<<7)
+#define P8              (1<<8)
+#define P9              (1<<9)
+#define P10             (1<<10)
+#define P11             (1<<11)
+#define P12             (1<<12)
+#define P13             (1<<13)
+#define P14             (1<<14)
+#define P15             (1<<15)
+#define P16             (1<<16)
+#define P17             (1<<17)
+#define P18             (1<<18)
+#define P19             (1<<19)
+#define P20             (1<<20)
+#define P21             (1<<21)
+#define P22             (1<<22)
+#define P23             (1<<23)
+#define P24             (1<<24)
+#define P25             (1<<25)
+#define P26             (1<<26)
+#define P27             (1<<27)
+#define P28             (1<<28)
+#define P29             (1<<29)
+#define P30             (1<<30)
+#define P31             (1<<31)
+
+/* PIO Multiplexing Definition */
+
+/* There is only one PIO Controller */
+#define PIO_CTRL        0
+
+#define PIO_TC0         PIO_CTRL
+#define TCLK0           P0
+#define TIOA0           P1
+#define TIOB0           P2
+#define PIN_TC0         (TIOA0|TIOB0|TCLK0)
+
+#define PIO_TC1         PIO_CTRL
+#define TCLK1           P3
+#define TIOA1           P4
+#define TIOB1           P5
+#define PIN_TC1         (TIOA1|TIOB1|TCLK1)
+
+#define PIO_TC2         PIO_CTRL
+#define TCLK2           P6
+#define TIOA2           P7
+#define TIOB2           P8
+#define PIN_TC2         (TIOA2|TIOB2|TCLK2)
+
+#define PIO_EXT_IRQ     PIO_CTRL
+#define PIN_IRQ0        P9
+#define PIN_IRQ1        P10
+#define PIN_IRQ2        P11
+#define PIN_FIQ         P12
+
+#define PIO_USART0      PIO_CTRL
+#define SCK0            P13
+#define TXD0            P14
+#define RXD0            P15
+#define PIN_USART0      (SCK0|TXD0|RXD0)
+
+#define PIO_USART1      PIO_CTRL
+#define SCK1            P20
+#define TXD1            P21
+#define RXD1            P22
+#define PIN_USART1      (SCK1|TXD1|RXD1)
+
+#define MCKO            P25
+#define CS2             P26
+#define CS3             P27
+#define CS4             P31
+#define CS5             P30
+#define CS6             P29
+#define CS7             P28
+
+#endif /* pio_h */

Demo/ARM7_AT91FR40008_GCC/ram_arm.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=NO
+set DEBUG=-g
+set OPTIM=-O0
+set RUN_MODE=RUN_FROM_RAM
+set LDSCRIPT=atmel-ram.ld
+make

Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=YES
+set DEBUG=-g
+set OPTIM=-O0
+set RUN_MODE=RUN_FROM_RAM
+set LDSCRIPT=atmel-ram.ld
+make

Demo/ARM7_AT91FR40008_GCC/rom_arm.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=NO
+set DEBUG=-g
+set OPTIM=-O2
+set RUN_MODE=RUN_FROM_ROM
+set LDSCRIPT=atmel-rom.ld
+make

Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=YES
+set DEBUG=-g
+set OPTIM=-O2
+set RUN_MODE=RUN_FROM_ROM
+set LDSCRIPT=atmel-rom.ld
+make

Demo/ARM7_AT91FR40008_GCC/serial/serial.c

@@ -0,0 +1,228 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. 
+
+	This file contains all the serial port components that can be compiled to
+	either ARM or THUMB mode.  Components that must be compiled to ARM mode are
+	contained in serialISR.c.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+#include "AT91R40008.h"
+#include "usart.h"
+#include "pio.h"
+#include "aic.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup and access the UART. */
+#define portUSART0_AIC_CHANNEL	( ( unsigned portLONG ) 2 )
+
+#define serINVALID_QUEUE		( ( xQueueHandle ) 0 )
+#define serHANDLE				( ( xComPortHandle ) 1 )
+#define serNO_BLOCK				( ( portTickType ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars; 
+static xQueueHandle xCharsForTx; 
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The queues are created in serialISR.c as they are used from the ISR.
+ * Obtain references to the queues and THRE Empty flag. 
+ */
+extern void vSerialISRCreateQueues(  unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx );
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulSpeed;
+unsigned portLONG ulCD;
+xComPortHandle xReturn = serHANDLE;
+extern void ( vUART_ISR )( void );
+
+	/* The queues are used in the serial ISR routine, so are created from
+	serialISR.c (which is always compiled to ARM mode. */
+	vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );
+
+	if( 
+		( xRxedChars != serINVALID_QUEUE ) && 
+		( xCharsForTx != serINVALID_QUEUE ) && 
+		( ulWantedBaud != ( unsigned portLONG ) 0 ) 
+	  )
+	{
+		portENTER_CRITICAL();
+		{
+			/* Enable clock to USART0... */
+			AT91C_BASE_PS->PS_PCER = AT91C_PS_US0;
+
+			/* Disable all USART0 interrupt sources to begin... */
+			AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
+
+			/* Reset various status bits (just in case)... */
+			AT91C_BASE_US0->US_CR = US_RSTSTA;
+
+			AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0;  /* Enable RXD and TXD pins */
+			AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS;
+
+			/* Clear Transmit and Receive Counters */
+			AT91C_BASE_US0->US_RCR = 0;
+			AT91C_BASE_US0->US_TCR = 0;
+
+			/* Input clock to baud rate generator is MCK */
+			ulSpeed = configCPU_CLOCK_HZ * 10;  
+			ulSpeed = ulSpeed / 16;
+			ulSpeed = ulSpeed / ulWantedBaud;
+			
+			/* compute the error */
+			ulCD  = ulSpeed / 10;
+			if ((ulSpeed - (ulCD * 10)) >= 5)
+			ulCD++;
+
+			/* Define the baud rate divisor register */
+			AT91C_BASE_US0->US_BRGR = ulCD;
+
+			/* Define the USART mode */
+			AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL;
+
+			/* Write the Timeguard Register */
+			AT91C_BASE_US0->US_TTGR = 0;
+
+			/* Setup the interrupt for USART0.
+
+			Store interrupt handler function address in USART0 vector register... */
+			AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR;
+			
+			/* USART0 interrupt level-sensitive, priority 1... */
+			AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1;
+			
+			/* Clear some pending USART0 interrupts (just in case)... */
+			AT91C_BASE_US0->US_CR = US_RSTSTA;
+
+			/* Enable USART0 interrupt sources (but not Tx for now)... */
+			AT91C_BASE_US0->US_IER = US_RXRDY;
+
+			/* Enable USART0 interrupts in the AIC... */
+			AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL );
+
+			/* Enable receiver and transmitter... */
+			AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN;
+		}
+		portEXIT_CRITICAL();
+	}
+	else
+	{
+		xReturn = ( xComPortHandle ) 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+	/* NOTE: This implementation does not handle the queue being full as no
+	block time is used! */
+
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+
+	/* Send each character in the string, one at a time. */
+	pxNext = ( signed portCHAR * ) pcString;
+	while( *pxNext )
+	{
+		xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+		pxNext++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+	/* Place the character in the queue of characters to be transmitted. */
+	if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
+	{
+		return pdFAIL;
+	}
+
+	/* Turn on the Tx interrupt so the ISR will remove the character from the
+	queue and send it.   This does not need to be in a critical section as
+	if the interrupt has already removed the character the next interrupt
+	will simply turn off the Tx interrupt again. */
+	AT91C_BASE_US0->US_IER = US_TXRDY;
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+	/* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+

Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c

@@ -0,0 +1,144 @@
+/*
+  FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+  This file is part of the FreeRTOS.org distribution.
+
+  FreeRTOS.org is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  FreeRTOS.org is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with FreeRTOS.org; if not, write to the Free Software
+  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+  A special exception to the GPL can be applied should you wish to distribute
+  a combined work that includes FreeRTOS.org, without being obliged to provide
+  the source code for any proprietary components.  See the licensing section 
+  of http://www.FreeRTOS.org for full details of how and when the exception
+  can be applied.
+
+  ***************************************************************************
+  See http://www.FreeRTOS.org for documentation, latest information, license 
+  and contact details.  Please ensure to read the configuration and relevant 
+  port sections of the online documentation.
+  ***************************************************************************
+*/
+
+
+/* 
+  BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. 
+
+  This file contains all the serial port components that must be compiled
+  to ARM mode.  The components that can be compiled to either ARM or THUMB
+  mode are contained in serial.c.
+
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+#include "AT91R40008.h"
+#include "usart.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constant to access the AIC. */
+#define serCLEAR_AIC_INTERRUPT      ( ( unsigned portLONG ) 0 )
+
+/* Constants to determine the ISR source. */
+#define serSOURCE_THRE				( ( unsigned portCHAR ) 0x02 )
+#define serSOURCE_RX_TIMEOUT		( ( unsigned portCHAR ) 0x0c )
+#define serSOURCE_ERROR				( ( unsigned portCHAR ) 0x06 )
+#define serSOURCE_RX				( ( unsigned portCHAR ) 0x04 )
+#define serINTERRUPT_SOURCE_MASK    ( ( unsigned portLONG ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) )
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars; 
+static xQueueHandle xCharsForTx; 
+
+/*-----------------------------------------------------------*/
+
+/* UART0 interrupt service routine.  This can cause a context switch so MUST
+be declared "naked". */
+void vUART_ISR( void ) __attribute__ ((naked));
+
+/*-----------------------------------------------------------*/
+void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )
+{
+	/* Create the queues used to hold Rx and Tx characters. */
+	xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+	xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+	/* Pass back a reference to the queues so the serial API file can 
+	post/receive characters. */
+	*pxRxedChars = xRxedChars;
+	*pxCharsForTx = xCharsForTx;
+}
+/*-----------------------------------------------------------*/
+
+void vUART_ISR( void )
+{
+	/* This ISR can cause a context switch, so the first statement must be a
+	call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
+	variable declarations. */
+	portENTER_SWITCHING_ISR();
+
+	/* Now we can declare the local variables. */
+	signed portCHAR cChar;
+	portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
+	unsigned portLONG ulStatus;
+
+	/* What caused the interrupt? */
+	ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR;
+
+	if (ulStatus & US_TXRDY)
+	{
+		/* The interrupt was caused by the THR becoming empty.  Are there any
+		more characters to transmit? */
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
+		{
+			/* A character was retrieved from the queue so can be sent to the
+			THR now. */
+			AT91C_BASE_US0->US_THR = cChar;
+		}
+		else
+		{
+			/* Queue empty, nothing to send so turn off the Tx interrupt. */
+			AT91C_BASE_US0->US_IDR = US_TXRDY;
+		}    
+	}
+
+	if (ulStatus & US_RXRDY)
+	{
+		/* The interrupt was caused by the receiver getting data. */
+		cChar = AT91C_BASE_US0->US_RHR;
+
+		if (xQueueSendFromISR(xRxedChars, &cChar, pdFALSE))
+		{
+			xTaskWokenByRx = pdTRUE;
+		}
+	}
+
+	// Acknowledge the interrupt at AIC level...
+	AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT;
+
+	/* Exit the ISR.  If a task was woken by either a character being received
+	or transmitted then a context switch will occur. */
+	portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
+}
+/*-----------------------------------------------------------*/
+

Demo/ARM7_AT91FR40008_GCC/tc.h

@@ -0,0 +1,301 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*-----------------------------------------------------------------------------
+//* File Name           : tc.h
+//* Object              : Timer Counter Header File
+//*
+//* 1.0 01/04/00 JCZ    : Creation
+//* 1.0 01/09/00 JPP    : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT,
+//*                       TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT
+//*-----------------------------------------------------------------------------
+
+#ifndef tc_h
+#define tc_h
+
+//#include    "periph/stdc/std_c.h"
+//#include    "periph/pio/lib_pio.h"
+
+/*-------------------------------------------*/
+/* Timer User Interface Structure Definition */
+/*-------------------------------------------*/
+
+typedef struct
+{
+    at91_reg        TC_CCR ;        /* Control Register */
+    at91_reg        TC_CMR ;        /* Mode Register */
+    at91_reg        Reserved0 ;
+    at91_reg        Reserved1 ;
+    at91_reg        TC_CV ;         /* Counter value */
+    at91_reg        TC_RA ;         /* Register A */
+    at91_reg        TC_RB ;         /* Register B */
+    at91_reg        TC_RC ;         /* Register C */
+    at91_reg        TC_SR ;         /* Status Register */
+    at91_reg        TC_IER ;        /* Interrupt Enable Register */
+    at91_reg        TC_IDR ;        /* Interrupt Disable Register */
+    at91_reg        TC_IMR ;        /* Interrupt Mask Register */
+    at91_reg        Reserved2 ;
+    at91_reg        Reserved3 ;
+    at91_reg        Reserved4 ;
+    at91_reg        Reserved5 ;
+} StructTC ;
+
+#define NB_TC_CHANNEL       3
+
+typedef struct
+{
+    StructTC        TC[NB_TC_CHANNEL] ;
+    at91_reg        TC_BCR ;        /* Block Control Register */
+    at91_reg        TC_BMR ;        /* Block Mode Register  */
+} StructTCBlock ;
+
+/*--------------------------------------------------------*/
+/* TC_CCR: Timer Counter Control Register Bits Definition */
+/*--------------------------------------------------------*/
+#define TC_CLKEN            0x1
+#define TC_CLKDIS           0x2
+#define TC_SWTRG            0x4
+
+/*---------------------------------------------------------------*/
+/* TC_CMR: Timer Counter Channel Mode Register Bits Definition   */
+/*---------------------------------------------------------------*/
+
+/*-----------------*/
+/* Clock Selection */
+/*-----------------*/
+#define TC_CLKS                  0x7
+#define TC_CLKS_MCK2             0x0
+#define TC_CLKS_MCK8             0x1
+#define TC_CLKS_MCK32            0x2
+#define TC_CLKS_MCK128           0x3
+#define TC_CLKS_MCK1024          0x4
+
+#define TC_CLKS_SLCK             0x4
+
+#define TC_CLKS_XC0              0x5
+#define TC_CLKS_XC1              0x6
+#define TC_CLKS_XC2              0x7
+
+
+/*-----------------*/
+/* Clock Inversion */
+/*-----------------*/
+#define TC_CLKI             0x8
+
+/*------------------------*/
+/* Burst Signal Selection */
+/*------------------------*/
+#define TC_BURST            0x30
+#define TC_BURST_NONE       0x0
+#define TC_BUSRT_XC0        0x10
+#define TC_BURST_XC1        0x20
+#define TC_BURST_XC2        0x30
+
+/*------------------------------------------------------*/
+/* Capture Mode : Counter Clock Stopped with RB Loading */
+/*------------------------------------------------------*/
+#define TC_LDBSTOP          0x40
+
+/*-------------------------------------------------------*/
+/* Waveform Mode : Counter Clock Stopped with RC Compare */
+/*-------------------------------------------------------*/
+#define TC_CPCSTOP          0x40
+
+/*-------------------------------------------------------*/
+/* Capture Mode : Counter Clock Disabled with RB Loading */
+/*--------------------------------------------------------*/
+#define TC_LDBDIS           0x80
+
+/*--------------------------------------------------------*/
+/* Waveform Mode : Counter Clock Disabled with RC Compare */
+/*--------------------------------------------------------*/
+#define TC_CPCDIS           0x80
+
+/*------------------------------------------------*/
+/* Capture Mode : External Trigger Edge Selection */
+/*------------------------------------------------*/
+#define TC_ETRGEDG                  0x300
+#define TC_ETRGEDG_EDGE_NONE        0x0
+#define TC_ETRGEDG_RISING_EDGE      0x100
+#define TC_ETRGEDG_FALLING_EDGE     0x200
+#define TC_ETRGEDG_BOTH_EDGE        0x300
+
+/*-----------------------------------------------*/
+/* Waveform Mode : External Event Edge Selection */
+/*-----------------------------------------------*/
+#define TC_EEVTEDG                  0x300
+#define TC_EEVTEDG_EDGE_NONE        0x0
+#define TC_EEVTEDG_RISING_EDGE      0x100
+#define TC_EEVTEDG_FALLING_EDGE     0x200
+#define TC_EEVTEDG_BOTH_EDGE        0x300
+
+/*--------------------------------------------------------*/
+/* Capture Mode : TIOA or TIOB External Trigger Selection */
+/*--------------------------------------------------------*/
+#define TC_ABETRG                   0x400
+#define TC_ABETRG_TIOB              0x0
+#define TC_ABETRG_TIOA              0x400
+
+/*------------------------------------------*/
+/* Waveform Mode : External Event Selection */
+/*------------------------------------------*/
+#define TC_EEVT                     0xC00
+#define TC_EEVT_TIOB                0x0
+#define TC_EEVT_XC0                 0x400
+#define TC_EEVT_XC1                 0x800
+#define TC_EEVT_XC2                 0xC00
+
+/*--------------------------------------------------*/
+/* Waveform Mode : Enable Trigger on External Event */
+/*--------------------------------------------------*/
+#define TC_ENETRG                   0x1000
+
+/*----------------------------------*/
+/* RC Compare Enable Trigger Enable */
+/*----------------------------------*/
+#define TC_CPCTRG                   0x4000
+
+/*----------------*/
+/* Mode Selection */
+/*----------------*/
+#define TC_WAVE                     0x8000
+#define TC_CAPT                     0x0
+
+/*-------------------------------------*/
+/* Capture Mode : RA Loading Selection */
+/*-------------------------------------*/
+#define TC_LDRA                     0x30000
+#define TC_LDRA_EDGE_NONE           0x0
+#define TC_LDRA_RISING_EDGE         0x10000
+#define TC_LDRA_FALLING_EDGE        0x20000
+#define TC_LDRA_BOTH_EDGE           0x30000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RA Compare Effect on TIOA */
+/*-------------------------------------------*/
+#define TC_ACPA                     0x30000
+#define TC_ACPA_OUTPUT_NONE         0x0
+#define TC_ACPA_SET_OUTPUT          0x10000
+#define TC_ACPA_CLEAR_OUTPUT        0x20000
+#define TC_ACPA_TOGGLE_OUTPUT       0x30000
+
+/*-------------------------------------*/
+/* Capture Mode : RB Loading Selection */
+/*-------------------------------------*/
+#define TC_LDRB                     0xC0000
+#define TC_LDRB_EDGE_NONE           0x0
+#define TC_LDRB_RISING_EDGE         0x40000
+#define TC_LDRB_FALLING_EDGE        0x80000
+#define TC_LDRB_BOTH_EDGE           0xC0000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RC Compare Effect on TIOA */
+/*-------------------------------------------*/
+#define TC_ACPC                     0xC0000
+#define TC_ACPC_OUTPUT_NONE         0x0
+#define TC_ACPC_SET_OUTPUT          0x40000
+#define TC_ACPC_CLEAR_OUTPUT        0x80000
+#define TC_ACPC_TOGGLE_OUTPUT       0xC0000
+
+/*-----------------------------------------------*/
+/* Waveform Mode : External Event Effect on TIOA */
+/*-----------------------------------------------*/
+#define TC_AEEVT                    0x300000
+#define TC_AEEVT_OUTPUT_NONE        0x0
+#define TC_AEEVT_SET_OUTPUT         0x100000
+#define TC_AEEVT_CLEAR_OUTPUT       0x200000
+#define TC_AEEVT_TOGGLE_OUTPUT      0x300000
+
+/*-------------------------------------------------*/
+/* Waveform Mode : Software Trigger Effect on TIOA */
+/*-------------------------------------------------*/
+#define TC_ASWTRG                   0xC00000
+#define TC_ASWTRG_OUTPUT_NONE       0x0
+#define TC_ASWTRG_SET_OUTPUT        0x400000
+#define TC_ASWTRG_CLEAR_OUTPUT      0x800000
+#define TC_ASWTRG_TOGGLE_OUTPUT     0xC00000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RB Compare Effect on TIOB */
+/*-------------------------------------------*/
+#define TC_BCPB                     0x1000000
+#define TC_BCPB_OUTPUT_NONE         0x0
+#define TC_BCPB_SET_OUTPUT          0x1000000
+#define TC_BCPB_CLEAR_OUTPUT        0x2000000
+#define TC_BCPB_TOGGLE_OUTPUT       0x3000000
+
+/*-------------------------------------------*/
+/* Waveform Mode : RC Compare Effect on TIOB */
+/*-------------------------------------------*/
+#define TC_BCPC                     0xC000000
+#define TC_BCPC_OUTPUT_NONE         0x0
+#define TC_BCPC_SET_OUTPUT          0x4000000
+#define TC_BCPC_CLEAR_OUTPUT        0x8000000
+#define TC_BCPC_TOGGLE_OUTPUT       0xC000000
+
+/*-----------------------------------------------*/
+/* Waveform Mode : External Event Effect on TIOB */
+/*-----------------------------------------------*/
+#define TC_BEEVT                    0x30000000      //* bit 29-28
+#define TC_BEEVT_OUTPUT_NONE        0x0
+#define TC_BEEVT_SET_OUTPUT         0x10000000      //* bit 29-28  01
+#define TC_BEEVT_CLEAR_OUTPUT       0x20000000      //* bit 29-28  10
+#define TC_BEEVT_TOGGLE_OUTPUT      0x30000000      //* bit 29-28  11
+
+/*- -----------------------------------------------*/
+/* Waveform Mode : Software Trigger Effect on TIOB */
+/*-------------------------------------------------*/
+#define TC_BSWTRG                   0xC0000000
+#define TC_BSWTRG_OUTPUT_NONE       0x0
+#define TC_BSWTRG_SET_OUTPUT        0x40000000
+#define TC_BSWTRG_CLEAR_OUTPUT      0x80000000
+#define TC_BSWTRG_TOGGLE_OUTPUT     0xC0000000
+
+/*------------------------------------------------------*/
+/* TC_SR: Timer Counter Status Register Bits Definition */
+/*------------------------------------------------------*/
+#define TC_COVFS            0x1         /* Counter Overflow Status */
+#define TC_LOVRS            0x2         /* Load Overrun Status */
+#define TC_CPAS             0x4         /* RA Compare Status */
+#define TC_CPBS             0x8         /* RB Compare Status */
+#define TC_CPCS             0x10        /* RC Compare Status */
+#define TC_LDRAS            0x20        /* RA Loading Status */
+#define TC_LDRBS            0x40        /* RB Loading Status */
+#define TC_ETRGS            0x80        /* External Trigger Status */
+#define TC_CLKSTA           0x10000     /* Clock Status */
+#define TC_MTIOA            0x20000     /* TIOA Mirror */
+#define TC_MTIOB            0x40000     /* TIOB Status */
+
+/*--------------------------------------------------------------*/
+/* TC_BCR: Timer Counter Block Control Register Bits Definition */
+/*--------------------------------------------------------------*/
+#define TC_SYNC             0x1         /* Synchronisation Trigger */
+
+/*------------------------------------------------------------*/
+/*  TC_BMR: Timer Counter Block Mode Register Bits Definition */
+/*------------------------------------------------------------*/
+#define TC_TC0XC0S          0x3        /* External Clock Signal 0 Selection */
+#define TC_TCLK0XC0         0x0
+#define TC_NONEXC0          0x1
+#define TC_TIOA1XC0         0x2
+#define TC_TIOA2XC0         0x3
+
+#define TC_TC1XC1S          0xC        /* External Clock Signal 1 Selection */
+#define TC_TCLK1XC1         0x0
+#define TC_NONEXC1          0x4
+#define TC_TIOA0XC1         0x8
+#define TC_TIOA2XC1         0xC
+
+#define TC_TC2XC2S          0x30       /* External Clock Signal 2 Selection */
+#define TC_TCLK2XC2         0x0
+#define TC_NONEXC2          0x10
+#define TC_TIOA0XC2         0x20
+#define TC_TIOA1XC2         0x30
+
+#endif /* tc_h */
+

Demo/ARM7_AT91FR40008_GCC/usart.h

@@ -0,0 +1,151 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*-----------------------------------------------------------------------------
+//* File Name           : usart.h
+//* Object              : USART Header File.
+//*
+//* 1.0 01/04/00 JCZ    : Creation
+//*----------------------------------------------------------------------------
+
+#ifndef usart_h
+#define usart_h
+
+//#include    "periph/stdc/std_c.h"
+//#include    "periph/pio/lib_pio.h"
+
+/*-------------------------------------------*/
+/* USART User Interface Structure Definition */
+/*-------------------------------------------*/
+
+typedef struct
+{
+    at91_reg            US_CR ;         /* Control Register */
+    at91_reg            US_MR ;         /* Mode Register */
+    at91_reg            US_IER ;        /* Interrupt Enable Register */
+    at91_reg            US_IDR ;        /* Interrupt Disable Register */
+    at91_reg            US_IMR ;        /* Interrupt Mask Register */
+    at91_reg            US_CSR ;        /* Channel Status Register */
+    at91_reg            US_RHR ;        /* Receive Holding Register */
+    at91_reg            US_THR ;        /* Transmit Holding Register */
+    at91_reg            US_BRGR ;       /* Baud Rate Generator Register */
+    at91_reg            US_RTOR ;       /* Receiver Timeout Register */
+    at91_reg            US_TTGR ;       /* Transmitter Time-guard Register */
+    at91_reg            Reserved ;
+    at91_reg            US_RPR ;        /* Receiver Pointer Register */
+    at91_reg            US_RCR ;        /* Receiver Counter Register */
+    at91_reg            US_TPR ;        /* Transmitter Pointer Register */
+    at91_reg            US_TCR ;        /* Transmitter Counter Register */
+} StructUSART ;
+
+/*--------------------------*/
+/* US_CR : Control Register */
+/*--------------------------*/
+
+#define US_RSTRX                0x0004      /* Reset Receiver */
+#define US_RSTTX                0x0008      /* Reset Transmitter */
+#define US_RXEN                 0x0010      /* Receiver Enable */
+#define US_RXDIS                0x0020      /* Receiver Disable */
+#define US_TXEN                 0x0040      /* Transmitter Enable */
+#define US_TXDIS                0x0080      /* Transmitter Disable */
+#define US_RSTSTA               0x0100      /* Reset Status Bits */
+#define US_STTBRK               0x0200      /* Start Break */
+#define US_STPBRK               0x0400      /* Stop Break */
+#define US_STTTO                0x0800      /* Start Time-out */
+#define US_SENDA                0x1000      /* Send Address */
+
+/*-----------------------*/
+/* US_MR : Mode Register */
+/*-----------------------*/
+
+#define US_CLKS                 0x0030      /* Clock Selection */
+#define US_CLKS_MCK             0x00        /* Master Clock */
+#define US_CLKS_MCK8            0x10        /* Master Clock divided by 8 */
+#define US_CLKS_SCK             0x20        /* External Clock */
+#define US_CLKS_SLCK            0x30        /* Slow Clock */
+
+#define US_CHRL                 0x00C0      /* Byte Length */
+#define US_CHRL_5               0x00        /* 5 bits */
+#define US_CHRL_6               0x40        /* 6 bits */
+#define US_CHRL_7               0x80        /* 7 bits */
+#define US_CHRL_8               0xC0        /* 8 bits */
+
+#define US_SYNC                 0x0100      /* Synchronous Mode Enable */
+
+#define US_PAR                  0x0E00      /* Parity Mode */
+#define US_PAR_EVEN             0x00        /* Even Parity */
+#define US_PAR_ODD              0x200       /* Odd Parity */
+#define US_PAR_SPACE            0x400       /* Space Parity to 0 */
+#define US_PAR_MARK             0x600       /* Marked Parity to 1 */
+#define US_PAR_NO               0x800       /* No Parity */
+#define US_PAR_MULTIDROP        0xC00       /* Multi-drop Mode */
+
+#define US_NBSTOP               0x3000      /* Stop Bit Number */
+#define US_NBSTOP_1             0x0000      /* 1 Stop Bit */
+#define US_NBSTOP_1_5           0x1000      /* 1.5 Stop Bits */
+#define US_NBSTOP_2             0x2000      /* 2 Stop Bits */
+
+#define US_CHMODE                   0xC000  /* Channel Mode */
+#define US_CHMODE_NORMAL            0x0000  /* Normal Mode */
+#define US_CHMODE_AUTOMATIC_ECHO    0x4000  /* Automatic Echo */
+#define US_CHMODE_LOCAL_LOOPBACK    0x8000  /* Local Loopback */
+#define US_CHMODE_REMOTE_LOOPBACK   0xC000  /* Remote Loopback */
+
+#define US_MODE9                0x20000     /* 9 Bit Mode */
+
+#define US_CLKO                 0x40000     /* Baud Rate Output Enable */
+
+/* Mode Register model */
+
+/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
+#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
+                        US_NBSTOP_1 + \
+                        US_PAR_NO + \
+                        US_CHRL_8 + \
+                        US_CLKS_MCK )
+
+/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
+#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \
+                            US_NBSTOP_1 + \
+                            US_PAR_NO + \
+                            US_CHRL_8 + \
+                            US_CLKS_SCK )
+
+/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
+#define US_SYNC_MODE ( US_SYNC + \
+                       US_CHMODE_NORMAL + \
+                       US_NBSTOP_1 + \
+                       US_PAR_NO + \
+                       US_CHRL_8 + \
+                       US_CLKS_MCK )
+
+/* SCK used Label */
+#define SCK_USED (US_CLKO | US_CLKS_SCK)
+
+/*---------------------------------------------------------------*/
+/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */
+/*---------------------------------------------------------------*/
+
+#define US_RXRDY            0x1       /* Receiver Ready */
+#define US_TXRDY            0x2       /* Transmitter Ready */
+#define US_RXBRK            0x4       /* Receiver Break */
+#define US_ENDRX            0x8       /* End of Receiver PDC Transfer */
+#define US_ENDTX            0x10       /* End of Transmitter PDC Transfer */
+#define US_OVRE             0x20       /* Overrun Error */
+#define US_FRAME            0x40       /* Framing Error */
+#define US_PARE             0x80       /* Parity Error */
+#define US_TIMEOUT          0x100       /* Receiver Timeout */
+#define US_TXEMPTY          0x200       /* Transmitter Empty */
+
+#define US_MASK_IRQ_TX      (US_TXRDY | US_ENDTX | US_TXEMPTY)
+#define US_MASK_IRQ_RX      (US_RXRDY | US_ENDRX | US_TIMEOUT)
+#define US_MASK_IRQ_ERROR   (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
+
+
+
+#endif /* usart_h */

Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h

@@ -0,0 +1,78 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <intrinsic.h>
+#include "Board.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 100 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) 14200 )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				0
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */

Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c

@@ -0,0 +1,81 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#include "FreeRTOS.h"
+#include "partest.h"
+#include "board.h"
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines for the LED's.
+ *-----------------------------------------------------------*/
+
+const unsigned portLONG led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 };
+
+void vParTestInitialise( void )
+{	
+	/* Start with all LED's off. */
+	AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK );	
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( xValue )
+		{
+			AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );
+		}
+		else
+		{
+			AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] )
+		{
+			AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);
+		}
+		else
+		{
+			AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );					
+		}
+	}
+}
+
+

Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h

@@ -0,0 +1,89 @@
+/*----------------------------------------------------------------------------
+*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name           : Board.h
+* Object              : AT91SAM7S Evaluation Board Features Definition File.
+*
+* Creation            : JPP   16/Jun/2004
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include "AT91SAM7S64.h"
+#define __inline inline
+#include "lib_AT91SAM7S64.h"
+
+#define true	-1
+#define false	0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash
+
+#define  INT_SARM           0x00200000
+#define  INT_SARM_REMAP	    0x00000000
+
+#define  INT_FLASH          0x00000000
+#define  INT_FLASH_REMAP    0x01000000
+
+#define  FLASH_PAGE_NB		512
+#define  FLASH_PAGE_SIZE	128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+/*                                 PIO   Flash    PA    PB   PIN */
+#define LED1            (1<<0)	/* PA0 / PGMEN0 & PWM0 TIOA0  48 */
+#define LED2            (1<<1)	/* PA1 / PGMEN1 & PWM1 TIOB0  47 */
+#define LED3            (1<<2)	/* PA2          & PWM2 SCK0   44 */
+#define LED4            (1<<3)	/* PA3          & TWD  NPCS3  43 */
+#define NB_LED			4
+
+#define LED_MASK        (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+/*                                 PIO    Flash    PA    PB   PIN */
+#define SW1_MASK        (1<<19)	/* PA19 / PGMD7  & RK   FIQ     13 */
+#define SW2_MASK        (1<<20)	/* PA20 / PGMD8  & RF   IRQ0    16 */
+#define SW3_MASK        (1<<15)	/* PA15 / PGM3   & TF   TIOA1   20 */
+#define SW4_MASK        (1<<14)	/* PA14 / PGMD2  & SPCK PWM3    21 */
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 	(1<<19)	// PA19
+#define SW2 	(1<<20)	// PA20
+#define SW3 	(1<<15)	// PA15
+#define SW4 	(1<<14)	// PA14
+
+/*------------------*/
+/* USART Definition */
+/*------------------*/
+/* SUB-D 9 points J3 DBGU*/
+#define DBGU_RXD		AT91C_PA9_DRXD	  /* JP11 must be close */
+#define DBGU_TXD		AT91C_PA10_DTXD	  /* JP12 must be close */
+#define AT91C_DBGU_BAUD	   115200   // Baud rate
+
+#define US_RXD_PIN		AT91C_PA5_RXD0    /* JP9 must be close */
+#define US_TXD_PIN		AT91C_PA6_TXD0    /* JP7 must be close */
+#define US_RTS_PIN		AT91C_PA7_RTS0    /* JP8 must be close */
+#define US_CTS_PIN		AT91C_PA8_CTS0    /* JP6 must be close */
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
+#define MCK             47923200   // MCK (PLLRC div by 2)
+#define MCKKHz          (MCK/1000) //
+
+#endif /* Board_h */

Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79

@@ -0,0 +1,223 @@
+;------------------------------------------------------------------------------
+;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
+;------------------------------------------------------------------------------
+; The software is delivered "AS IS" without warranty or condition of any
+; kind, either express, implied or statutory. This includes without
+; limitation any warranty or condition with respect to merchantability or
+; fitness for any particular purpose, or against the infringements of
+; intellectual property rights of others.
+;-----------------------------------------------------------------------------
+;- File source          : Cstartup.s79
+;- Object               : Generic CStartup for IAR No Use REMAP
+;- Compilation flag     : None
+;-
+;- 1.0 15/Jun/04 JPP    : Creation
+;------------------------------------------------------------------------------
+
+#include "AT91SAM7S64_inc.h"
+
+;------------------------------------------------------------------------------
+;- Area Definition
+;------------------------------------------------------------------------------
+
+;---------------------------------------------------------------
+; ?RESET
+; Reset Vector.
+; Normally, segment INTVEC is linked at address 0.
+; For debugging purposes, INTVEC may be placed at other
+; addresses.
+; A debugger that honors the entry point will start the
+; program in a normal way even if INTVEC is not at address 0.
+;-------------------------------------------------------------
+
+		PROGRAM	?RESET
+		RSEG	INTRAMSTART_REMAP
+		RSEG	INTRAMEND_REMAP
+
+		EXTERN	vPortYieldProcessor
+
+		RSEG	ICODE:CODE:ROOT(2)
+		CODE32	; Always ARM mode after reset	
+		org	0	
+reset		
+;------------------------------------------------------------------------------
+;- Exception vectors 
+;--------------------
+;- These vectors can be read at address 0 or at RAM address
+;- They ABSOLUTELY requires to be in relative addresssing mode in order to
+;- guarantee a valid jump. For the moment, all are just looping.
+;- If an exception occurs before remap, this would result in an infinite loop.
+;- To ensure if a exeption occurs before start application to infinite loop.
+;------------------------------------------------------------------------------
+
+                B           InitReset           ; 0x00 Reset handler
+undefvec:
+                B           undefvec            ; 0x04 Undefined Instruction
+swivec:
+                B           vPortYieldProcessor ; 0x08 Software Interrupt
+pabtvec:
+                B           pabtvec             ; 0x0C Prefetch Abort
+dabtvec:
+                B           dabtvec             ; 0x10 Data Abort
+rsvdvec:
+                B           rsvdvec             ; 0x14 reserved
+irqvec:
+				LDR			PC, [PC, #-0xF20]	; Jump directly to the address given by the AIC
+
+fiqvec:               							; 0x1c FIQ
+
+;------------------------------------------------------------------------------
+;- Function             : FIQ_Handler_Entry
+;- Treatments           : FIQ Controller Interrupt Handler.
+;- Called Functions     : AIC_FVR[interrupt] 
+;------------------------------------------------------------------------------
+
+FIQ_Handler_Entry:
+
+;- Switch in SVC/User Mode to allow User Stack access for C code 
+; because the FIQ is not yet acknowledged
+
+;- Save and r0 in FIQ_Register 
+            mov         r9,r0
+		    ldr         r0 , [r8, #AIC_FVR]
+            msr         CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
+
+;- Save scratch/used registers and LR in User Stack
+            stmfd       sp!, { r1-r3, r12, lr}
+
+;- Branch to the routine pointed by the AIC_FVR
+            mov         r14, pc
+            bx          r0
+
+;- Restore scratch/used registers and LR from User Stack
+            ldmia       sp!, { r1-r3, r12, lr}
+
+;- Leave Interrupts disabled and switch back in FIQ mode
+            msr         CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
+
+;- Restore the R0 ARM_MODE_SVC register 
+            mov         r0,r9
+
+;- Restore the Program Counter using the LR_fiq directly in the PC
+            subs        pc,lr,#4
+
+InitReset:
+;------------------------------------------------------------------------------
+;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
+;------------------------------------------------------------------------------
+            	EXTERN   AT91F_LowLevelInit
+
+#define  __iramend 	SFB(INTRAMEND_REMAP)
+
+;- minumum C initialization
+;- call  AT91F_LowLevelInit( void)
+
+            ldr     r13,=__iramend            ; temporary stack in internal RAM
+;--Call Low level init function in ABSOLUTE through the Interworking
+		    ldr	    r0,=AT91F_LowLevelInit
+       	    mov     lr, pc
+		    bx	    r0
+;------------------------------------------------------------------------------
+;- Stack Sizes Definition
+;------------------------
+;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
+;- the vectoring. This assume that the IRQ management.
+;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
+;- Fast Interrupt not requires stack If in your application it required you must
+;- be definehere.
+;- The System stack size is not defined and is limited by the free internal
+;- SRAM.
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;- Top of Stack Definition
+;-------------------------
+;- Interrupt and Supervisor Stack are located at the top of internal memory in 
+;- order to speed the exception handling context saving and restoring.
+;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
+;------------------------------------------------------------------------------
+
+IRQ_STACK_SIZE          EQU     300
+
+ARM_MODE_FIQ            EQU     0x11
+ARM_MODE_IRQ            EQU     0x12
+ARM_MODE_SVC            EQU     0x13
+
+I_BIT                   EQU     0x80
+F_BIT                   EQU     0x40
+
+;------------------------------------------------------------------------------
+;- Setup the stack for each mode
+;-------------------------------
+                ldr     r0, =__iramend
+
+;- Set up Fast Interrupt Mode and set FIQ Mode Stack
+                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
+;- Init the FIQ register
+            	ldr     r8, =AT91C_BASE_AIC
+
+;- Set up Interrupt Mode and set IRQ Mode Stack
+                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
+                mov     r13, r0                     ; Init stack IRQ
+                sub     r0, r0, #IRQ_STACK_SIZE
+
+;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
+                msr     CPSR_c, #ARM_MODE_SVC 
+                mov     r13, r0                     
+
+
+;---------------------------------------------------------------
+; ?CSTARTUP
+;---------------------------------------------------------------
+		EXTERN	__segment_init
+		EXTERN	main
+; Initialize segments.
+; __segment_init is assumed to use
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+		ldr	r0,=__segment_init
+                mov     lr, pc
+		bx	r0
+
+		PUBLIC	__main
+?jump_to_main:
+		ldr	lr,=?call_exit
+		ldr	r0,=main
+__main:
+		bx	r0
+
+;------------------------------------------------------------------------------
+;- Loop for ever
+;---------------
+;- End of application. Normally, never occur.
+;- Could jump on Software Reset ( B 0x0 ).
+;------------------------------------------------------------------------------
+?call_exit:
+End
+            b       End
+
+
+
+;---------------------------------------------------------------
+; ?EXEPTION_VECTOR
+; This module is only linked if needed for closing files.
+;---------------------------------------------------------------
+		PUBLIC	AT91F_Default_FIQ_handler
+		PUBLIC	AT91F_Default_IRQ_handler
+		PUBLIC	AT91F_Spurious_handler
+
+		CODE32	; Always ARM mode after exeption	
+
+AT91F_Default_FIQ_handler
+            b     AT91F_Default_FIQ_handler
+
+AT91F_Default_IRQ_handler
+            b     AT91F_Default_IRQ_handler
+
+AT91F_Spurious_handler
+            b     AT91F_Spurious_handler
+
+	ENDMOD
+
+	END
+

Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c

@@ -0,0 +1,84 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Cstartup_SAM7.c
+//* Object              : Low level initializations written in C for IAR
+//*                       tools
+//* Creation            : 12/Jun/04
+//*
+//*----------------------------------------------------------------------------
+
+
+// Include the board file description
+#include "Board.h"
+
+// The following functions must be write in ARM mode this function called directly
+// by exception vector
+extern void AT91F_Spurious_handler(void);
+extern void AT91F_Default_IRQ_handler(void);
+extern void AT91F_Default_FIQ_handler(void);
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can be use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit( void );
+void AT91F_LowLevelInit( void) @ "ICODE"
+{
+ int            i;
+ AT91PS_PMC     pPMC = AT91C_BASE_PMC;
+    //* Set Flash Waite sate
+	//  Single Cycle Access at Up to 30 MHz, or 40
+	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
+	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;
+
+    //* Watchdog Disable
+        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
+
+	//* Set MCK at 47 923 200
+    // 1 Enabling the Main Oscillator:
+        // SCK = 1/32768 = 30.51 uSeconde
+    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
+       pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
+	// 2 Checking the Main Oscillator Frequency (Optional)
+	// 3 Setting PLL and divider:
+		// - div by 5 Fin = 3,6864 =(18,432 / 5)
+		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+		// for 96 MHz the erroe is 0.16%
+		// Field out NOT USED = 0
+		// PLLCOUNT pll startup time esrtimate at : 0.844 ms
+		// PLLCOUNT 28 = 0.000844 /(1/32768)
+       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
+                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+                         (AT91C_CKGR_MUL & (25<<16)));
+
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
+	// 4. Selection of Master Clock and Processor Clock
+        // select the PLL clock divided by 2
+	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ;
+
+	// Enable User Reset and set its minimal assertion to 960 us
+	AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24);
+
+
+	// Set up the default interrupts handler vectors
+	AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
+	for (i=1;i < 31; i++)
+	{
+	    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
+	}
+	AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;
+
+}
+

Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h

@@ -0,0 +1,8 @@
+#ifndef USB_DEMO_H
+#define USB_DEMO_H
+
+void vUSBDemoTask( void *pvParameters );
+
+
+#endif
+

Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79

@@ -0,0 +1,24 @@
+		RSEG ICODE:CODE
+		CODE32
+
+		EXTERN vUSB_ISR
+		PUBLIC vUSBISREntry
+
+; Wrapper for the USB interrupt service routine.  This can cause a
+; context switch so requires an assembly wrapper.
+
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
+#include "ISR_Support.h"
+
+vUSBISREntry:
+
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	bl	vUSB_ISR				; Call the ISR routine.
+
+	portRESTORE_CONTEXT			; Restore the context of the current task -
+								; which may be different to the task that
+								; was interrupted.
+
+		END
+

Demo/ARM7_AT91SAM7S64_IAR/main.c

@@ -0,0 +1,252 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.  The SAM7
+ * includes a sample USB that emulates a Joystick input to a USB host.
+ * 
+ * Main.c also creates a task called "Check".  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.
+ * Each task (other than the "flash" tasks) maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * check task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles the onboard LED.  Should any task contain an error at any time 
+ * the LED toggle rate will change from 3 seconds to 500ms.
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "flash.h"
+#include "integer.h"
+#include "PollQ.h"
+#include "BlockQ.h"
+#include "semtest.h"
+#include "dynamic.h"
+#include "partest.h"
+#include "comtest2.h"
+#include "USB/USBSample.h"
+
+/* Priorities for the demo application tasks. */
+#define mainLED_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCOM_TEST_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainUSB_PRIORITY			( tskIDLE_PRIORITY + 2 )
+
+/* Constants required by the 'Check' task. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+#define mainCHECK_TASK_LED			( 3 )
+
+/* Constants for the ComTest tasks. */
+#define mainCOM_TEST_BAUD_RATE		( ( unsigned portLONG ) 115200 )
+#define mainCOM_TEST_LED			( 4 ) /* Off the board. */
+
+/*
+ * The task that executes at the highest priority and calls 
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Atmel demo board.  Setup is minimal
+ * as the low level init function (called from the startup asm file) takes care
+ * of most things.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler. 
+ */
+void main( void )
+{
+	/* Setup any hardware that has not already been configured by the low
+	level init routines. */
+	prvSetupHardware();
+
+	/* Initialise the LED outputs for use by the demo application tasks. */
+	vParTestInitialise();
+
+	/* Start all the standard demo application tasks. */
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+	vStartDynamicPriorityTasks();
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
+	
+	/* Also start the USB demo which is just for the SAM7. */
+	xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL );
+	
+	/* Start the check task - which is defined in this file. */
+	xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Start the scheduler.
+
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here. */
+
+	vTaskStartScheduler();
+
+	/* We should never get here as control is now taken by the scheduler. */
+  	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* When using the JTAG debugger the hardware is not always initialised to
+	the correct default state.  This line just ensures that this does not
+	cause all interrupts to be masked at the start. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+	
+	/* Most setup is performed by the low level init function called from the 
+	startup asm file. */
+
+	/* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as 
+	well as the UART Tx line. */
+	AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK );
+	
+	/* Enable the peripheral clock. */
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+
+	/* The parameters are not used in this task. */
+	( void ) pvParameters;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the on board LED flash rate will increase. */
+
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelay( xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without 
+		error. */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+		
+		vParTestToggleLED( mainCHECK_TASK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+

Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac

@@ -0,0 +1,180 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: SAM7.mac
+//
+//  User setup file for CSPY debugger to simulate interrupt
+//  driven Fibonacchi data input. 
+//  1.1 16/Jun/04 JPP    : Creation
+//
+//  $Revision: 1.3 $
+//
+// ---------------------------------------------------------
+
+__var i;
+__var pt;
+
+execUserPreload()
+{
+//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
+     CheckRemap();
+//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+    i=__readMemory32(0xFFFFF240,"Memory");
+    __message " ---------------------------------------- Chip ID   0x",i:%X;  
+    i=__readMemory32(0xFFFFF244,"Memory");
+    __message " ---------------------------------------- Extention 0x",i:%X;  
+//* Get the chip status
+
+//* Init AIC
+   AIC();
+//*  Watchdog Disable
+   Watchdog();
+
+}
+
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
+   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+   __message "------------------------------- Watchdog Disable ----------------------------------------";  
+}
+
+
+//-----------------------------------------------------------------------------
+// Check Remap
+//-------------
+//-----------------------------------------------------------------------------
+CheckRemap()
+{
+//* Read the value at 0x0
+    i=__readMemory32(0x00000000,"Memory");
+    i=i+1;
+    __writeMemory32(i,0x00,"Memory");
+    pt=__readMemory32(0x00000000,"Memory");
+    
+ if (i == pt)  
+ {
+   __message "------------------------------- The Remap is done ----------------------------------------";  
+//*   Toggel RESET The remap
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+   
+ } else {  
+   __message "------------------------------- The Remap is NOT -----------------------------------------";  
+ }
+
+}
+
+
+execUserSetup()
+{
+ ini();
+     __message "-------------------------------Set PC ----------------------------------------";  
+     __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+    __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
+
+    for (i=0;i < 8; i++)
+    {
+      // AT91C_BASE_AIC->AIC_EOICR
+      pt =  __readMemory32(0xFFFFF130,"Memory");
+    
+    }
+   __message "------------------------------- AIC INIT ---------------------------------------------";  
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+i=__readMemory32(0x00,"Register");   __message "R00 0x",i:%X;  
+i=__readMemory32(0x04,"Register");   __message "R01 0x",i:%X;  
+i=__readMemory32(0x08,"Register");   __message "R02 0x",i:%X;  
+i=__readMemory32(0x0C,"Register");   __message "R03 0x",i:%X;  
+i=__readMemory32(0x10,"Register");   __message "R04 0x",i:%X;  
+i=__readMemory32(0x14,"Register");   __message "R05 0x",i:%X;  
+i=__readMemory32(0x18,"Register");   __message "R06 0x",i:%X;  
+i=__readMemory32(0x1C,"Register");   __message "R07 0x",i:%X;  
+i=__readMemory32(0x20,"Register");   __message "R08 0x",i:%X;  
+i=__readMemory32(0x24,"Register");   __message "R09 0x",i:%X;  
+i=__readMemory32(0x28,"Register");   __message "R10 0x",i:%X;  
+i=__readMemory32(0x2C,"Register");   __message "R11 0x",i:%X;  
+i=__readMemory32(0x30,"Register");   __message "R12 0x",i:%X;  
+i=__readMemory32(0x34,"Register");   __message "R13 0x",i:%X;  
+i=__readMemory32(0x38,"Register");   __message "R14 0x",i:%X;  
+i=__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",i:%X;  
+i=__readMemory32(0x40,"Register");   __message "R14 SVC 0x",i:%X;  
+i=__readMemory32(0x44,"Register");   __message "R13 ABT 0x",i:%X;  
+i=__readMemory32(0x48,"Register");   __message "R14 ABT 0x",i:%X;  
+i=__readMemory32(0x4C,"Register");   __message "R13 UND 0x",i:%X;  
+i=__readMemory32(0x50,"Register");   __message "R14 UND 0x",i:%X;  
+i=__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",i:%X;  
+i=__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",i:%X;  
+i=__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",i:%X;  
+i=__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",i:%X;  
+i=__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",i:%X;  
+i=__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",i:%X;  
+i=__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",i:%X;  
+i=__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",i:%X;  
+i=__readMemory32(0x74,"Register");   __message "R14 FIQ0x",i:%X; 
+i=__readMemory32(0x98,"Register");   __message "CPSR     ",i:%X; 
+i=__readMemory32(0x94,"Register");   __message "SPSR     ",i:%X; 
+i=__readMemory32(0x9C,"Register");   __message "SPSR ABT ",i:%X; 
+i=__readMemory32(0xA0,"Register");   __message "SPSR ABT ",i:%X; 
+i=__readMemory32(0xA4,"Register");   __message "SPSR UND ",i:%X; 
+i=__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",i:%X; 
+i=__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",i:%X; 
+
+i=__readMemory32(0xB4,"Register");   __message "PC 0x",i:%X;  
+
+}
+

Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac

@@ -0,0 +1,211 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: SAM7_RAM.mac
+//
+//  User setup file for CSPY debugger to simulate interrupt
+//  driven Fibonacchi data input. 
+//  1.1 16/Jun/04 JPP    : Creation
+//  1.2 27/Aug/04 JPP    : PLL setting
+//
+//  $Revision: 1.3 $
+//
+// ---------------------------------------------------------
+
+__var i;
+__var pt;
+
+execUserPreload()
+{
+//*  
+     PllSetting();
+//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
+     CheckNoRemap();
+//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+    i=__readMemory32(0xFFFFF240,"Memory");
+    __message " ---------------------------------------- Chip ID   0x",i:%X;  
+    i=__readMemory32(0xFFFFF244,"Memory");
+    __message " ---------------------------------------- Extention 0x",i:%X;  
+    i=__readMemory32(0xFFFFFF6C,"Memory");
+    __message " ---------------------------------------- Flash Version 0x",i:%X;  
+//* Get the chip status
+
+//* Init AIC
+   AIC();
+//*  Watchdog Disable
+   Watchdog();
+}
+//-----------------------------------------------------------------------------
+// PllSetting
+//-------------------------------
+// Set PLL
+//-----------------------------------------------------------------------------
+PllSetting()
+{
+// -1- Enabling the Main Oscillator:
+//*#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+//*#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+//*#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) |    //0x0000 0600
+//                          AT91C_CKGR_MOSCEN ));          //0x0000 0001 
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
+
+// -2- Wait
+// -3- Setting PLL and divider:
+// - div by 5 Fin = 3,6864 =(18,432 / 5)
+// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+// for 96 MHz the erroe is 0.16%
+// Field out NOT USED = 0
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms
+// PLLCOUNT 28 = 0.000844 /(1/32768)
+//       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |       //0x0000 0005
+//                         (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
+//                         (AT91C_CKGR_MUL & (25<<16)));   //0x0019 0000 
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
+// -2- Wait
+// -5- Selection of Master Clock and Processor Clock
+// select the PLL clock divided by 2
+//	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |     //0x0000 0003
+//                           AT91C_PMC_PRES_CLK_2 ;      //0x0000 0004
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory");        
+
+   __message "------------------------------- PLL  Enable ----------------------------------------";  
+}
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
+   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+   __message "------------------------------- Watchdog Disable ----------------------------------------";  
+}
+
+CheckNoRemap()
+{
+//* Read the value at 0x0
+    i=__readMemory32(0x00000000,"Memory");
+    i=i+1;
+    __writeMemory32(i,0x00,"Memory");
+    pt=__readMemory32(0x00000000,"Memory");
+    
+ if (i == pt)  
+ {
+   __message "------------------------------- The Remap is done ----------------------------------------";  
+   
+ } else {  
+   __message "------------------------------- The Remap is NOT -----------------------------------------";  
+//*   Toggel RESET The remap
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+ }
+
+}
+
+execUserSetup()
+{
+ ini();
+     __message "-------------------------------Set PC ----------------------------------------";  
+     __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+    __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
+
+    for (i=0;i < 8; i++)
+    {
+      // AT91C_BASE_AIC->AIC_EOICR
+      pt =  __readMemory32(0xFFFFF130,"Memory");
+    
+    }
+   __message "------------------------------- AIC INIT ---------------------------------------------";  
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+}
+
+RG()
+{
+
+i=__readMemory32(0x00,"Register");   __message "R00 0x",i:%X;  
+i=__readMemory32(0x04,"Register");   __message "R01 0x",i:%X;  
+i=__readMemory32(0x08,"Register");   __message "R02 0x",i:%X;  
+i=__readMemory32(0x0C,"Register");   __message "R03 0x",i:%X;  
+i=__readMemory32(0x10,"Register");   __message "R04 0x",i:%X;  
+i=__readMemory32(0x14,"Register");   __message "R05 0x",i:%X;  
+i=__readMemory32(0x18,"Register");   __message "R06 0x",i:%X;  
+i=__readMemory32(0x1C,"Register");   __message "R07 0x",i:%X;  
+i=__readMemory32(0x20,"Register");   __message "R08 0x",i:%X;  
+i=__readMemory32(0x24,"Register");   __message "R09 0x",i:%X;  
+i=__readMemory32(0x28,"Register");   __message "R10 0x",i:%X;  
+i=__readMemory32(0x2C,"Register");   __message "R11 0x",i:%X;  
+i=__readMemory32(0x30,"Register");   __message "R12 0x",i:%X;  
+i=__readMemory32(0x34,"Register");   __message "R13 0x",i:%X;  
+i=__readMemory32(0x38,"Register");   __message "R14 0x",i:%X;  
+i=__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",i:%X;  
+i=__readMemory32(0x40,"Register");   __message "R14 SVC 0x",i:%X;  
+i=__readMemory32(0x44,"Register");   __message "R13 ABT 0x",i:%X;  
+i=__readMemory32(0x48,"Register");   __message "R14 ABT 0x",i:%X;  
+i=__readMemory32(0x4C,"Register");   __message "R13 UND 0x",i:%X;  
+i=__readMemory32(0x50,"Register");   __message "R14 UND 0x",i:%X;  
+i=__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",i:%X;  
+i=__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",i:%X;  
+i=__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",i:%X;  
+i=__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",i:%X;  
+i=__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",i:%X;  
+i=__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",i:%X;  
+i=__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",i:%X;  
+i=__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",i:%X;  
+i=__readMemory32(0x74,"Register");   __message "R14 FIQ0x",i:%X; 
+i=__readMemory32(0x98,"Register");   __message "CPSR     ",i:%X; 
+i=__readMemory32(0x94,"Register");   __message "SPSR     ",i:%X; 
+i=__readMemory32(0x9C,"Register");   __message "SPSR ABT ",i:%X; 
+i=__readMemory32(0xA0,"Register");   __message "SPSR ABT ",i:%X; 
+i=__readMemory32(0xA4,"Register");   __message "SPSR UND ",i:%X; 
+i=__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",i:%X; 
+i=__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",i:%X; 
+
+i=__readMemory32(0xB4,"Register");   __message "PC 0x",i:%X;  
+
+}
+

Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl

@@ -0,0 +1,135 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91SAM7S64_16KRAM.xlc
+//
+//  1.1 16/Jun/04 JPP    : Creation for 4.11A
+//
+//  $Revision: 1.1.1.1 $
+//
+// ---------------------------------------------------------
+
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage:  xlink  -f lnkarm  <your_object_file(s)>
+//                -s <program start label>  <C/C++ runtime library>
+//
+// $Revision: 1.1.1.1 $
+//*************************************************************************
+
+//************************************************
+// Inform the linker about the CPU family used.
+// AT91SAM7S64 Memory mapping
+// No remap
+//  ROMSTART
+//  Start address 0x0000 0000 
+//  Size  64 Kbo  0x0001 0000 
+//  RAMSTART
+//  Start address 0x0020 0000 
+//  Size  16 Kbo  0x0000 4000 
+// Remap done
+//  RAMSTART
+//  Start address 0x0000 0000 
+//  Size  16 Kbo  0x0000 4000 
+//  ROMSTART
+//  Start address 0x0010 0000 
+//  Size  64 Kbo  0x0001 0000 
+
+//************************************************
+-carm
+
+//*************************************************************************
+// Internal Ram segments mapped AFTER REMAP 16 K.
+//*************************************************************************
+// Use these addresses for the .
+-Z(CONST)INTRAMSTART_REMAP=00000000
+-Z(CONST)INTRAMEND_REMAP=00003FFF
+
+//*************************************************************************
+// Read-only segments mapped to Flash 64 K.
+//*************************************************************************
+-DROMSTART=00000000
+-DROMEND=0000FFFF
+//*************************************************************************
+// Read/write segments mapped to RAM.
+//*************************************************************************
+-DRAMSTART=00000000
+-DRAMEND=00003FFF
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes, 
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+-Z(CODE)INTVEC=00-3F
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+//************************************************
+// Data segments.
+//************************************************
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+-D_CSTACK_SIZE=(100*4)
+-D_IRQ_STACK_SIZE=(2*8*4)
+
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+//   "-yn": Suppress DWARF debug output
+//   "-yp": Multiple ELF program sections
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf

Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl

@@ -0,0 +1,136 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91SAM7S64_NoRemap.xlc
+//
+//  1.1 16/Jun/04 JPP    : Creation for 4.11A
+//
+//  $Revision: 1.1.1.1 $
+//
+// ---------------------------------------------------------
+
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage:  xlink  -f lnkarm  <your_object_file(s)>
+//                -s <program start label>  <C/C++ runtime library>
+//
+// $Revision: 1.1.1.1 $
+//*************************************************************************
+
+//************************************************
+// Inform the linker about the CPU family used.
+// AT91SAM7S64 Memory mapping
+// No remap
+//  ROMSTART
+//  Start address 0x0000 0000 
+//  Size  64 Kbo  0x0001 0000 
+//  RAMSTART
+//  Start address 0x0020 0000 
+//  Size  16 Kbo  0x0000 4000 
+// Remap done
+//  RAMSTART
+//  Start address 0x0000 0000 
+//  Size  16 Kbo  0x0000 4000 
+//  ROMSTART
+//  Start address 0x0010 0000 
+//  Size  64 Kbo  0x0001 0000 
+
+//************************************************
+-carm
+
+//*************************************************************************
+// Internal Ram segments mapped AFTER REMAP 16 K.
+//*************************************************************************
+// Use these addresses for the .
+-Z(CONST)INTRAMSTART_REMAP=00200000
+-Z(CONST)INTRAMEND_REMAP=00203FFF
+
+//*************************************************************************
+// Read-only segments mapped to Flash 64 K.
+//*************************************************************************
+-DROMSTART=00000000
+-DROMEND=0000FFFF
+//*************************************************************************
+// Read/write segments mapped to RAM.
+//*************************************************************************
+-DRAMSTART=00200000
+-DRAMEND=002003FFF
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes, 
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+-Z(CODE)INTVEC=00-3F
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+
+//************************************************
+// Data segments.
+//************************************************
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+//-D_CSTACK_SIZE=(100*4)
+//-D_IRQ_STACK_SIZE=(2*8*4)
+
+//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+//   "-yn": Suppress DWARF debug output
+//   "-yp": Multiple ELF program sections
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf

Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd

@@ -0,0 +1,905 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>1</fileVersion>
+  <configuration>
+    <name>Flash Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>13</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state>$PROJ_DIR$\resource\SAM7.mac</state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\ioat91sam7s64.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.10B</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>JLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>4.30A</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FlashLoaders</name>
+          <state>,,,,(default),</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommunication</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>30</state>
+        </option>
+        <option>
+          <name>CCJLinkHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTRSTReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDIUseETM</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>Flash Bin</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>13</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state>$PROJ_DIR$\resource\SAM7.mac</state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\ioat91sam7s64.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.10B</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>JLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>4.30A</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FlashLoaders</name>
+          <state>,,,,(default),</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommunication</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>30</state>
+        </option>
+        <option>
+          <name>CCJLinkHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTRSTReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDIUseETM</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+

Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\rtosdemo.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c

@@ -0,0 +1,246 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. 
+*/
+
+/* Standard includes. */ 
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Location of the COM0 registers. */
+#define serCOM0							( ( AT91PS_USART ) AT91C_BASE_US0 )
+
+/* Interrupt control macros. */
+#define serINTERRUPT_LEVEL				( 5 )
+#define vInterruptOn()					AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY )
+#define vInterruptOff()					AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY )
+
+/* Misc constants. */
+#define serINVALID_QUEUE				( ( xQueueHandle ) 0 )
+#define serHANDLE						( ( xComPortHandle ) 1 )
+#define serNO_BLOCK						( ( portTickType ) 0 )
+#define serNO_TIMEGUARD					( ( unsigned portLONG ) 0 )
+#define serNO_PERIPHERAL_B_SETUP		( ( unsigned portLONG ) 0 )
+
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars; 
+static xQueueHandle xCharsForTx; 
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt entry point written in the assembler file serialISR.s79. */
+extern void vSerialISREntry( void );
+
+/* The interrupt service routine - called from the assembly entry point. */
+__arm void vSerialISR( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See the serial2.h header file.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+xComPortHandle xReturn = serHANDLE;
+extern void ( vUART_ISR )( void );
+
+	/* Create the queues used to hold Rx and Tx characters. */
+	xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+	xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+	/* If the queues were created correctly then setup the serial port 
+	hardware. */
+	if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
+	{
+		portENTER_CRITICAL();
+		{
+			/* Enable the USART clock. */
+   			AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
+
+			AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned portLONG ) AT91C_PA5_RXD0 ) | ( ( unsigned portLONG ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP );
+
+			/* Set the required protocol. */
+			AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD );
+
+			/* Enable Rx and Tx. */
+			serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+
+			/* Enable the Rx interrupts.  The Tx interrupts are not enabled
+			until there are characters to be transmitted. */
+    		AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY );
+
+			/* Enable the interrupts in the AIC. */
+			AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry );
+			AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 );
+		}
+		portEXIT_CRITICAL();
+	}
+	else
+	{
+		xReturn = ( xComPortHandle ) 0;
+	}
+
+	/* This demo file only supports a single port but we have to return 
+	something to comply with the standard demo header file. */
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* The port handle is not required as this driver only supports one port. */
+	( void ) pxPort;
+
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+	/* A couple of parameters that this port does not use. */
+	( void ) usStringLength;
+	( void ) pxPort;
+
+	/* NOTE: This implementation does not handle the queue being full as no
+	block time is used! */
+
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+
+	/* Send each character in the string, one at a time. */
+	pxNext = ( signed portCHAR * ) pcString;
+	while( *pxNext )
+	{
+		xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+		pxNext++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+	/* Place the character in the queue of characters to be transmitted. */
+	if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
+	{
+		return pdFAIL;
+	}
+
+	/* Turn on the Tx interrupt so the ISR will remove the character from the
+	queue and send it.   This does not need to be in a critical section as
+	if the interrupt has already removed the character the next interrupt
+	will simply turn off the Tx interrupt again. */
+	vInterruptOn();
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+	/* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+
+/* Serial port ISR.  This can cause a context switch so is not defined as a
+standard ISR using the __irq keyword.  Instead a wrapper function is defined
+within serialISR.s79 which in turn calls this function.  See the port
+documentation on the FreeRTOS.org website for more information. */
+__arm void vSerialISR( void )
+{
+unsigned portLONG ulStatus;
+signed portCHAR cChar;
+portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;
+
+	/* What caused the interrupt? */
+	ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR;
+
+	if( ulStatus & AT91C_US_TXRDY )
+	{
+		/* The interrupt was caused by the THR becoming empty.  Are there any
+		more characters to transmit? */
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
+		{
+			/* A character was retrieved from the queue so can be sent to the
+			THR now. */
+			serCOM0->US_THR = cChar;
+		}
+		else
+		{
+			/* Queue empty, nothing to send so turn off the Tx interrupt. */
+			vInterruptOff();
+		}		
+	}
+
+	if( ulStatus & AT91C_US_RXRDY )
+	{
+		/* The interrupt was caused by a character being received.  Grab the
+		character from the RHR and place it in the queue or received 
+		characters. */
+		cChar = serCOM0->US_RHR;
+		xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost );
+	}
+
+	/* If a task was woken by either a character being received or a character 
+	being transmitted then we may need to switch to another task. */
+	portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );
+
+	/* End the interrupt in the AIC. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+}
+
+
+
+
+	

Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79

@@ -0,0 +1,24 @@
+		RSEG ICODE:CODE
+		CODE32
+
+		EXTERN vSerialISR
+		PUBLIC vSerialISREntry
+
+; Wrapper for the serial port interrupt service routine.  This can cause a
+; context switch so requires an assembly wrapper.
+
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
+#include "ISR_Support.h"
+
+vSerialISREntry:
+
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	bl	vSerialISR				; Call the ISR routine.
+
+	portRESTORE_CONTEXT			; Restore the context of the current task -
+								; which may be different to the task that
+								; was interrupted.
+
+		END
+

Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt

@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Project>
+  <Desktop>
+    <Static>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
+        <Column0>189</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>
+      </Workspace>
+      <Disassembly>
+        
+        
+        
+      <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
+      <Debug-Log/>
+      <Build/>
+    <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><QWatch><Column0>188</Column0><Column1>171</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Watch><Format><struct_types/><watch_formats/></Format></Watch></Static>
+    <Windows>
+      <Wnd0>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-23416-30482</Identity>
+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
+            <Session>
+              
+            <NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd0>
+      
+      <Wnd2>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-12145-30489</Identity>
+            <TabName>Debug Log</TabName>
+            <Factory>Debug-Log</Factory>
+            <Session/>
+          </Tab>
+          <Tab>
+            <Identity>TabID-22894-30492</Identity>
+            <TabName>Build</TabName>
+            <Factory>Build</Factory>
+            <Session/>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>1</SelectedTab></Wnd2>
+    <Wnd4><Tabs><Tab><Identity>TabID-18780-12821</Identity><TabName>Memory</TabName><Factory>Memory</Factory><Session><SelectionAnchor>2097764</SelectionAnchor><SelectionEnd>2097764</SelectionEnd><UnitsPerGroup>1</UnitsPerGroup><EndianMode>0</EndianMode><DataCovEnabled>0</DataCovEnabled><DataCovShown>0</DataCovShown></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-23506-14575</Identity><TabName>Watch</TabName><Factory>Watch</Factory><Session><Expressions><Expression><Expression>pxCurrentTCB</Expression></Expression><Expression><Expression>ulCriticalNesting</Expression></Expression></Expressions><TabId>0</TabId><Column0>176</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5><Wnd1><Tabs><Tab><Identity>TabID-4859-22480</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1><Wnd3><Tabs><Tab><Identity>TabID-154-22568</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
+    <Editor>
+      
+      
+      
+      
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+
+

Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dni

@@ -0,0 +1,23 @@
+[DisAssemblyWindow]
+NumStates=_ 1
+State 1=_ 1
+[JLinkDriver]
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+WatchCond=_ 0
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+[Log file]
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+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[Disassemble mode]
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+[Breakpoints]
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+[Low Level]
+Pipeline mode=0
+Initialized=0

Demo/ARM7_AT91SAM7S64_IAR/settings/BasicSAM7.wsdt

@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Workspace>
+  <ConfigDictionary>
+    
+  <CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
+  <Desktop>
+    <Static>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
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+      <TerminalIO/>
+      <Profiling/>
+      <Watch>
+        <Format>
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+          <watch_formats/>
+        </Format>
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+      <Debug-Log/>
+      <Disassembly>
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+        
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+    <CodeCoveragePlugin/><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory></Static>
+    <Windows>
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+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
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+              
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+        </Tabs>
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+        <Tabs>
+          <Tab>
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+            <TabName>Build</TabName>
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+          <Tab>
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+            <TabName>Debug Log</TabName>
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+            <Session/>
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+
+

Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt

@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Project>
+  <Desktop>
+    <Static>
+      <Workspace>
+        <ColumnWidths>
+          
+          
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+      <Disassembly>
+        
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+      <Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window></Windows></PreferedWindows></Debug-Log>
+      <Build><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>
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+    <Windows>
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+            <TabName>Workspace</TabName>
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+          </Tab>
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+
+

Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni

@@ -0,0 +1,22 @@
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+[Disassemble mode]
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+[Breakpoints]
+Count=0

Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt

@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Workspace>
+  <ConfigDictionary>
+    
+  <CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
+  <Desktop>
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+        <ColumnWidths>
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+      <CodeCoveragePlugin/>
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+</Workspace>
+
+

Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h

@@ -0,0 +1,78 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <lpc210x.h>
+
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 58982400 )	/* =14.7456MHz xtal multiplied by 4 using the PLL. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 128 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 23 * 1024 ) )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */

Demo/ARM7_LPC2106_GCC/Makefile

@@ -0,0 +1,118 @@
+#	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+#
+#	This file is part of the FreeRTOS.org distribution.
+#
+#	FreeRTOS.org is free software; you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation; either version 2 of the License, or
+#	(at your option) any later version.
+#
+#	FreeRTOS.org is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with FreeRTOS.org; if not, write to the Free Software
+#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#	A special exception to the GPL can be applied should you wish to distribute
+#	a combined work that includes FreeRTOS.org, without being obliged to provide
+#	the source code for any proprietary components.  See the licensing section 
+#	of http://www.FreeRTOS.org for full details of how and when the exception
+#	can be applied.
+#
+#	***************************************************************************
+#	See http://www.FreeRTOS.org for documentation, latest information, license 
+#	and contact details.  Please ensure to read the configuration and relevant 
+#	port sections of the online documentation.
+#	***************************************************************************
+
+# Changes from V2.4.2
+#
+#	+ Replaced source/portable/gcc/arm7/portheap.c with source/portable/memmang/heap_2.c.
+
+CC=arm-elf-gcc
+OBJCOPY=arm-elf-objcopy
+ARCH=arm-elf-ar
+CRT0=boot.s
+WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \
+		-Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused
+
+#
+# CFLAGS common to both the THUMB and ARM mode builds
+#
+CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \
+		-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
+		 $(OPTIM) -fomit-frame-pointer
+
+ifeq ($(USE_THUMB_MODE),YES)
+	CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
+	THUMB_FLAGS=-mthumb
+endif
+
+
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
+
+RTOS_SOURCE_DIR=../../Source
+DEMO_SOURCE_DIR=../Common/Minimal
+#
+# Source files that can be built to THUMB mode.
+#
+THUMB_SRC = \
+main.c \
+serial/serial.c \
+ParTest/ParTest.c \
+$(DEMO_SOURCE_DIR)/integer.c \
+$(DEMO_SOURCE_DIR)/flash.c \
+$(DEMO_SOURCE_DIR)/PollQ.c \
+$(DEMO_SOURCE_DIR)/comtest.c \
+$(DEMO_SOURCE_DIR)/flop.c \
+$(DEMO_SOURCE_DIR)/semtest.c \
+$(DEMO_SOURCE_DIR)/dynamic.c \
+$(DEMO_SOURCE_DIR)/BlockQ.c \
+$(RTOS_SOURCE_DIR)/tasks.c \
+$(RTOS_SOURCE_DIR)/queue.c \
+$(RTOS_SOURCE_DIR)/list.c \
+$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \
+$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c
+
+#
+# Source files that must be built to ARM mode.
+#
+ARM_SRC = \
+$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \
+serial/serialISR.c
+
+#
+# Define all object files.
+#
+ARM_OBJ = $(ARM_SRC:.c=.o)
+THUMB_OBJ = $(THUMB_SRC:.c=.o)
+
+rtosdemo.hex : rtosdemo.elf
+	$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
+
+rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
+	$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
+
+$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
+	$(CC) -c $(CFLAGS) $< -o $@
+
+clean :
+	touch Makefile
+
+
+
+
+
+
+
+
+
+	
+
+

Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c

@@ -0,0 +1,106 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+	Changes from V2.5.2
+		
+	+ All LED's are turned off to start.
+*/
+
+
+#include "FreeRTOS.h"
+#include "partest.h"
+
+#define partstFIRST_IO			( ( unsigned portLONG ) 0x400 )
+#define partstNUM_LEDS			( 4 )
+#define partstALL_OUTPUTS_OFF	( ( unsigned portLONG ) 0xffffffff )
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines.
+ *-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* This is performed from main() as the io bits are shared with other setup
+	functions. */
+
+	/* Turn all outputs off. */
+	GPIO_IOSET = partstALL_OUTPUTS_OFF;
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+unsigned portLONG ulLED = partstFIRST_IO;
+
+	if( uxLED < partstNUM_LEDS )
+	{
+		/* Rotate to the wanted bit of port 0.  Only P10 to P13 have an LED
+		attached. */
+		ulLED <<= ( unsigned portLONG ) uxLED;
+
+		/* Set of clear the output. */
+		if( xValue )
+		{
+			GPIO_IOCLR = ulLED;
+		}
+		else
+		{
+			GPIO_IOSET = ulLED;			
+		}
+	}	
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;
+
+	if( uxLED < partstNUM_LEDS )
+	{
+		/* Rotate to the wanted bit of port 0.  Only P10 to P13 have an LED
+		attached. */
+		ulLED <<= ( unsigned portLONG ) uxLED;
+
+		/* If this bit is already set, clear it, and visa versa. */
+		ulCurrentState = GPIO0_IOPIN;
+		if( ulCurrentState & ulLED )
+		{
+			GPIO_IOCLR = ulLED;
+		}
+		else
+		{
+			GPIO_IOSET = ulLED;			
+		}
+	}	
+}
+

Demo/ARM7_LPC2106_GCC/boot.s

@@ -0,0 +1,157 @@
+	/* Sample initialization file */
+
+	.extern main
+	.extern exit
+
+	.text
+	.code 32
+
+
+	.align  0
+
+	.extern __bss_beg__
+	.extern __bss_end__
+	.extern __stack_end__
+	.extern __data_beg__
+	.extern __data_end__
+	.extern __data+beg_src__
+
+	.global start
+	.global endless_loop
+
+	/* Stack Sizes */
+    .set  UND_STACK_SIZE, 0x00000004
+    .set  ABT_STACK_SIZE, 0x00000004
+    .set  FIQ_STACK_SIZE, 0x00000004
+    .set  IRQ_STACK_SIZE, 0X00000400
+    .set  SVC_STACK_SIZE, 0x00000400
+
+	/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+    .set  MODE_USR, 0x10            /* User Mode */
+    .set  MODE_FIQ, 0x11            /* FIQ Mode */
+    .set  MODE_IRQ, 0x12            /* IRQ Mode */
+    .set  MODE_SVC, 0x13            /* Supervisor Mode */
+    .set  MODE_ABT, 0x17            /* Abort Mode */
+    .set  MODE_UND, 0x1B            /* Undefined Mode */
+    .set  MODE_SYS, 0x1F            /* System Mode */
+
+    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
+    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
+
+
+start:
+_start:
+_mainCRTStartup:
+
+	/* Setup a stack for each mode - note that this only sets up a usable stack
+	for system/user, SWI and IRQ modes.   Also each mode is setup with
+	interrupts initially disabled. */
+    ldr   r0, .LC6
+    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode
+    mov   sp, r0
+    sub   r0, r0, #UND_STACK_SIZE
+    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
+    mov   sp, r0
+    sub   r0, r0, #ABT_STACK_SIZE
+    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #FIQ_STACK_SIZE
+    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #IRQ_STACK_SIZE
+    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
+    mov   sp, r0
+    sub   r0, r0, #SVC_STACK_SIZE
+    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
+    mov   sp, r0
+
+	/* We want to start in supervisor mode.  Operation will switch to system
+	mode when the first task starts. */
+	msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
+
+	/* Clear BSS. */
+
+	mov     a2, #0			/* Fill value */
+	mov		fp, a2			/* Null frame pointer */
+	mov		r7, a2			/* Null frame pointer for Thumb */
+
+	ldr		r1, .LC1		/* Start of memory block */
+	ldr		r3, .LC2		/* End of memory block */
+	subs	r3, r3, r1      /* Length of block */
+	beq		.end_clear_loop
+	mov		r2, #0
+
+.clear_loop:
+	strb	r2, [r1], #1
+	subs	r3, r3, #1
+	bgt		.clear_loop
+
+.end_clear_loop:
+
+	/* Initialise data. */
+
+	ldr		r1, .LC3		/* Start of memory block */
+	ldr		r2, .LC4		/* End of memory block */
+	ldr		r3, .LC5
+	subs	r3, r3, r1		/* Length of block */
+	beq		.end_set_loop
+
+.set_loop:
+	ldrb	r4, [r2], #1
+	strb	r4, [r1], #1
+	subs	r3, r3, #1
+	bgt		.set_loop
+
+.end_set_loop:
+
+	mov		r0, #0          /* no arguments  */
+	mov		r1, #0          /* no argv either */
+
+	bl		main
+
+endless_loop:
+	b               endless_loop
+
+
+	.align 0
+
+	.LC1:
+	.word   __bss_beg__
+	.LC2:
+	.word   __bss_end__
+	.LC3:
+	.word   __data_beg__
+	.LC4:
+	.word   __data_beg_src__
+	.LC5:
+	.word   __data_end__
+	.LC6:
+	.word   __stack_end__
+
+
+	/* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
+	a null loop. */
+
+.section .startup,"ax"
+         .code 32
+         .align 0
+
+	b     _start						/* reset - _start			*/
+	ldr   pc, _undf						/* undefined - _undf		*/
+	ldr   pc, _swi						/* SWI - _swi				*/
+	ldr   pc, _pabt						/* program abort - _pabt	*/
+	ldr   pc, _dabt						/* data abort - _dabt		*/
+	nop									/* reserved					*/
+	ldr   pc, [pc,#-0xFF0]				/* IRQ - read the VIC		*/
+	ldr   pc, _fiq						/* FIQ - _fiq				*/
+
+_undf:  .word __undf                    /* undefined				*/
+_swi:   .word vPortYieldProcessor       /* SWI						*/
+_pabt:  .word __pabt                    /* program abort			*/
+_dabt:  .word __dabt                    /* data abort				*/
+_fiq:   .word __fiq                     /* FIQ						*/
+
+__undf: b     .                         /* undefined				*/
+__pabt: b     .                         /* program abort			*/
+__dabt: b     .                         /* data abort				*/
+__fiq:  b     .                         /* FIQ						*/

Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld

@@ -0,0 +1,49 @@
+MEMORY 
+{
+	flash	: ORIGIN = 0, LENGTH = 120K
+	ram		: ORIGIN = 0x40000000, LENGTH = 64K
+}
+
+__stack_end__ = 0x40000000 + 64K - 4;
+
+SECTIONS 
+{
+	. = 0;
+	startup : { *(.startup)} >ram
+
+	prog : 
+	{
+		*(.text)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+	} >ram
+
+	__end_of_text__ = .;
+
+	.data : 
+	{
+		__data_beg__ = .;
+		__data_beg_src__ = __end_of_text__;
+		*(.data)
+		__data_end__ = .;
+	} >ram
+
+	.bss : 
+	{
+		__bss_beg__ = .;
+		*(.bss)
+	} >ram
+
+	/* Align here to ensure that the .bss section occupies space up to
+	_end.  Align after .bss to ensure correct alignment even if the
+	.bss section disappears because there are no input sections.  */
+	. = ALIGN(32 / 8);
+}
+	. = ALIGN(32 / 8);
+	_end = .;
+	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+	PROVIDE (end = .);
+
+

Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld

@@ -0,0 +1,49 @@
+MEMORY 
+{
+	flash	: ORIGIN = 0, LENGTH = 120K
+	ram		: ORIGIN = 0x40000000, LENGTH = 64K
+}
+
+__stack_end__ = 0x40000000 + 64K - 4;
+
+SECTIONS 
+{
+	. = 0;
+	startup : { *(.startup)} >flash
+
+	prog : 
+	{
+		*(.text)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+	} >flash
+
+	__end_of_text__ = .;
+
+	.data : 
+	{
+		__data_beg__ = .;
+		__data_beg_src__ = __end_of_text__;
+		*(.data)
+		__data_end__ = .;
+	} >ram AT>flash
+
+	.bss : 
+	{
+		__bss_beg__ = .;
+		*(.bss)
+	} >ram
+
+	/* Align here to ensure that the .bss section occupies space up to
+	_end.  Align after .bss to ensure correct alignment even if the
+	.bss section disappears because there are no input sections.  */
+	. = ALIGN(32 / 8);
+}
+	. = ALIGN(32 / 8);
+	_end = .;
+	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+	PROVIDE (end = .);
+
+

Demo/ARM7_LPC2106_GCC/lpc210x.h

@@ -0,0 +1,321 @@
+#ifndef lpc210x_h
+#define lpc210x_h
+/*******************************************************************************
+lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106
+
+           
+THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, 
+EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY 
+WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY 
+PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS 
+OF OTHERS.
+           
+This file may be freely used for commercial and non-commercial applications, 
+including being redistributed with any tools.
+
+If you find a problem with the file, please report it so that it can be fixed.
+
+Created by Sten Larsson (sten_larsson at yahoo com)
+
+Edited by Richard Barry.
+*******************************************************************************/
+
+#define REG8  (volatile unsigned char*)
+#define REG16 (volatile unsigned short*)
+#define REG32 (volatile unsigned int*)
+
+
+/*##############################################################################
+## MISC
+##############################################################################*/
+
+        /* Constants for data to put in IRQ/FIQ Exception Vectors */
+#define VECTDATA_IRQ  0xE51FFFF0  /* LDR PC,[PC,#-0xFF0] */
+#define VECTDATA_FIQ  /* __TODO */
+
+
+/*##############################################################################
+## VECTORED INTERRUPT CONTROLLER
+##############################################################################*/
+
+#define VICIRQStatus    (*(REG32 (0xFFFFF000)))
+#define VICFIQStatus    (*(REG32 (0xFFFFF004)))
+#define VICRawIntr      (*(REG32 (0xFFFFF008)))
+#define VICIntSelect    (*(REG32 (0xFFFFF00C)))
+#define VICIntEnable    (*(REG32 (0xFFFFF010)))
+#define VICIntEnClear   (*(REG32 (0xFFFFF014)))
+#define VICSoftInt      (*(REG32 (0xFFFFF018)))
+#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
+#define VICProtection   (*(REG32 (0xFFFFF020)))
+#define VICVectAddr     (*(REG32 (0xFFFFF030)))
+#define VICDefVectAddr  (*(REG32 (0xFFFFF034)))
+
+#define VICVectAddr0    (*(REG32 (0xFFFFF100)))
+#define VICVectAddr1    (*(REG32 (0xFFFFF104)))
+#define VICVectAddr2    (*(REG32 (0xFFFFF108)))
+#define VICVectAddr3    (*(REG32 (0xFFFFF10C)))
+#define VICVectAddr4    (*(REG32 (0xFFFFF110)))
+#define VICVectAddr5    (*(REG32 (0xFFFFF114)))
+#define VICVectAddr6    (*(REG32 (0xFFFFF118)))
+#define VICVectAddr7    (*(REG32 (0xFFFFF11C)))
+#define VICVectAddr8    (*(REG32 (0xFFFFF120)))
+#define VICVectAddr9    (*(REG32 (0xFFFFF124)))
+#define VICVectAddr10   (*(REG32 (0xFFFFF128)))
+#define VICVectAddr11   (*(REG32 (0xFFFFF12C)))
+#define VICVectAddr12   (*(REG32 (0xFFFFF130)))
+#define VICVectAddr13   (*(REG32 (0xFFFFF134)))
+#define VICVectAddr14   (*(REG32 (0xFFFFF138)))
+#define VICVectAddr15   (*(REG32 (0xFFFFF13C)))
+
+#define VICVectCntl0    (*(REG32 (0xFFFFF200)))
+#define VICVectCntl1    (*(REG32 (0xFFFFF204)))
+#define VICVectCntl2    (*(REG32 (0xFFFFF208)))
+#define VICVectCntl3    (*(REG32 (0xFFFFF20C)))
+#define VICVectCntl4    (*(REG32 (0xFFFFF210)))
+#define VICVectCntl5    (*(REG32 (0xFFFFF214)))
+#define VICVectCntl6    (*(REG32 (0xFFFFF218)))
+#define VICVectCntl7    (*(REG32 (0xFFFFF21C)))
+#define VICVectCntl8    (*(REG32 (0xFFFFF220)))
+#define VICVectCntl9    (*(REG32 (0xFFFFF224)))
+#define VICVectCntl10   (*(REG32 (0xFFFFF228)))
+#define VICVectCntl11   (*(REG32 (0xFFFFF22C)))
+#define VICVectCntl12   (*(REG32 (0xFFFFF230)))
+#define VICVectCntl13   (*(REG32 (0xFFFFF234)))
+#define VICVectCntl14   (*(REG32 (0xFFFFF238)))
+#define VICVectCntl15   (*(REG32 (0xFFFFF23C)))
+
+#define VICITCR         (*(REG32 (0xFFFFF300)))
+#define VICITIP1        (*(REG32 (0xFFFFF304)))
+#define VICITIP2        (*(REG32 (0xFFFFF308)))
+#define VICITOP1        (*(REG32 (0xFFFFF30C)))
+#define VICITOP2        (*(REG32 (0xFFFFF310)))
+#define VICPeriphID0    (*(REG32 (0xFFFFFFE0)))
+#define VICPeriphID1    (*(REG32 (0xFFFFFFE4)))
+#define VICPeriphID2    (*(REG32 (0xFFFFFFE8)))
+#define VICPeriphID3    (*(REG32 (0xFFFFFFEC)))
+
+#define VICIntEnClr     VICIntEnClear
+#define VICSoftIntClr   VICSoftIntClear
+
+
+/*##############################################################################
+## PCB - Pin Connect Block
+##############################################################################*/
+
+#define PCB_PINSEL0     (*(REG32 (0xE002C000)))
+#define PCB_PINSEL1     (*(REG32 (0xE002C004)))
+
+
+/*##############################################################################
+## GPIO - General Purpose I/O
+##############################################################################*/
+
+#define GPIO_IOPIN      (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
+#define GPIO_IOSET      (*(REG32 (0xE0028004)))
+#define GPIO_IODIR      (*(REG32 (0xE0028008)))
+#define GPIO_IOCLR      (*(REG32 (0xE002800C)))
+
+#define GPIO0_IOPIN     (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
+#define GPIO0_IOSET     (*(REG32 (0xE0028004)))
+#define GPIO0_IODIR     (*(REG32 (0xE0028008)))
+#define GPIO0_IOCLR     (*(REG32 (0xE002800C)))
+
+
+/*##############################################################################
+## UART0 / UART1
+##############################################################################*/
+
+/* ---- UART 0 --------------------------------------------- */
+#define UART0_RBR       (*(REG32 (0xE000C000)))
+#define UART0_THR       (*(REG32 (0xE000C000)))
+#define UART0_IER       (*(REG32 (0xE000C004)))
+#define UART0_IIR       (*(REG32 (0xE000C008)))
+#define UART0_FCR       (*(REG32 (0xE000C008)))
+#define UART0_LCR       (*(REG32 (0xE000C00C)))
+#define UART0_LSR       (*(REG32 (0xE000C014)))
+#define UART0_SCR       (*(REG32 (0xE000C01C)))
+#define UART0_DLL       (*(REG32 (0xE000C000)))
+#define UART0_DLM       (*(REG32 (0xE000C004)))
+
+/* ---- UART 1 --------------------------------------------- */
+#define UART1_RBR       (*(REG32 (0xE0010000)))
+#define UART1_THR       (*(REG32 (0xE0010000)))
+#define UART1_IER       (*(REG32 (0xE0010004)))
+#define UART1_IIR       (*(REG32 (0xE0010008)))
+#define UART1_FCR       (*(REG32 (0xE0010008)))
+#define UART1_LCR       (*(REG32 (0xE001000C)))
+#define UART1_LSR       (*(REG32 (0xE0010014)))
+#define UART1_SCR       (*(REG32 (0xE001001C)))
+#define UART1_DLL       (*(REG32 (0xE0010000)))
+#define UART1_DLM       (*(REG32 (0xE0010004)))
+#define UART1_MCR       (*(REG32 (0xE0010010)))
+#define UART1_MSR       (*(REG32 (0xE0010018)))
+
+
+/*##############################################################################
+## I2C
+##############################################################################*/
+
+#define I2C_I2CONSET    (*(REG32 (0xE001C000)))
+#define I2C_I2STAT      (*(REG32 (0xE001C004)))
+#define I2C_I2DAT       (*(REG32 (0xE001C008)))
+#define I2C_I2ADR       (*(REG32 (0xE001C00C)))
+#define I2C_I2SCLH      (*(REG32 (0xE001C010)))
+#define I2C_I2SCLL      (*(REG32 (0xE001C014)))
+#define I2C_I2CONCLR    (*(REG32 (0xE001C018)))
+
+
+/*##############################################################################
+## SPI - Serial Peripheral Interface
+##############################################################################*/
+
+#define SPI_SPCR        (*(REG32 (0xE0020000)))
+#define SPI_SPSR        (*(REG32 (0xE0020004)))
+#define SPI_SPDR        (*(REG32 (0xE0020008)))
+#define SPI_SPCCR       (*(REG32 (0xE002000C)))
+#define SPI_SPTCR       (*(REG32 (0xE0020010)))
+#define SPI_SPTSR       (*(REG32 (0xE0020014)))
+#define SPI_SPTOR       (*(REG32 (0xE0020018)))
+#define SPI_SPINT       (*(REG32 (0xE002001C)))
+
+
+/*##############################################################################
+## Timer 0 and Timer 1
+##############################################################################*/
+
+/* ---- Timer 0 -------------------------------------------- */
+#define T0_IR           (*(REG32 (0xE0004000)))
+#define T0_TCR          (*(REG32 (0xE0004004)))
+#define T0_TC           (*(REG32 (0xE0004008)))
+#define T0_PR           (*(REG32 (0xE000400C)))
+#define T0_PC           (*(REG32 (0xE0004010)))
+#define T0_MCR          (*(REG32 (0xE0004014)))
+#define T0_MR0          (*(REG32 (0xE0004018)))
+#define T0_MR1          (*(REG32 (0xE000401C)))
+#define T0_MR2          (*(REG32 (0xE0004020)))
+#define T0_MR3          (*(REG32 (0xE0004024)))
+#define T0_CCR          (*(REG32 (0xE0004028)))
+#define T0_CR0          (*(REG32 (0xE000402C)))
+#define T0_CR1          (*(REG32 (0xE0004030)))
+#define T0_CR2          (*(REG32 (0xE0004034)))
+#define T0_CR3          (*(REG32 (0xE0004038)))
+#define T0_EMR          (*(REG32 (0xE000403C)))
+
+/* ---- Timer 1 -------------------------------------------- */
+#define T1_IR           (*(REG32 (0xE0008000)))
+#define T1_TCR          (*(REG32 (0xE0008004)))
+#define T1_TC           (*(REG32 (0xE0008008)))
+#define T1_PR           (*(REG32 (0xE000800C)))
+#define T1_PC           (*(REG32 (0xE0008010)))
+#define T1_MCR          (*(REG32 (0xE0008014)))
+#define T1_MR0          (*(REG32 (0xE0008018)))
+#define T1_MR1          (*(REG32 (0xE000801C)))
+#define T1_MR2          (*(REG32 (0xE0008020)))
+#define T1_MR3          (*(REG32 (0xE0008024)))
+#define T1_CCR          (*(REG32 (0xE0008028)))
+#define T1_CR0          (*(REG32 (0xE000802C)))
+#define T1_CR1          (*(REG32 (0xE0008030)))
+#define T1_CR2          (*(REG32 (0xE0008034)))
+#define T1_CR3          (*(REG32 (0xE0008038)))
+#define T1_EMR          (*(REG32 (0xE000803C)))
+
+
+/*##############################################################################
+## PWM
+##############################################################################*/
+
+#define PWM_IR          (*(REG32 (0xE0014000)))
+#define PWM_TCR         (*(REG32 (0xE0014004)))
+#define PWM_TC          (*(REG32 (0xE0014008)))
+#define PWM_PR          (*(REG32 (0xE001400C)))
+#define PWM_PC          (*(REG32 (0xE0014010)))
+#define PWM_MCR         (*(REG32 (0xE0014014)))
+#define PWM_MR0         (*(REG32 (0xE0014018)))
+#define PWM_MR1         (*(REG32 (0xE001401C)))
+#define PWM_MR2         (*(REG32 (0xE0014020)))
+#define PWM_MR3         (*(REG32 (0xE0014024)))
+#define PWM_MR4         (*(REG32 (0xE0014040)))
+#define PWM_MR5         (*(REG32 (0xE0014044)))
+#define PWM_MR6         (*(REG32 (0xE0014048)))
+#define PWM_EMR         (*(REG32 (0xE001403C)))
+#define PWM_PCR         (*(REG32 (0xE001404C)))
+#define PWM_LER         (*(REG32 (0xE0014050)))
+#define PWM_CCR         (*(REG32 (0xE0014028)))
+#define PWM_CR0         (*(REG32 (0xE001402C)))
+#define PWM_CR1         (*(REG32 (0xE0014030)))
+#define PWM_CR2         (*(REG32 (0xE0014034)))
+#define PWM_CR3         (*(REG32 (0xE0014038)))
+
+/*##############################################################################
+## RTC
+##############################################################################*/
+
+/* ---- RTC: Miscellaneous Register Group ------------------ */
+#define RTC_ILR         (*(REG32 (0xE0024000)))
+#define RTC_CTC         (*(REG32 (0xE0024004)))
+#define RTC_CCR         (*(REG32 (0xE0024008)))  
+#define RTC_CIIR        (*(REG32 (0xE002400C)))
+#define RTC_AMR         (*(REG32 (0xE0024010)))
+#define RTC_CTIME0      (*(REG32 (0xE0024014)))
+#define RTC_CTIME1      (*(REG32 (0xE0024018)))
+#define RTC_CTIME2      (*(REG32 (0xE002401C)))
+
+/* ---- RTC: Timer Control Group --------------------------- */
+#define RTC_SEC         (*(REG32 (0xE0024020)))
+#define RTC_MIN         (*(REG32 (0xE0024024)))
+#define RTC_HOUR        (*(REG32 (0xE0024028)))
+#define RTC_DOM         (*(REG32 (0xE002402C)))
+#define RTC_DOW         (*(REG32 (0xE0024030)))
+#define RTC_DOY         (*(REG32 (0xE0024034)))
+#define RTC_MONTH       (*(REG32 (0xE0024038)))
+#define RTC_YEAR        (*(REG32 (0xE002403C)))
+
+/* ---- RTC: Alarm Control Group --------------------------- */
+#define RTC_ALSEC       (*(REG32 (0xE0024060)))
+#define RTC_ALMIN       (*(REG32 (0xE0024064)))
+#define RTC_ALHOUR      (*(REG32 (0xE0024068)))
+#define RTC_ALDOM       (*(REG32 (0xE002406C)))
+#define RTC_ALDOW       (*(REG32 (0xE0024070)))
+#define RTC_ALDOY       (*(REG32 (0xE0024074)))
+#define RTC_ALMON       (*(REG32 (0xE0024078)))
+#define RTC_ALYEAR      (*(REG32 (0xE002407C)))
+
+/* ---- RTC: Reference Clock Divider Group ----------------- */
+#define RTC_PREINT      (*(REG32 (0xE0024080)))
+#define RTC_PREFRAC     (*(REG32 (0xE0024084)))
+
+
+/*##############################################################################
+## WD - Watchdog
+##############################################################################*/
+
+#define WD_WDMOD        (*(REG32 (0xE0000000)))
+#define WD_WDTC         (*(REG32 (0xE0000004)))
+#define WD_WDFEED       (*(REG32 (0xE0000008)))
+#define WD_WDTV         (*(REG32 (0xE000000C)))
+
+
+/*##############################################################################
+## System Control Block
+##############################################################################*/
+
+#define SCB_EXTINT      (*(REG32 (0xE01FC140)))
+#define SCB_EXTWAKE     (*(REG32 (0xE01FC144)))
+#define SCB_MEMMAP      (*(REG32 (0xE01FC040)))
+#define SCB_PLLCON      (*(REG32 (0xE01FC080)))
+#define SCB_PLLCFG      (*(REG32 (0xE01FC084)))
+#define SCB_PLLSTAT     (*(REG32 (0xE01FC088)))
+#define SCB_PLLFEED     (*(REG32 (0xE01FC08C)))
+#define SCB_PCON        (*(REG32 (0xE01FC0C0)))
+#define SCB_PCONP       (*(REG32 (0xE01FC0C4)))
+#define SCB_VPBDIV      (*(REG32 (0xE01FC100)))
+
+/*##############################################################################
+## Memory Accelerator Module (MAM)
+##############################################################################*/
+
+#define MAM_TIM			(*(REG32 (0xE01FC004)))
+#define MAM_CR			(*(REG32 (0xE01FC000)))
+
+#endif /* lpc210x_h */
+

Demo/ARM7_LPC2106_GCC/lpc221x.h

@@ -0,0 +1 @@
+#include "lpc2114.h"

Demo/ARM7_LPC2106_GCC/main.c

@@ -0,0 +1,474 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ * 
+ * Main.c also creates a task called "Check".  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.
+ * Each task (other than the "flash" tasks) maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * check task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles the onboard LED.  Should any task contain an error at any time 
+ * the LED toggle rate will change from 3 seconds to 500ms.
+ *
+ * To check the operation of the memory allocator the check task also 
+ * dynamically creates a task before delaying, and deletes it again when it 
+ * wakes.  If memory cannot be allocated for the new task the call to xTaskCreate
+ * will fail and an error is signalled.  The dynamically created task itself
+ * allocates and frees memory just to give the allocator a bit more exercise.
+ *
+ */
+
+/* 
+	Changes from V2.4.2
+
+	+ The vErrorChecks() task now dynamically creates then deletes a task each
+	  cycle.  This tests the operation of the memory allocator.
+
+	Changes from V2.5.2
+		
+	+ vParTestInitialise() is called during initialisation to ensure all the 
+	  LED's start off.
+*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "integer.h"
+#include "PollQ.h"
+#include "comtest2.h"
+#include "semtest.h"
+#include "flop.h"
+#include "dynamic.h"
+#include "BlockQ.h"
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup I/O. */
+#define mainTX_ENABLE	( ( unsigned portLONG ) 0x0001 )
+#define mainRX_ENABLE	( ( unsigned portLONG ) 0x0004 )
+#define mainP0_14		( ( unsigned portLONG ) 0x4000 )
+#define mainJTAG_PORT	( ( unsigned portLONG ) 0x3E0000UL )
+
+/* Constants to setup the PLL. */
+#define mainPLL_MUL_4		( ( unsigned portCHAR ) 0x0003 )
+#define mainPLL_DIV_1		( ( unsigned portCHAR ) 0x0000 )
+#define mainPLL_ENABLE		( ( unsigned portCHAR ) 0x0001 )
+#define mainPLL_CONNECT		( ( unsigned portCHAR ) 0x0003 )
+#define mainPLL_FEED_BYTE1	( ( unsigned portCHAR ) 0xaa )
+#define mainPLL_FEED_BYTE2	( ( unsigned portCHAR ) 0x55 )
+#define mainPLL_LOCK		( ( unsigned portLONG ) 0x0400 )
+
+/* Constants to setup the MAM. */
+#define mainMAM_TIM_3		( ( unsigned portCHAR ) 0x03 )
+#define mainMAM_MODE_FULL	( ( unsigned portCHAR ) 0x02 )
+
+/* Constants to setup the peripheral bus. */
+#define mainBUS_CLK_FULL	( ( unsigned portCHAR ) 0x01 )
+
+/* Constants for the ComTest tasks. */
+#define mainCOM_TEST_BAUD_RATE	( ( unsigned portLONG ) 115200 )
+#define mainCOM_TEST_LED		( 3 )
+
+/* Priorities for the demo application tasks. */
+#define mainLED_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 2 )
+
+/* The rate at which the on board LED will toggle when there is/is not an 
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+#define mainON_BOARD_LED_BIT		( ( unsigned portLONG ) 0x80 )
+
+/* Constants used by the vMemCheckTask() task. */
+#define mainCOUNT_INITIAL_VALUE		( ( unsigned portLONG ) 0 )
+#define mainNO_TASK					( 0 )
+
+/* The size of the memory blocks allocated by the vMemCheckTask() task. */
+#define mainMEM_CHECK_SIZE_1		( ( size_t ) 51 )
+#define mainMEM_CHECK_SIZE_2		( ( size_t ) 52 )
+#define mainMEM_CHECK_SIZE_3		( ( size_t ) 151 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The Olimex demo board has a single built in LED.  This function simply
+ * toggles its state. 
+ */
+void prvToggleOnBoardLED( void );
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );
+
+/*
+ * The task that executes at the highest priority and calls 
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Dynamically created and deleted during each cycle of the vErrorChecks()
+ * task.  This is done to check the operation of the memory allocator.
+ * See the top of vErrorChecks for more details.
+ */
+static void vMemCheckTask( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Olimex demo board.  This includes
+ * setup for the I/O, system clock, and access timings.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler. 
+ */
+int main( void )
+{
+	/* Setup the hardware for use with the Olimex demo board. */
+	prvSetupHardware();
+
+	/* Start the demo/test application tasks. */
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartMathTasks( tskIDLE_PRIORITY );
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartDynamicPriorityTasks();
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */
+	xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Now all the tasks have been started - start the scheduler.
+
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here. */
+	vTaskStartScheduler();
+
+	/* Should never reach here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+unsigned portLONG ulMemCheckTaskRunningCount;
+xTaskHandle xCreatedTask;
+
+	/* The parameters are not used in this function. */
+	( void ) pvParameters;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the on board LED flash rate will increase. 
+	
+	In addition to the standard tests the memory allocator is tested through
+	the dynamic creation and deletion of a task each cycle.  Each time the 
+	task is created memory must be allocated for its stack.  When the task is
+	deleted this memory is returned to the heap.  If the task cannot be created 
+	then it is likely that the memory allocation failed. */
+
+	for( ;; )
+	{
+		/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a 
+		parameter. */
+		ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
+		xCreatedTask = mainNO_TASK;
+		if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
+		{
+			/* Could not create the task - we have probably run out of heap. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		/* Delay until it is time to execute again. */
+		vTaskDelay( xDelayPeriod );
+	
+		/* Delete the dynamically created task. */
+		if( xCreatedTask != mainNO_TASK )
+		{
+			vTaskDelete( xCreatedTask );
+		}
+
+		/* Check all the standard demo application tasks are executing without 
+		error.  ulMemCheckTaskRunningCount is checked to ensure it was
+		modified by the task just deleted. */
+		if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		prvToggleOnBoardLED();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	#ifdef RUN_FROM_RAM
+		/* Remap the interrupt vectors to RAM if we are are running from RAM. */
+		SCB_MEMMAP = 2;
+	#endif
+
+	/* Configure the RS2332 pins.  All other pins remain at their default of 0. */
+	PCB_PINSEL0 |= mainTX_ENABLE;
+	PCB_PINSEL0 |= mainRX_ENABLE;
+
+	/* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins.  
+	The JTAG pins are left as input as I'm not sure what will happen if the 
+	Wiggler is connected after powerup - not that it would be a good idea to
+	do that anyway. */
+	GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT );
+
+	/* Setup the PLL to multiply the XTAL input by 4. */
+	SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );
+
+	/* Activate the PLL by turning it on then feeding the correct sequence of
+	bytes. */
+	SCB_PLLCON = mainPLL_ENABLE;
+	SCB_PLLFEED = mainPLL_FEED_BYTE1;
+	SCB_PLLFEED = mainPLL_FEED_BYTE2;
+
+	/* Wait for the PLL to lock... */
+	while( !( SCB_PLLSTAT & mainPLL_LOCK ) );
+
+	/* ...before connecting it using the feed sequence again. */
+	SCB_PLLCON = mainPLL_CONNECT;
+	SCB_PLLFEED = mainPLL_FEED_BYTE1;
+	SCB_PLLFEED = mainPLL_FEED_BYTE2;
+
+	/* Setup and turn on the MAM.  Three cycle access is used due to the fast
+	PLL used.  It is possible faster overall performance could be obtained by
+	tuning the MAM and PLL settings. */
+	MAM_TIM = mainMAM_TIM_3;
+	MAM_CR = mainMAM_MODE_FULL;
+
+	/* Setup the peripheral bus to be the same as the PLL output. */
+	SCB_VPBDIV = mainBUS_CLK_FULL;
+	
+	/* Initialise LED outputs. */
+	vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void prvToggleOnBoardLED( void )
+{
+unsigned portLONG ulState;
+
+	ulState = GPIO0_IOPIN;
+	if( ulState & mainON_BOARD_LED_BIT )
+	{
+		GPIO_IOCLR = mainON_BOARD_LED_BIT;
+	}
+	else
+	{
+		GPIO_IOSET = mainON_BOARD_LED_BIT;
+	}	
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
+	{
+		/* The vMemCheckTask did not increment the counter - it must
+		have failed. */
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void vMemCheckTask( void *pvParameters )
+{
+unsigned portLONG *pulMemCheckTaskRunningCounter;
+void *pvMem1, *pvMem2, *pvMem3;
+static portLONG lErrorOccurred = pdFALSE;
+
+	/* This task is dynamically created then deleted during each cycle of the
+	vErrorChecks task to check the operation of the memory allocator.  Each time
+	the task is created memory is allocated for the stack and TCB.  Each time
+	the task is deleted this memory is returned to the heap.  This task itself
+	exercises the allocator by allocating and freeing blocks. 
+	
+	The task executes at the idle priority so does not require a delay. 
+	
+	pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
+	vErrorChecks() task that this task is still executing without error. */
+
+	pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;
+
+	for( ;; )
+	{
+		if( lErrorOccurred == pdFALSE )
+		{
+			/* We have never seen an error so increment the counter. */
+			( *pulMemCheckTaskRunningCounter )++;
+		}
+
+		/* Allocate some memory - just to give the allocator some extra 
+		exercise.  This has to be in a critical section to ensure the
+		task does not get deleted while it has memory allocated. */
+		vTaskSuspendAll();
+		{
+			pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
+			if( pvMem1 == NULL )
+			{
+				lErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
+				vPortFree( pvMem1 );
+			}
+		}
+		xTaskResumeAll();
+
+		/* Again - with a different size block. */
+		vTaskSuspendAll();
+		{
+			pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
+			if( pvMem2 == NULL )
+			{
+				lErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
+				vPortFree( pvMem2 );
+			}
+		}
+		xTaskResumeAll();
+
+		/* Again - with a different size block. */
+		vTaskSuspendAll();
+		{
+			pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
+			if( pvMem3 == NULL )
+			{
+				lErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
+				vPortFree( pvMem3 );
+			}
+		}
+		xTaskResumeAll();
+	}
+}
+
+
+

Demo/ARM7_LPC2106_GCC/ram_arm.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=NO
+set DEBUG=-g
+set OPTIM=-O0
+set RUN_MODE=RUN_FROM_RAM
+set LDSCRIPT=lpc2106-ram.ld
+make

Demo/ARM7_LPC2106_GCC/ram_thumb.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=YES
+set DEBUG=-g
+set OPTIM=-O0
+set RUN_MODE=RUN_FROM_RAM
+set LDSCRIPT=lpc2106-ram.ld
+make

Demo/ARM7_LPC2106_GCC/readme.txt

@@ -0,0 +1,18 @@
+Use one of the following four batch files to build the demo application:
+
++ rom_arm.bat
+
+Creates an ARM mode release build suitable for programming into flash.
+
++ ram_arm.bat
+
+Creates an ARM mode debug build suitable for running from RAM.
+
++ rom_thumb.bat
+
+Creates a THUMB mode release build suitable for programming into flash.
+
++ ram_thumb.bat
+
+Creates a THUMB mode debug build suitable for running from RAM.
+

Demo/ARM7_LPC2106_GCC/rom_arm.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=NO
+set DEBUG=
+set OPTIM=-O3
+set RUN_MODE=RUN_FROM_ROM
+set LDSCRIPT=lpc2106-rom.ld
+make

Demo/ARM7_LPC2106_GCC/rom_thumb.bat

@@ -0,0 +1,6 @@
+set USE_THUMB_MODE=YES
+set DEBUG=
+set OPTIM=-O3
+set RUN_MODE=RUN_FROM_ROM
+set LDSCRIPT=lpc2106-rom.ld
+make

Demo/ARM7_LPC2106_GCC/serial/serial.c

@@ -0,0 +1,263 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*
+	Changes from V2.4.0
+
+		+ Made serial ISR handling more complete and robust.
+
+	Changes from V2.4.1
+
+		+ Split serial.c into serial.c and serialISR.c.  serial.c can be 
+		  compiled using ARM or THUMB modes.  serialISR.c must always be
+		  compiled in ARM mode.
+		+ Another small change to cSerialPutChar().
+
+	Changed from V2.5.1
+
+		+ In cSerialPutChar() an extra check is made to ensure the post to
+		  the queue was successful if then attempting to retrieve the posted
+		  character.
+
+*/
+
+/* 
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. 
+
+	This file contains all the serial port components that can be compiled to
+	either ARM or THUMB mode.  Components that must be compiled to ARM mode are
+	contained in serialISR.c.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup and access the UART. */
+#define serDLAB							( ( unsigned portCHAR ) 0x80 )
+#define serENABLE_INTERRUPTS			( ( unsigned portCHAR ) 0x03 )
+#define serNO_PARITY					( ( unsigned portCHAR ) 0x00 )
+#define ser1_STOP_BIT					( ( unsigned portCHAR ) 0x00 )
+#define ser8_BIT_CHARS					( ( unsigned portCHAR ) 0x03 )
+#define serFIFO_ON						( ( unsigned portCHAR ) 0x01 )
+#define serCLEAR_FIFO					( ( unsigned portCHAR ) 0x06 )
+#define serWANTED_CLOCK_SCALING			( ( unsigned portLONG ) 16 )
+
+/* Constants to setup and access the VIC. */
+#define serUART0_VIC_CHANNEL			( ( unsigned portLONG ) 0x0006 )
+#define serUART0_VIC_CHANNEL_BIT		( ( unsigned portLONG ) 0x0040 )
+#define serUART0_VIC_ENABLE				( ( unsigned portLONG ) 0x0020 )
+#define serCLEAR_VIC_INTERRUPT			( ( unsigned portLONG ) 0 )
+
+#define serINVALID_QUEUE				( ( xQueueHandle ) 0 )
+#define serHANDLE						( ( xComPortHandle ) 1 )
+#define serNO_BLOCK						( ( portTickType ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars; 
+static xQueueHandle xCharsForTx; 
+
+/*-----------------------------------------------------------*/
+
+/* Communication flag between the interrupt service routine and serial API. */
+static volatile portLONG *plTHREEmpty;
+
+/* 
+ * The queues are created in serialISR.c as they are used from the ISR.
+ * Obtain references to the queues and THRE Empty flag. 
+ */
+extern void vSerialISRCreateQueues(	unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulDivisor, ulWantedClock;
+xComPortHandle xReturn = serHANDLE;
+extern void ( vUART_ISR )( void );
+
+	/* The queues are used in the serial ISR routine, so are created from
+	serialISR.c (which is always compiled to ARM mode. */
+	vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );
+
+	if( 
+		( xRxedChars != serINVALID_QUEUE ) && 
+		( xCharsForTx != serINVALID_QUEUE ) && 
+		( ulWantedBaud != ( unsigned portLONG ) 0 ) 
+	  )
+	{
+		portENTER_CRITICAL();
+		{
+			/* Setup the baud rate:  Calculate the divisor value. */
+			ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
+			ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
+
+			/* Set the DLAB bit so we can access the divisor. */
+			UART0_LCR |= serDLAB;
+
+			/* Setup the divisor. */
+			UART0_DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
+			ulDivisor >>= 8;
+			UART0_DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
+
+			/* Turn on the FIFO's and clear the buffers. */
+			UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO );
+
+			/* Setup transmission format. */
+			UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
+
+			/* Setup the VIC for the UART. */
+			VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT );
+			VICIntEnable |= serUART0_VIC_CHANNEL_BIT;
+			VICVectAddr1 = ( portLONG ) vUART_ISR;
+			VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE;
+
+			/* Enable UART0 interrupts. */
+			UART0_IER |= serENABLE_INTERRUPTS;
+		}
+		portEXIT_CRITICAL();
+	}
+	else
+	{
+		xReturn = ( xComPortHandle ) 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+	/* NOTE: This implementation does not handle the queue being full as no
+	block time is used! */
+
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+	( void ) usStringLength;
+
+	/* Send each character in the string, one at a time. */
+	pxNext = ( signed portCHAR * ) pcString;
+	while( *pxNext )
+	{
+		xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+		pxNext++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	/* This demo driver only supports one port so the parameter is not used. */
+	( void ) pxPort;
+
+	portENTER_CRITICAL();
+	{
+		/* Is there space to write directly to the UART? */
+		if( *plTHREEmpty == ( portLONG ) pdTRUE )
+		{
+			/* We wrote the character directly to the UART, so was 
+			successful. */
+			*plTHREEmpty = pdFALSE;
+			UART0_THR = cOutChar;
+			xReturn = pdPASS;
+		}
+		else 
+		{
+			/* We cannot write directly to the UART, so queue the character.
+			Block for a maximum of xBlockTime if there is no space in the
+			queue. */
+			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
+
+			/* Depending on queue sizing and task prioritisation:  While we 
+			were blocked waiting to post interrupts were not disabled.  It is 
+			possible that the serial ISR has emptied the Tx queue, in which
+			case we need to start the Tx off again. */
+			if( ( *plTHREEmpty == ( portLONG ) pdTRUE ) && ( xReturn == pdPASS ) )
+			{
+				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
+				*plTHREEmpty = pdFALSE;
+				UART0_THR = cOutChar;
+			}
+		}
+	}
+	portEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+	/* Not supported as not required by the demo application. */
+	( void ) xPort;
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+	

Demo/ARM7_LPC2106_GCC/serial/serialISR.c

@@ -0,0 +1,163 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license 
+	and contact details.  Please ensure to read the configuration and relevant 
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/* 
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. 
+
+	This file contains all the serial port components that must be compiled
+	to ARM mode.  The components that can be compiled to either ARM or THUMB
+	mode are contained in serial.c.
+
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constant to access the VIC. */
+#define serCLEAR_VIC_INTERRUPT			( ( unsigned portLONG ) 0 )
+
+/* Constants to determine the ISR source. */
+#define serSOURCE_THRE					( ( unsigned portCHAR ) 0x02 )
+#define serSOURCE_RX_TIMEOUT			( ( unsigned portCHAR ) 0x0c )
+#define serSOURCE_ERROR					( ( unsigned portCHAR ) 0x06 )
+#define serSOURCE_RX					( ( unsigned portCHAR ) 0x04 )
+#define serINTERRUPT_SOURCE_MASK		( ( unsigned portCHAR ) 0x0f )
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars; 
+static xQueueHandle xCharsForTx; 
+static volatile portLONG lTHREEmpty;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The queues are created in serialISR.c as they are used from the ISR.
+ * Obtain references to the queues and THRE Empty flag. 
+ */
+void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );
+
+/* UART0 interrupt service routine.  This can cause a context switch so MUST
+be declared "naked". */
+void vUART_ISR( void ) __attribute__ ((naked));
+
+/*-----------------------------------------------------------*/
+void vSerialISRCreateQueues(	unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, 
+								xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag )
+{
+	/* Create the queues used to hold Rx and Tx characters. */
+	xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+	xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+	/* Pass back a reference to the queues so the serial API file can 
+	post/receive characters. */
+	*pxRxedChars = xRxedChars;
+	*pxCharsForTx = xCharsForTx;
+
+	/* Initialise the THRE empty flag - and pass back a reference. */
+	lTHREEmpty = ( portLONG ) pdTRUE;
+	*pplTHREEmptyFlag = &lTHREEmpty;
+}
+/*-----------------------------------------------------------*/
+
+void vUART_ISR( void )
+{
+	/* This ISR can cause a context switch, so the first statement must be a
+	call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
+	variable declarations. */
+	portENTER_SWITCHING_ISR();
+
+	/* Now we can declare the local variables. */
+	signed portCHAR cChar;
+	portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
+
+	/* What caused the interrupt? */
+	switch( UART0_IIR & serINTERRUPT_SOURCE_MASK )
+	{
+		case serSOURCE_ERROR :	/* Not handling this, but clear the interrupt. */
+								cChar = UART0_LSR;
+								break;
+
+		case serSOURCE_THRE	:	/* The THRE is empty.  If there is another
+								character in the Tx queue, send it now. */
+								if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
+								{
+									UART0_THR = cChar;
+								}
+								else
+								{
+									/* There are no further characters 
+									queued to send so we can indicate 
+									that the THRE is available. */
+									lTHREEmpty = pdTRUE;
+								}
+								break;
+
+		case serSOURCE_RX_TIMEOUT :
+		case serSOURCE_RX	:	/* A character was received.  Place it in 
+								the queue of received characters. */
+								cChar = UART0_RBR;
+								if( xQueueSendFromISR( xRxedChars, &cChar, ( portBASE_TYPE ) pdFALSE ) ) 
+								{
+									xTaskWokenByRx = pdTRUE;
+								}
+								break;
+
+		default				:	/* There is nothing to do, leave the ISR. */
+								break;
+	}
+
+	/* Clear the ISR in the VIC. */
+	VICVectAddr = serCLEAR_VIC_INTERRUPT;
+
+	/* Exit the ISR.  If a task was woken by either a character being received
+	or transmitted then a context switch will occur. */
+	portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+	

Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h

@@ -0,0 +1,78 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/* Hardware specifics. */
+#include <iolpc2129.h>
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 60000000 )	/* =12.0MHz xtal multiplied by 5 using the PLL. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 100 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) 14200 )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				0
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */

Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c

@@ -0,0 +1,102 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines for the LED's.
+ *-----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Board specific defines. */
+#define partstFIRST_IO		( ( unsigned portLONG ) 0x10000 )
+#define partstNUM_LEDS		( 8 )
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{	
+	/* The ports are setup within prvInitialiseHardware(), called by main(). */
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+unsigned portLONG ulLED = partstFIRST_IO;
+
+	if( uxLED < partstNUM_LEDS )
+	{
+		/* Rotate to the wanted bit of port 1.  Only P16 to P23 have an LED
+		attached. */
+		ulLED <<= ( unsigned portLONG ) uxLED;
+
+		/* Set or clear the output. */
+		if( xValue )
+		{
+			IO1SET = ulLED;
+		}
+		else
+		{
+			IO1CLR = ulLED;			
+		}
+	}	
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;
+
+	if( uxLED < partstNUM_LEDS )
+	{
+		/* Rotate to the wanted bit of port 1.  Only P10 to P13 have an LED
+		attached. */
+		ulLED <<= ( unsigned portLONG ) uxLED;
+
+		/* If this bit is already set, clear it, and visa versa. */
+		ulCurrentState = IO1PIN;
+		if( ulCurrentState & ulLED )
+		{
+			IO1CLR = ulLED;
+		}
+		else
+		{
+			IO1SET = ulLED;			
+		}
+	}	
+}
+
+

Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79

@@ -0,0 +1,173 @@
+;-----------------------------------------------------------------------------
+; This file contains the startup code used by the ICCARM C compiler.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; All code in the modules (except ?RESET) will be placed in the ICODE segment.
+;
+; $Revision: 1.56 $
+;
+;-----------------------------------------------------------------------------
+	
+;
+; Naming covention of labels in this file:
+;
+;  ?xxx	  - External labels only accessed from assembler.
+;  __xxx  - External labels accessed from or defined in C.
+;  xxx	  - Labels local to one module (note: this file contains
+;           several modules).
+;  main	  - The starting point of the user program.
+;
+
+;---------------------------------------------------------------
+; Macros and definitions for the whole file
+;---------------------------------------------------------------
+
+; Mode, correspords to bits 0-5 in CPSR
+MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
+USR_MODE	DEFINE	0x10		; User mode
+FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
+IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
+SVC_MODE	DEFINE	0x13		; Supervisor mode
+ABT_MODE	DEFINE	0x17		; Abort mode
+UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
+SYS_MODE	DEFINE	0x1F		; System mode
+	
+I_Bit       DEFINE  0x80        ; IRQ Disable Bit
+F_Bit       DEFINE  0x40        ; FIQ Disable Bit
+
+;---------------------------------------------------------------
+; ?RESET
+; Reset Vector.
+; Normally, segment INTVEC is linked at address 0.
+; For debugging purposes, INTVEC may be placed at other
+; addresses.
+; A debugger that honors the entry point will start the
+; program in a normal way even if INTVEC is not at address 0.
+;---------------------------------------------------------------
+
+		MODULE	?RESET
+		COMMON	INTVEC:CODE:NOROOT(2)
+		PUBLIC  __program_start
+		EXTERN	?cstartup
+		EXTERN	undef_handler, swi_handler, prefetch_handler
+		EXTERN	data_handler, irq_handler, fiq_handler
+   		EXTERN	vPortYieldProcessor
+
+		CODE32	; Always ARM mode after reset	
+
+__program_start
+
+		org	0x00
+
+						B           InitReset           ; 0x00 Reset handler
+		undefvec:
+						B           undefvec            ; 0x04 Undefined Instruction
+		swivec:
+						B           vPortYieldProcessor ; 0x08 Software Interrupt
+		pabtvec:
+						B           pabtvec             ; 0x0C Prefetch Abort
+		dabtvec:
+						B           dabtvec             ; 0x10 Data Abort
+		rsvdvec:
+						B           rsvdvec             ; 0x14 reserved
+		irqvec:
+						LDR			PC, [PC, #-0xFF0]	; Jump directly to the address given by the AIC
+		
+		fiqvec:               							; 0x1c FIQ
+
+
+;---------------------------------------------------------------
+; ?CSTARTUP
+;---------------------------------------------------------------
+
+		RSEG	IRQ_STACK:DATA(2)
+		RSEG	SVC_STACK:DATA:NOROOT(2)
+		RSEG	CSTACK:DATA(2)
+		RSEG	ICODE:CODE:NOROOT(2)
+		EXTERN	?main
+
+; Execution starts here.
+; After a reset, the mode is ARM, Supervisor, interrupts disabled.
+
+
+		CODE32
+
+InitReset
+
+; Add initialization needed before setup of stackpointers here
+
+
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+                mrs     r0,cpsr                             ; Original PSR value
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8     ; End of IRQ_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(CSTACK) & 0xFFFFFFF8        ; End of CSTACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#SVC_MODE                     ; Set System mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(SVC_STACK) & 0xFFFFFFF8     ; End of CSTACK
+
+; Must start in supervisor mode.
+                MSR     CPSR_c, #SVC_MODE|I_Bit|F_Bit
+
+
+; Add more initialization here
+
+
+; Continue to ?main for more IAR specific system startup
+
+                ldr     r0,=?main
+                bx      r0
+
+
+
+
+;---------------------------------------------------------------
+; ?EXEPTION_VECTOR
+; This module is only linked if needed for closing files.
+;---------------------------------------------------------------
+		PUBLIC	AT91F_Default_FIQ_handler
+		PUBLIC	AT91F_Default_IRQ_handler
+		PUBLIC	AT91F_Spurious_handler
+
+		CODE32	; Always ARM mode after exeption	
+
+AT91F_Default_FIQ_handler
+            b     AT91F_Default_FIQ_handler
+
+AT91F_Default_IRQ_handler
+            b     AT91F_Default_IRQ_handler
+
+AT91F_Spurious_handler
+            b     AT91F_Spurious_handler
+
+	ENDMOD
+
+	END
+
+
+
+
+                ENDMOD
+                END
+
+
+
+

Demo/ARM7_LPC2129_IAR/main.c

@@ -0,0 +1,284 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ *
+ * Main.c also creates a task called "Check".  This only executes every three
+ * seconds but has the highest priority so is guaranteed to get processor time.
+ * Its main function is to check that all the other tasks are still operational.
+ * Each task (other than the "flash" tasks) maintains a unique count that is
+ * incremented each time the task successfully completes its function.  Should
+ * any error occur within such a task the count is permanently halted.  The
+ * check task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have
+ * changed all the tasks are still executing error free, and the check task
+ * toggles the onboard LED.  Should any task contain an error at any time
+ * the LED toggle rate will change from 3 seconds to 500ms.
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "flash.h"
+#include "integer.h"
+#include "PollQ.h"
+#include "BlockQ.h"
+#include "semtest.h"
+#include "dynamic.h"
+#include "partest.h"
+#include "comtest2.h"
+
+/* Priorities for the demo application tasks. */
+#define mainLED_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define mainCOM_TEST_PRIORITY		( tskIDLE_PRIORITY + 2 )
+
+/* Constants required by the 'Check' task. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+#define mainCHECK_TASK_LED			( 7 )
+
+/* Constants for the ComTest tasks. */
+#define mainCOM_TEST_BAUD_RATE		( ( unsigned portLONG ) 115200 )
+#define mainCOM_TEST_LED			( 4 )
+#define mainTX_ENABLE				( ( unsigned portLONG ) 0x0001 )
+#define mainRX_ENABLE				( ( unsigned portLONG ) 0x0004 )
+
+/* Constants to setup the PLL. */
+#define mainPLL_MUL_4				( ( unsigned portCHAR ) 0x0003 )
+#define mainPLL_DIV_1				( ( unsigned portCHAR ) 0x0000 )
+#define mainPLL_ENABLE				( ( unsigned portCHAR ) 0x0001 )
+#define mainPLL_CONNECT				( ( unsigned portCHAR ) 0x0003 )
+#define mainPLL_FEED_BYTE1			( ( unsigned portCHAR ) 0xaa )
+#define mainPLL_FEED_BYTE2			( ( unsigned portCHAR ) 0x55 )
+#define mainPLL_LOCK				( ( unsigned portLONG ) 0x0400 )
+
+/* Constants to setup the MAM. */
+#define mainMAM_TIM_3				( ( unsigned portCHAR ) 0x03 )
+#define mainMAM_MODE_FULL			( ( unsigned portCHAR ) 0x02 )
+
+/* Constants to setup the peripheral bus. */
+#define mainBUS_CLK_FULL			( ( unsigned portCHAR ) 0x01 )
+
+/* And finally, constant to setup the port for the LED's. */
+#define mainLED_TO_OUTPUT			( ( unsigned portLONG ) 0xff0000 )
+
+/*
+ * The task that executes at the highest priority and calls
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configures the processor for use with this demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler.
+ */
+void main( void )
+{
+	/* Setup the processor. */
+	prvSetupHardware();
+
+	/* Start all the standard demo application tasks. */
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+	vStartDynamicPriorityTasks();
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
+		
+	/* Start the check task - which is defined in this file. */
+	xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Start the scheduler.
+ 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here.
+	*/
+	vTaskStartScheduler();
+
+	/* We should never get here as control is now taken by the scheduler. */
+  	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* Setup the PLL to multiply the XTAL input by 4. */
+	PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );
+
+	/* Activate the PLL by turning it on then feeding the correct sequence of
+	bytes. */
+	PLLCON = mainPLL_ENABLE;
+	PLLFEED = mainPLL_FEED_BYTE1;
+	PLLFEED = mainPLL_FEED_BYTE2;
+
+	/* Wait for the PLL to lock... */
+	while( !( PLLSTAT & mainPLL_LOCK ) );
+
+	/* ...before connecting it using the feed sequence again. */
+	PLLCON = mainPLL_CONNECT;
+	PLLFEED = mainPLL_FEED_BYTE1;
+	PLLFEED = mainPLL_FEED_BYTE2;
+
+	/* Setup and turn on the MAM.  Three cycle access is used due to the fast
+	PLL used.  It is possible faster overall performance could be obtained by
+	tuning the MAM and PLL settings. */
+	MAMTIM = mainMAM_TIM_3;
+	MAMCR = mainMAM_MODE_FULL;
+
+	/* Setup the peripheral bus to be the same as the PLL output. */
+	VPBDIV = mainBUS_CLK_FULL;
+	
+	/* Configure the RS2332 pins.  All other pins remain at their default of 0. */
+	PINSEL0 |= mainTX_ENABLE;
+	PINSEL0 |= mainRX_ENABLE;
+
+	/* LED pins need to be output. */
+	IO1DIR = mainLED_TO_OUTPUT;
+
+	/* Setup the peripheral bus to be the same as the PLL output. */
+	VPBDIV = mainBUS_CLK_FULL;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+
+	/* The parameters are not used in this task. */
+	( void ) pvParameters;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the on board LED flash rate will increase. */
+
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelay( xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without
+		error. */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+		
+		vParTestToggleLED( mainCHECK_TASK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+

Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl

@@ -0,0 +1,190 @@
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage:  xlink  -f lnkarm  <your_object_file(s)>
+//                -s <program start label>  <C/C++ runtime library>
+//
+// $Revision: 1.1 $
+//*************************************************************************
+
+//*************************************************************************
+//
+// -------------
+// Code segments - may be placed anywhere in memory.
+// -------------
+//
+//   INTVEC     -- Exception vector table.
+//   SWITAB     -- Software interrupt vector table.
+//   ICODE      -- Startup (cstartup) and exception code.
+//   DIFUNCT    -- Dynamic initialization vectors used by C++.
+//   CODE       -- Compiler generated code.
+//   CODE_I     -- Compiler generated code declared __ramfunc (executes in RAM)
+//   CODE_ID    -- Initializer for CODE_I (ROM).
+//
+// -------------
+// Data segments - may be placed anywhere in memory.
+// -------------
+//
+//   CSTACK     -- The stack used by C/C++ programs (system and user mode).
+//   IRQ_STACK  -- The stack used by IRQ service routines.
+//   SVC_STACK  -- The stack used in supervisor mode
+//                 (Define other exception stacks as needed for
+//                 FIQ, ABT, UND).
+//   HEAP       -- The heap used by malloc and free in C and new and
+//                 delete in C++.
+//   INITTAB    -- Table containing addresses and sizes of segments that
+//                 need to be initialized at startup (by cstartup).
+//   CHECKSUM   -- The linker places checksum byte(s) in this segment,
+//                 when the -J linker command line option is used.
+//   DATA_y     -- Data objects.
+//
+// Where _y can be one of:
+//
+//   _AN        -- Holds uninitialized located objects, i.e. objects with
+//                 an absolute location given by the @ operator or the
+//                 #pragma location directive. Since these segments
+//                 contain objects which already have a fixed address,
+//                 they should not be mentioned in this linker command
+//                 file.
+//   _C         -- Constants (ROM).
+//   _I         -- Initialized data (RAM).
+//   _ID        -- The original content of _I (copied to _I by cstartup) (ROM).
+//   _N         -- Uninitialized data (RAM).
+//   _Z         -- Zero initialized data (RAM).
+//
+// Note:  Be sure to use end values for the defined address ranges.
+//        Otherwise, the linker may allocate space outside the
+//        intended memory range.
+//*************************************************************************
+
+
+//************************************************
+// Inform the linker about the CPU family used.
+//************************************************
+
+-carm
+
+//*************************************************************************
+// Segment placement - General information
+//
+// All numbers in the segment placement command lines below are interpreted
+// as hexadecimal unless they are immediately preceded by a '.', which
+// denotes decimal notation. 
+//
+// When specifying the segment placement using the -P instead of the -Z
+// option, the linker is free to split each segment into its segment parts
+// and randomly place these parts within the given ranges in order to
+// achieve a more efficient memory usage. One disadvantage, however, is
+// that it is not possible to find the start or end address (using
+// the assembler operators .sfb./.sfe.) of a segment which has been split
+// and reformed. 
+//
+// When generating an output file which is to be used for programming
+// external ROM/Flash devices, the -M linker option is very useful 
+// (see xlink.pdf for details).
+//*************************************************************************
+
+
+//*************************************************************************
+// Read-only segments mapped to ROM.
+//*************************************************************************
+
+-DROMSTART=00000000
+-DROMEND=00001ffff
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes, 
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+
+-Z(CODE)INTVEC=00000000-0000003f
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Original ROM location for __ramfunc code copied
+// to and executed from RAM.
+//************************************************
+
+-Z(CONST)CODE_ID=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+//*************************************************************************
+// Read/write segments mapped to RAM.
+//*************************************************************************
+
+-DRAMSTART=40000000
+-DRAMEND=40003fff
+
+//************************************************
+// Data segments.
+//************************************************
+
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// CODE_ID segment instead, but to keep symbol and
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+-QCODE_I=CODE_ID
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+
+-D_CSTACK_SIZE=200
+-D_SVC_STACK_SIZE=190
+-D_IRQ_STACK_SIZE=190
+-D_HEAP_SIZE=4
+
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+//   "-yn": Suppress DWARF debug output
+//   "-yp": Multiple ELF program sections
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf

Demo/ARM7_LPC2129_IAR/rtosdemo.ewd

@@ -0,0 +1,913 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>1</fileVersion>
+  <configuration>
+    <name>Flash Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>13</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\iolpc2129.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.10B</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>JLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>4.30A</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FlashLoaders</name>
+          <state>,,,,(default),</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommunication</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>30</state>
+        </option>
+        <option>
+          <name>CCJLinkHWReset</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkTRSTReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDIUseETM</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>Flash Bin</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>13</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\iolpc2129.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.10B</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>JLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>4.30A</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FlashLoaders</name>
+          <state>,,,,(default),</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommunication</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>30</state>
+        </option>
+        <option>
+          <name>CCJLinkHWReset</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkTRSTReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDIUseETM</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+

Demo/ARM7_LPC2129_IAR/rtosdemo.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\rtosdemo.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

Demo/ARM7_LPC2129_IAR/serial/serial.c

@@ -0,0 +1,288 @@
+/*
+	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+	See http://www.FreeRTOS.org for documentation, latest information, license
+	and contact details.  Please ensure to read the configuration and relevant
+	port sections of the online documentation.
+	***************************************************************************
+*/
+
+
+/*
+	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup and access the UART. */
+#define serDLAB							( ( unsigned portCHAR ) 0x80 )
+#define serENABLE_INTERRUPTS			( ( unsigned portCHAR ) 0x03 )
+#define serNO_PARITY					( ( unsigned portCHAR ) 0x00 )
+#define ser1_STOP_BIT					( ( unsigned portCHAR ) 0x00 )
+#define ser8_BIT_CHARS					( ( unsigned portCHAR ) 0x03 )
+#define serFIFO_ON						( ( unsigned portCHAR ) 0x01 )
+#define serCLEAR_FIFO					( ( unsigned portCHAR ) 0x06 )
+#define serWANTED_CLOCK_SCALING			( ( unsigned portLONG ) 16 )
+
+/* Constants to setup and access the VIC. */
+#define serU0VIC_CHANNEL				( ( unsigned portLONG ) 0x0006 )
+#define serU0VIC_CHANNEL_BIT			( ( unsigned portLONG ) 0x0040 )
+#define serU0VIC_ENABLE					( ( unsigned portLONG ) 0x0020 )
+#define serCLEAR_VIC_INTERRUPT			( ( unsigned portLONG ) 0 )
+
+/* Constants to determine the ISR source. */
+#define serSOURCE_THRE					( ( unsigned portCHAR ) 0x02 )
+#define serSOURCE_RX_TIMEOUT			( ( unsigned portCHAR ) 0x0c )
+#define serSOURCE_ERROR					( ( unsigned portCHAR ) 0x06 )
+#define serSOURCE_RX					( ( unsigned portCHAR ) 0x04 )
+#define serINTERRUPT_SOURCE_MASK		( ( unsigned portCHAR ) 0x0f )
+
+/* Misc. */
+#define serINVALID_QUEUE				( ( xQueueHandle ) 0 )
+#define serHANDLE						( ( xComPortHandle ) 1 )
+#define serNO_BLOCK						( ( portTickType ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+static volatile portLONG lTHREEmpty = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+/* The ISR.  Note that this is called by a wrapper written in the file
+SerialISR.s79.  See the WEB documentation for this port for further
+information. */
+__arm void vSerialISR( void );
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulDivisor, ulWantedClock;
+xComPortHandle xReturn = serHANDLE;
+extern void ( vSerialISREntry) ( void );
+
+	/* Create the queues used to hold Rx and Tx characters. */
+	xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+	xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+	/* Initialise the THRE empty flag. */
+	lTHREEmpty = pdTRUE;
+
+	if(
+		( xRxedChars != serINVALID_QUEUE ) &&
+		( xCharsForTx != serINVALID_QUEUE ) &&
+		( ulWantedBaud != ( unsigned portLONG ) 0 )
+	  )
+	{
+		portENTER_CRITICAL();
+		{
+			/* Setup the baud rate:  Calculate the divisor value. */
+			ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
+			ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
+
+			/* Set the DLAB bit so we can access the divisor. */
+			U0LCR |= serDLAB;
+
+			/* Setup the divisor. */
+			U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
+			ulDivisor >>= 8;
+			U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
+
+			/* Turn on the FIFO's and clear the buffers. */
+			U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
+
+			/* Setup transmission format. */
+			U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
+
+			/* Setup the VIC for the UART. */
+			VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
+			VICIntEnable |= serU0VIC_CHANNEL_BIT;
+			VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry;
+			VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
+
+			/* Enable UART0 interrupts. */
+			U0IER |= serENABLE_INTERRUPTS;
+		}
+		portEXIT_CRITICAL();
+
+		xReturn = ( xComPortHandle ) 1;
+	}
+	else
+	{
+		xReturn = ( xComPortHandle ) 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+	/* NOTE: This implementation does not handle the queue being full as no
+	block time is used! */
+
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+	( void ) usStringLength;
+
+	/* Send each character in the string, one at a time. */
+	pxNext = ( signed portCHAR * ) pcString;
+	while( *pxNext )
+	{
+		xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+		pxNext++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	/* The port handle is not required as this driver only supports UART0. */
+	( void ) pxPort;
+
+	portENTER_CRITICAL();
+	{
+		/* Is there space to write directly to the UART? */
+		if( lTHREEmpty == ( portLONG ) pdTRUE )
+		{
+			/* We wrote the character directly to the UART, so was
+			successful. */
+			lTHREEmpty = pdFALSE;
+			U0THR = cOutChar;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* We cannot write directly to the UART, so queue the character.
+			Block for a maximum of xBlockTime if there is no space in the
+			queue.  It is ok to block within a critical section as each
+			task has it's own critical section management. */
+			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
+
+			/* Depending on queue sizing and task prioritisation:  While we
+			were blocked waiting to post interrupts were not disabled.  It is
+			possible that the serial ISR has emptied the Tx queue, in which
+			case we need to start the Tx off again. */
+			if( lTHREEmpty == ( portLONG ) pdTRUE )
+			{
+				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
+				lTHREEmpty = pdFALSE;
+				U0THR = cOutChar;
+			}
+		}
+	}
+	portEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+__arm void vSerialISR( void )
+{
+signed portCHAR cChar;
+portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE;
+
+	/* What caused the interrupt? */
+	switch( U0IIR & serINTERRUPT_SOURCE_MASK )
+	{
+		case serSOURCE_ERROR :	/* Not handling this, but clear the interrupt. */
+								cChar = U0LSR;
+								break;
+
+		case serSOURCE_THRE	:	/* The THRE is empty.  If there is another
+								character in the Tx queue, send it now. */
+								if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
+								{
+									U0THR = cChar;
+								}
+								else
+								{
+									/* There are no further characters
+									queued to send so we can indicate
+									that the THRE is available. */
+									lTHREEmpty = pdTRUE;
+								}
+								break;
+
+		case serSOURCE_RX_TIMEOUT :
+		case serSOURCE_RX	:	/* A character was received.  Place it in
+								the queue of received characters. */
+								cChar = U0RBR;
+								if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+								{
+									xTaskWokenByRx = pdTRUE;
+								}
+								break;
+
+		default				:	/* There is nothing to do, leave the ISR. */
+								break;
+	}
+
+	/* Exit the ISR.  If a task was woken by either a character being received
+	or transmitted then a context switch will occur. */
+	portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
+
+	/* Clear the ISR in the VIC. */
+	VICVectAddr = serCLEAR_VIC_INTERRUPT;
+}
+/*-----------------------------------------------------------*/

Demo/ARM7_LPC2129_IAR/serial/serialISR.s79

@@ -0,0 +1,24 @@
+		RSEG ICODE:CODE
+		CODE32
+
+		EXTERN vSerialISR
+		PUBLIC vSerialISREntry
+
+; Wrapper for the serial port interrupt service routine.  This can cause a
+; context switch so requires an assembly wrapper.
+
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
+#include "ISR_Support.h"
+
+vSerialISREntry:
+
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	bl	vSerialISR				; Call the ISR routine.
+
+	portRESTORE_CONTEXT			; Restore the context of the current task -
+								; which may be different to the task that
+								; was interrupted.
+
+		END
+

Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt

@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Project>
+  <Desktop>
+    <Static>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
+        <Column0>189</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>
+      </Workspace>
+      <Disassembly>
+        
+        
+        
+      <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
+      <Debug-Log/>
+      <Build/>
+    <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><QWatch><Column0>188</Column0><Column1>171</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Watch><Format><struct_types/><watch_formats/></Format></Watch></Static>
+    <Windows>
+      <Wnd0>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-23416-30482</Identity>
+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
+            <Session>
+              
+            <NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd0>
+      
+      <Wnd2>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-12145-30489</Identity>
+            <TabName>Debug Log</TabName>
+            <Factory>Debug-Log</Factory>
+            <Session/>
+          </Tab>
+          <Tab>
+            <Identity>TabID-22894-30492</Identity>
+            <TabName>Build</TabName>
+            <Factory>Build</Factory>
+            <Session/>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>1</SelectedTab></Wnd2>
+    <Wnd4><Tabs><Tab><Identity>TabID-18780-12821</Identity><TabName>Memory</TabName><Factory>Memory</Factory><Session><SelectionAnchor>2097764</SelectionAnchor><SelectionEnd>2097764</SelectionEnd><UnitsPerGroup>1</UnitsPerGroup><EndianMode>0</EndianMode><DataCovEnabled>0</DataCovEnabled><DataCovShown>0</DataCovShown></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-23506-14575</Identity><TabName>Watch</TabName><Factory>Watch</Factory><Session><Expressions><Expression><Expression>pxCurrentTCB</Expression></Expression><Expression><Expression>ulCriticalNesting</Expression></Expression></Expressions><TabId>0</TabId><Column0>176</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5><Wnd1><Tabs><Tab><Identity>TabID-4859-22480</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1><Wnd3><Tabs><Tab><Identity>TabID-154-22568</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
+    <Editor>
+      
+      
+      
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