[AUTO][RELEASE]: Bump file header version to "10.4.3 LTS Patch 3"

[AUTO][RELEASE]: Bump task.h version macros to "10.4.3 LTS Patch 3"
Update History.txt as per PR feedback
2025-04-19 21:11:57 -04:00 · 2022-09-16 18:13:25 +00:00 · 2022-09-16 18:13:24 +00:00 · 2022-09-16 22:18:35 +05:30 · 2022-09-16 22:18:35 +05:30 · 2022-09-16 22:18:35 +05:30
468 changed files with 5079 additions and 3019 deletions
--- a/.github/lexicon.txt
+++ b/.github/lexicon.txt
@ -2533,7 +2533,6 @@ vportgetheapstats
 vportinitialiseblocks
 vportisrstartfirststask
 vportraisebasepri
 vportresetprivilege
 vportsetmpuregistersetone
 vportsetuptimerinterrupt
 vportstartfirststask
@ -2852,7 +2851,6 @@ xperiod
 xportgetcoreid
 xportgetfreeheapsize
 xportinstallinterrupthandler
 xportraiseprivilege
 xportregistercinterrupthandler
 xportregisterdump
 xportstartfirsttask
--- a/.github/workflows/header-checks.yml
+++ b/.github/workflows/header-checks.yml
@ -16,12 +16,12 @@ jobs:
        env:
          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-      # Get latest checks from master
+      # Get latest checks from main
      - name: Checkout FreeRTOS Tools
        uses: actions/checkout@v2
        with:
          repository: FreeRTOS/FreeRTOS
-          ref:  master
+          ref:  main
          path: tools
      # Checkout user pull request changes
--- a/History.txt
+++ b/History.txt
@ -1,5 +1,65 @@
 Documentation and download available at https://www.FreeRTOS.org/
 Changes between FreeRTOS V10.4.3 LTS Patch 2 and FreeRTOS V10.4.3 LTS Patch 3 released September 16 2022
 	+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
 	  already independently gained the ability to execute injected code to
 	  read from or write to arbitrary addresses by passing a negative argument
 	  as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or
 	  vTaskSetThreadLocalStoragePointer respectively. A check has been added to
 	  ensure that passing a negative argument as the xIndex parameter does not
 	  cause arbitrary read or write.
 	  We thank Certibit Consulting, LLC for reporting this issue.
 	+ ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task
 	  to invoke any function with privilege by passing it as a parameter to
 	  MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate,
 	  MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate
 	  and MPU_xTaskCreateStatic have been updated to only allow creation of
 	  unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and
 	  MPU_xTimerPendFunctionCall APIs have been removed.
 	  We thank Huazhong University of Science and Technology for reporting
 	  this issue.
 	+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
 	  already independently gained the ability to execute injected code to
 	  achieve further privilege escalation by branching directly inside a
 	  FreeRTOS MPU API wrapper function with a manually crafted stack frame.
 	  The local stack variable `xRunningPrivileged` has been removed so that
 	  a manually crafted stack frame cannot be used for privilege escalation
 	  by branching directly inside a FreeRTOS MPU API wrapper.
 	  We thank Certibit Consulting, LLC, Huazhong University of Science and
 	  Technology and the SecLab team at Northeastern University for reporting
 	  this issue.
 	+ ARMv7-M MPU ports: It was possible to configure overlapping memory
 	  protection unit (MPU) regions such that an unprivileged task could access
 	  privileged data. The kernel now uses highest numbered MPU regions for
 	  kernel protections to prevent such MPU configurations.
 	  We thank the SecLab team at Northeastern University for reporting this
 	  issue.
 Changes between FreeRTOS V10.4.3 LTS Patch 1 and FreeRTOS V10.4.3 LTS Patch 2 released November 12 2021
 	+ ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the
 	  internal functions xPortRaisePrivilege and vPortResetPrivilege by changing
 	  them to macros.
 Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.3 LTS Patch 1 released September 10 2021
 	See https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html
 	+ ARMv8-M secure-side port:  Tasks that call secure functions from the
 	  non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two
 	  contexts – one on the non-secure side and one on the secure-side. Previous
 	  versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures
 	  that reference secure-side contexts at run time.  Now the structures are
 	  allocated statically at compile time.  The change necessitates the
 	  introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant,
 	  which sets the number of statically allocated secure contexts.
 	  secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined.
 	  Applications that only use FreeRTOS code on the non-secure side, such as
 	  those running third-party code on the secure side, are not affected by
 	  this change.
 Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
 	V10.4.3 is included in the 202012.00 LTS release.  Learn more at https:/freertos.org/lts-libraries.html
--- a/croutine.c
+++ b/croutine.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/event_groups.c
+++ b/event_groups.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/FreeRTOS.h
+++ b/include/FreeRTOS.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/StackMacros.h
+++ b/include/StackMacros.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/atomic.h
+++ b/include/atomic.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/croutine.h
+++ b/include/croutine.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/deprecated_definitions.h
+++ b/include/deprecated_definitions.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/event_groups.h
+++ b/include/event_groups.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/list.h
+++ b/include/list.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/message_buffer.h
+++ b/include/message_buffer.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/mpu_prototypes.h
+++ b/include/mpu_prototypes.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/mpu_wrappers.h
+++ b/include/mpu_wrappers.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -117,13 +117,10 @@
        #endif
 /* Map standard timer.h API functions to the MPU equivalents. */
        #define xTimerCreate                           MPU_xTimerCreate
        #define xTimerCreateStatic                     MPU_xTimerCreateStatic
        #define pvTimerGetTimerID                      MPU_pvTimerGetTimerID
        #define vTimerSetTimerID                       MPU_vTimerSetTimerID
        #define xTimerIsTimerActive                    MPU_xTimerIsTimerActive
        #define xTimerGetTimerDaemonTaskHandle         MPU_xTimerGetTimerDaemonTaskHandle
        #define xTimerPendFunctionCall                 MPU_xTimerPendFunctionCall
        #define pcTimerGetName                         MPU_pcTimerGetName
        #define vTimerSetReloadMode                    MPU_vTimerSetReloadMode
        #define uxTimerGetReloadMode                   MPU_uxTimerGetReloadMode
@ -165,7 +162,7 @@
    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-/* Ensure API functions go in the privileged execution section. */
+        /* Ensure API functions go in the privileged execution section. */
        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
--- a/include/portable.h
+++ b/include/portable.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/projdefs.h
+++ b/include/projdefs.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/queue.h
+++ b/include/queue.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/semphr.h
+++ b/include/semphr.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/stack_macros.h
+++ b/include/stack_macros.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/stdint.readme
+++ b/include/stdint.readme
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/stream_buffer.h
+++ b/include/stream_buffer.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/include/task.h
+++ b/include/task.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -44,7 +44,7 @@
 * MACROS AND DEFINITIONS
 *----------------------------------------------------------*/
-#define tskKERNEL_VERSION_NUMBER       "V10.4.3"
+#define tskKERNEL_VERSION_NUMBER       "V10.4.3 LTS Patch 3"
 #define tskKERNEL_VERSION_MAJOR        10
 #define tskKERNEL_VERSION_MINOR        4
 #define tskKERNEL_VERSION_BUILD        3
@ -2758,7 +2758,7 @@ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
 *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
 *  // continues until either the buffer contains at least uxWantedBytes bytes,
 *  // or the total amount of time spent in the Blocked state reaches
- *  // MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+ *  // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are
 *  // available up to a maximum of uxWantedBytes.
 *
 *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
--- a/include/timers.h
+++ b/include/timers.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/list.c
+++ b/list.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/copy_files.py
+++ b/portable/ARMv8M/copy_files.py
@ -1,5 +1,5 @@
 #/*
-# * FreeRTOS Kernel V10.4.3
+# * FreeRTOS Kernel V10.4.3 LTS Patch 3
 # * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 # *
 # * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/port.c
+++ b/portable/ARMv8M/non_secure/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -779,7 +779,8 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
    uint32_t ulPC;
    #if ( configENABLE_TRUSTZONE == 1 )
-        uint32_t ulR0;
+        uint32_t ulR0, ulR1;
        extern TaskHandle_t pxCurrentTCB;
        #if ( configENABLE_MPU == 1 )
            uint32_t ulControl, ulIsTaskPrivileged;
        #endif /* configENABLE_MPU */
@ -810,25 +811,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
                        /* Allocate and load a context for the secure task. */
-                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
                    }
                #else /* if ( configENABLE_MPU == 1 ) */
                    {
                        /* Allocate and load a context for the secure task. */
-                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                        xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
                    }
                #endif /* configENABLE_MPU */
-                configASSERT( xSecureContext != NULL );
+                configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
-                SecureContext_LoadContext( xSecureContext );
+                SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
                break;
            case portSVC_FREE_SECURE_CONTEXT:
-                /* R0 contains the secure context handle to be freed. */
+                /* R0 contains TCB being freed and R1 contains the secure
                 * context handle to be freed. */
                ulR0 = pulCallerStackAddress[ 0 ];
                ulR1 = pulCallerStackAddress[ 1 ];
                /* Free the secure context. */
-                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
                break;
        #endif /* configENABLE_TRUSTZONE */
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -232,64 +232,66 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
        "	.extern SecureContext_SaveContext				\n"
        "	.extern SecureContext_LoadContext				\n"
        "													\n"
-        "	mrs r1, psp										\n"/* Read PSP in r1. */
+        "	ldr r3, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r3]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "	ldr r0, [r2]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
        "	mrs r2, psp										\n"/* Read PSP in r2. */
        "													\n"
        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
        "	push {r0-r2, r14}								\n"
-        "	bl SecureContext_SaveContext					\n"
+        "	bl SecureContext_SaveContext					\n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
        "	pop {r0-r3}										\n"/* LR is now in r3. */
        "	mov lr, r3										\n"/* LR = r3. */
-        "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	lsls r1, r3, #25								\n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
        #if ( configENABLE_MPU == 1 )
-            "	subs r1, r1, #16								\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	subs r2, r2, #16							\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mrs r3, control								\n"/* r3 = CONTROL. */
            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
-            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
        #else /* configENABLE_MPU */
-            "	subs r1, r1, #12								\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	subs r2, r2, #12							\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
-            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
        #endif /* configENABLE_MPU */
        "	b select_next_task								\n"
        "													\n"
        " save_ns_context:									\n"
        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
        #if ( configENABLE_MPU == 1 )
-            "	subs r1, r1, #48								\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	subs r2, r2, #48							\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	adds r1, r1, #16								\n"/* r1 = r1 + 16. */
+            "	adds r2, r2, #16							\n"/* r2 = r2 + 16. */
-            "	stmia r1!, {r4-r7}								\n"/* Store the low registers that are not saved automatically. */
+            "	stmia r2!, {r4-r7}							\n"/* Store the low registers that are not saved automatically. */
            "	mov r4, r8									\n"/* r4 = r8. */
            "	mov r5, r9									\n"/* r5 = r9. */
            "	mov r6, r10									\n"/* r6 = r10. */
            "	mov r7, r11									\n"/* r7 = r11. */
-            "	stmia r1!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+            "	stmia r2!, {r4-r7}							\n"/* Store the high registers that are not saved automatically. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mrs r3, control								\n"/* r3 = CONTROL. */
            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
-            "	subs r1, r1, #48								\n"/* r1 = r1 - 48. */
+            "	subs r2, r2, #48							\n"/* r2 = r2 - 48. */
-            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
        #else /* configENABLE_MPU */
-            "	subs r1, r1, #44								\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	subs r2, r2, #44							\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
-            "	stmia r1!, {r0, r2-r7}							\n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "	stmia r2!, {r0, r1, r3-r7}					\n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
            "	mov r4, r8									\n"/* r4 = r8. */
            "	mov r5, r9									\n"/* r5 = r9. */
            "	mov r6, r10									\n"/* r6 = r10. */
            "	mov r7, r11									\n"/* r7 = r11. */
-            "	stmia r1!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+            "	stmia r2!, {r4-r7}							\n"/* Store the high registers that are not saved automatically. */
        #endif /* configENABLE_MPU */
        "													\n"
        " select_next_task:									\n"
@ -297,96 +299,100 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
        "	bl vTaskSwitchContext							\n"
        "	cpsie i											\n"
        "													\n"
-        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
-        "	ldr r1, [r3]									\n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+        "	ldr r2, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
        "													\n"
        #if ( configENABLE_MPU == 1 )
            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
-            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
            "	movs r5, #1									\n"/* r5 = 1. */
            "	bics r4, r5									\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Disable MPU. */
+            "	str r4, [r3]								\n"/* Disable MPU. */
            "												\n"
-            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-            "	ldr r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr r4, [r1]								\n"/* r4 = *r1 i.e. r4 = MAIR0. */
-            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	ldr r3, xMAIR0Const							\n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
-            "	str r4, [r2]									\n"/* Program MAIR0. */
+            "	str r4, [r3]								\n"/* Program MAIR0. */
-            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	ldr r4, xRNRConst							\n"/* r4 = 0xe000ed98 [Location of RNR]. */
-            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
            "	movs r5, #4									\n"/* r5 = 4. */
-            "	str  r5, [r2]									\n"/* Program RNR = 4. */
+            "	str  r5, [r4]								\n"/* Program RNR = 4. */
-            "	ldmia r3!, {r6,r7}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read first set of RBAR/RLAR from TCB. */
-            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
-            "	stmia r4!, {r6,r7}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	stmia r3!, {r6,r7}							\n"/* Write first set of RBAR/RLAR registers. */
            "	movs r5, #5									\n"/* r5 = 5. */
-            "	str  r5, [r2]									\n"/* Program RNR = 5. */
+            "	str  r5, [r4]								\n"/* Program RNR = 5. */
-            "	ldmia r3!, {r6,r7}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read second set of RBAR/RLAR from TCB. */
-            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
-            "	stmia r4!, {r6,r7}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	stmia r3!, {r6,r7}							\n"/* Write second set of RBAR/RLAR registers. */
            "	movs r5, #6									\n"/* r5 = 6. */
-            "	str  r5, [r2]									\n"/* Program RNR = 6. */
+            "	str  r5, [r4]								\n"/* Program RNR = 6. */
-            "	ldmia r3!, {r6,r7}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read third set of RBAR/RLAR from TCB. */
-            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
-            "	stmia r4!, {r6,r7}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	stmia r3!, {r6,r7}							\n"/* Write third set of RBAR/RLAR registers. */
            "	movs r5, #7									\n"/* r5 = 7. */
-            "	str  r5, [r2]									\n"/* Program RNR = 7. */
+            "	str  r5, [r4]								\n"/* Program RNR = 7. */
-            "	ldmia r3!, {r6,r7}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read fourth set of RBAR/RLAR from TCB. */
-            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
-            "	stmia r4!, {r6,r7}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "	stmia r3!, {r6,r7}							\n"/* Write fourth set of RBAR/RLAR registers. */
            "												\n"
-            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
            "	movs r5, #1									\n"/* r5 = 1. */
            "	orrs r4, r5									\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	str r4, [r3]								\n"/* Enable MPU. */
            "	dsb											\n"/* Force memory writes before continuing. */
        #endif /* configENABLE_MPU */
        "													\n"
        #if ( configENABLE_MPU == 1 )
-            "	ldmia r1!, {r0, r2-r4}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	ldmia r2!, {r0, r1, r3, r4}					\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
-            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
            "	msr control, r3								\n"/* Restore the CONTROL register value for the task. */
            "	mov lr, r4									\n"/* LR = r4. */
-            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
-            "	push {r1,r4}									\n"
+             "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
-            "	pop {r1,r4}										\n"
+            "	push {r2, r4}								\n"
            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
            "	pop {r2, r4}								\n"
            "	mov lr, r4									\n"/* LR = r4. */
-            "	lsls r2, r4, #25								\n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
            "	bx lr										\n"
        #else /* configENABLE_MPU */
-            "	ldmia r1!, {r0, r2-r3}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+            "	ldmia r2!, {r0, r1, r4}						\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
-            "	mov lr, r3										\n"/* LR = r3. */
+            "	mov lr, r4									\n"/* LR = r4. */
-            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
-            "	push {r1,r3}									\n"
+            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
-            "	pop {r1,r3}										\n"
+            "	push {r2, r4}								\n"
-            "	mov lr, r3										\n"/* LR = r3. */
+            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	pop {r2, r4}								\n"
-            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	mov lr, r4									\n"/* LR = r4. */
-            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
            "	bx lr										\n"
        #endif /* configENABLE_MPU */
        "													\n"
        " restore_ns_context:								\n"
-        "	adds r1, r1, #16								\n"/* Move to the high registers. */
+        "	adds r2, r2, #16								\n"/* Move to the high registers. */
-        "	ldmia r1!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+        "	ldmia r2!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
        "	mov r8, r4										\n"/* r8 = r4. */
        "	mov r9, r5										\n"/* r9 = r5. */
        "	mov r10, r6										\n"/* r10 = r6. */
        "	mov r11, r7										\n"/* r11 = r7. */
-        "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+        "	msr psp, r2										\n"/* Remember the new top of stack for the task. */
-        "	subs r1, r1, #32								\n"/* Go back to the low registers. */
+        "	subs r2, r2, #32								\n"/* Go back to the low registers. */
-        "	ldmia r1!, {r4-r7}								\n"/* Restore the low registers that are not automatically restored. */
+        "	ldmia r2!, {r4-r7}								\n"/* Restore the low registers that are not automatically restored. */
        "	bx lr											\n"
        "													\n"
        "	.align 4										\n"
@ -439,10 +445,10 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
 {
    __asm volatile
    (
-        "	ldr r1, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r2, [r0]									\n"/* The first item in the TCB is the top of the stack. */
-        "	ldr r0, [r1]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	ldr r1, [r2]									\n"/* The first item on the stack is the task's xSecureContext. */
-        "	cmp r0, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	cmp r1, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
-        "	beq free_secure_context							\n"
+        "	bne free_secure_context							\n"/* Branch if r1 != 0. */
        "	bx lr											\n"/* There is no secure context (xSecureContext is NULL). */
        " free_secure_context:								\n"
        "	svc %0											\n"/* Secure context is freed in the supervisor call. */
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -216,62 +216,65 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
        "	.extern SecureContext_SaveContext				\n"
        "	.extern SecureContext_LoadContext				\n"
        "													\n"
-        "	mrs r1, psp										\n"/* Read PSP in r1. */
+        "	ldr r3, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r3]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "	ldr r0, [r2]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
        "	mrs r2, psp										\n"/* Read PSP in r2. */
        "													\n"
        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
        "	push {r0-r2, r14}								\n"
-        "	bl SecureContext_SaveContext					\n"
+        "	bl SecureContext_SaveContext					\n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
        "	pop {r0-r3}										\n"/* LR is now in r3. */
        "	mov lr, r3										\n"/* LR = r3. */
-        "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	lsls r1, r3, #25								\n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
        "													\n"
        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB.*/
        #if ( configENABLE_MPU == 1 )
-            "	subs r1, r1, #16								\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	subs r2, r2, #16							\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mrs r3, control								\n"/* r3 = CONTROL. */
            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
-            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
        #else /* configENABLE_MPU */
-            "	subs r1, r1, #12								\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	subs r2, r2, #12							\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
-            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
        #endif /* configENABLE_MPU */
        "	b select_next_task								\n"
        "													\n"
        " save_ns_context:									\n"
        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
        #if ( configENABLE_FPU == 1 )
            "	tst lr, #0x10								\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
            "	it eq										\n"
-            "	vstmdbeq r1!, {s16-s31}							\n"/* Store the FPU registers which are not saved automatically. */
+            "	vstmdbeq r2!, {s16-s31}						\n"/* Store the FPU registers which are not saved automatically. */
        #endif /* configENABLE_FPU */
        #if ( configENABLE_MPU == 1 )
-            "	subs r1, r1, #48								\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	subs r2, r2, #48							\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	adds r1, r1, #16								\n"/* r1 = r1 + 16. */
+            "	adds r2, r2, #16							\n"/* r2 = r2 + 16. */
-            "	stm r1, {r4-r11}								\n"/* Store the registers that are not saved automatically. */
+            "	stm r2, {r4-r11}							\n"/* Store the registers that are not saved automatically. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mrs r3, control								\n"/* r3 = CONTROL. */
            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
-            "	subs r1, r1, #16								\n"/* r1 = r1 - 16. */
+            "	subs r2, r2, #16							\n"/* r2 = r2 - 16. */
-            "	stm r1, {r0, r2-r4}								\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
        #else /* configENABLE_MPU */
-            "	subs r1, r1, #44								\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	subs r2, r2, #44							\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
-            "	adds r1, r1, #12								\n"/* r1 = r1 + 12. */
+            "	adds r2, r2, #12							\n"/* r2 = r2 + 12. */
-            "	stm r1, {r4-r11}								\n"/* Store the registers that are not saved automatically. */
+            "	stm r2, {r4-r11}							\n"/* Store the registers that are not saved automatically. */
-            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
-            "	subs r1, r1, #12								\n"/* r1 = r1 - 12. */
+            "	subs r2, r2, #12							\n"/* r2 = r2 - 12. */
-            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
        #endif /* configENABLE_MPU */
        "													\n"
        " select_next_task:									\n"
@ -283,77 +286,81 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
        "	mov r0, #0										\n"/* r0 = 0. */
        "	msr basepri, r0									\n"/* Enable interrupts. */
        "													\n"
-        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "	ldr r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
-        "	ldr r1, [r3]									\n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+        "	ldr r2, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
        "													\n"
        #if ( configENABLE_MPU == 1 )
            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
-            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
            "	bic r4, #1									\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Disable MPU. */
+            "	str r4, [r3]								\n"/* Disable MPU. */
            "												\n"
-            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-            "	ldr r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr r4, [r1]								\n"/* r4 = *r1 i.e. r4 = MAIR0. */
-            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	ldr r3, xMAIR0Const							\n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
-            "	str r4, [r2]									\n"/* Program MAIR0. */
+            "	str r4, [r3]								\n"/* Program MAIR0. */
-            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	ldr r3, xRNRConst							\n"/* r3 = 0xe000ed98 [Location of RNR]. */
            "	movs r4, #4									\n"/* r4 = 4. */
-            "	str r4, [r2]									\n"/* Program RNR = 4. */
+            "	str r4, [r3]								\n"/* Program RNR = 4. */
-            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-            "	ldr  r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldr r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
-            "	ldmia r3!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	ldmia r1!, {r4-r11}							\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
-            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "	stmia r3!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
            "												\n"
-            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
            "	orr r4, #1									\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	str r4, [r3]								\n"/* Enable MPU. */
            "	dsb											\n"/* Force memory writes before continuing. */
        #endif /* configENABLE_MPU */
        "													\n"
        #if ( configENABLE_MPU == 1 )
-            "	ldmia r1!, {r0, r2-r4}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	ldmia r2!, {r0, r1, r3, r4}					\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
-            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
            "	msr control, r3								\n"/* Restore the CONTROL register value for the task. */
            "	mov lr, r4									\n"/* LR = r4. */
-            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
-            "	push {r1,r4}									\n"
+            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
-            "	pop {r1,r4}										\n"
+            "	push {r2, r4}								\n"
            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
            "	pop {r2, r4}								\n"
            "	mov lr, r4									\n"/* LR = r4. */
-            "	lsls r2, r4, #25								\n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
            "	bx lr										\n"
        #else /* configENABLE_MPU */
-            "	ldmia r1!, {r0, r2-r3}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+            "	ldmia r2!, {r0, r1, r4}						\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
-            "	mov lr, r3										\n"/* LR = r3. */
+            "	mov lr, r4									\n"/* LR = r4. */
-            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
-            "	push {r1,r3}									\n"
+            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
-            "	pop {r1,r3}										\n"
+            "	push {r2, r4}								\n"
-            "	mov lr, r3										\n"/* LR = r3. */
+            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-            "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	pop {r2, r4}								\n"
-            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	mov lr, r4									\n"/* LR = r4. */
-            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
            "	bx lr										\n"
        #endif /* configENABLE_MPU */
        "													\n"
        " restore_ns_context:								\n"
-        "	ldmia r1!, {r4-r11}								\n"/* Restore the registers that are not automatically restored. */
+        "	ldmia r2!, {r4-r11}								\n"/* Restore the registers that are not automatically restored. */
        #if ( configENABLE_FPU == 1 )
            "	tst lr, #0x10								\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
            "	it eq										\n"
-            "	vldmiaeq r1!, {s16-s31}							\n"/* Restore the FPU registers which are not restored automatically. */
+            "	vldmiaeq r2!, {s16-s31}						\n"/* Restore the FPU registers which are not restored automatically. */
        #endif /* configENABLE_FPU */
-        "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+        "	msr psp, r2										\n"/* Remember the new top of stack for the task. */
        "	bx lr											\n"
        "													\n"
        "	.align 4										\n"
@ -402,9 +409,9 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
 {
    __asm volatile
    (
-        "	ldr r1, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r2, [r0]									\n"/* The first item in the TCB is the top of the stack. */
-        "	ldr r0, [r1]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	ldr r1, [r2]									\n"/* The first item on the stack is the task's xSecureContext. */
-        "	cmp r0, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	cmp r1, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
        "	it ne											\n"
        "	svcne %0										\n"/* Secure context is freed in the supervisor call. */
        "	bx lr											\n"/* Return. */
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -25,6 +25,13 @@
 * 1 tab == 4 spaces!
 */
 /* Including FreeRTOSConfig.h here will cause build errors if the header file
 contains code not understood by the assembler - for example the 'extern' keyword.
 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
 the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 	EXTERN pxCurrentTCB
 	EXTERN xSecureContext
 	EXTERN vTaskSwitchContext
@ -193,64 +200,66 @@ vClearInterruptMask:
 /*-----------------------------------------------------------*/
 PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
+	ldr r3, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r3]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 	ldr r1, [r3]							/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 	mrs r2, psp								/* Read PSP in r2. */
 	cbz r0, save_ns_context					/* No secure context to save. */
 	push {r0-r2, r14}
-	bl SecureContext_SaveContext
+	bl SecureContext_SaveContext			/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 	pop {r0-r3}								/* LR is now in r3. */
 	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	lsls r1, r3, #25						/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
+	ldr r1, [r3]							/* Read pxCurrentTCB. */
 #if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	subs r2, r2, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mrs r3, control							/* r3 = CONTROL. */
 	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	stmia r2!, {r0, r1, r3, r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 #else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	subs r2, r2, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+	stmia r2!, {r0, r1, r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
 #endif /* configENABLE_MPU */
 	b select_next_task
 	save_ns_context:
 		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
 	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		subs r2, r2, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
+		adds r2, r2, #16					/* r2 = r2 + 16. */
-		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		stmia r2!, {r4-r7}					/* Store the low registers that are not saved automatically. */
 		mov r4, r8							/* r4 = r8. */
 		mov r5, r9							/* r5 = r9. */
 		mov r6, r10							/* r6 = r10. */
 		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		stmia r2!, {r4-r7}					/* Store the high registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mrs r3, control						/* r3 = CONTROL. */
 		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #48					/* r1 = r1 - 48. */
+		subs r2, r2, #48					/* r2 = r2 - 48. */
-		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+		stmia r2!, {r0, r1, r3, r4}			/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		subs r2, r2, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		stmia r2!, {r0, r1, r3-r7}			/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
 		mov r4, r8							/* r4 = r8. */
 		mov r5, r9							/* r5 = r9. */
 		mov r6, r10							/* r6 = r10. */
 		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		stmia r2!, {r4-r7}					/* Store the high registers that are not saved automatically. */
 	#endif /* configENABLE_MPU */
 	select_next_task:
@ -258,96 +267,100 @@ PendSV_Handler:
 		bl vTaskSwitchContext
 		cpsie i
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+		ldr r2, [r1]						/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 	#if ( configENABLE_MPU == 1 )
 		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		movs r5, #1							/* r5 = 1. */
 		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
+		str r4, [r3]						/* Disable MPU. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r4, [r1]						/* r4 = *r1 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		ldr r3, =0xe000edc0					/* r3 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
+		str r4, [r3]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		ldr r4, =0xe000ed98					/* r4 = 0xe000ed98 [Location of RNR]. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
 		movs r5, #4							/* r5 = 4. */
-		str  r5, [r2]						/* Program RNR = 4. */
+		str  r5, [r4]						/* Program RNR = 4. */
-		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldmia r1!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		stmia r3!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
 		movs r5, #5							/* r5 = 5. */
-		str  r5, [r2]						/* Program RNR = 5. */
+		str  r5, [r4]						/* Program RNR = 5. */
-		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldmia r1!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		stmia r3!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
 		movs r5, #6							/* r5 = 6. */
-		str  r5, [r2]						/* Program RNR = 6. */
+		str  r5, [r4]						/* Program RNR = 6. */
-		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldmia r1!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		stmia r3!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
 		movs r5, #7							/* r5 = 7. */
-		str  r5, [r2]						/* Program RNR = 7. */
+		str  r5, [r4]						/* Program RNR = 7. */
-		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldmia r1!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+		stmia r3!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		movs r5, #1							/* r5 = 1. */
 		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
+		str r4, [r3]						/* Enable MPU. */
 		dsb									/* Force memory writes before continuing. */
 	#endif /* configENABLE_MPU */
 	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		ldmia r2!, {r0, r1, r3, r4}			/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
 		msr control, r3						/* Restore the CONTROL register value for the task. */
 		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		bl SecureContext_LoadContext		/* Restore the secure context. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		pop {r1,r4}
+		push {r2, r4}
 		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 		pop {r2, r4}
 		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		ldmia r2!, {r0, r1, r4}				/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
+		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		bl SecureContext_LoadContext		/* Restore the secure context. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		pop {r1,r3}
+		push {r2, r4}
-		mov lr, r3							/* LR = r3. */
+		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		pop {r2, r4}
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		mov lr, r4							/* LR = r4. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#endif /* configENABLE_MPU */
 	restore_ns_context:
-		adds r1, r1, #16					/* Move to the high registers. */
+		adds r2, r2, #16					/* Move to the high registers. */
-		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		ldmia r2!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
 		mov r8, r4							/* r8 = r4. */
 		mov r9, r5							/* r9 = r5. */
 		mov r10, r6							/* r10 = r6. */
 		mov r11, r7							/* r11 = r7. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
-		subs r1, r1, #32					/* Go back to the low registers. */
+		subs r2, r2, #32					/* Go back to the low registers. */
-		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		ldmia r2!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
 		bx lr
 /*-----------------------------------------------------------*/
@ -364,10 +377,10 @@ SVC_Handler:
 /*-----------------------------------------------------------*/
 vPortFreeSecureContext:
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r2, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	ldr r1, [r2]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	cmp r1, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	beq free_secure_context
+	bne free_secure_context					/* Branch if r1 != 0. */
 	bx lr									/* There is no secure context (xSecureContext is NULL). */
 	free_secure_context:
 		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -24,6 +24,12 @@
 *
 * 1 tab == 4 spaces!
 */
 /* Including FreeRTOSConfig.h here will cause build errors if the header file
 contains code not understood by the assembler - for example the 'extern' keyword.
 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
 the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 	EXTERN pxCurrentTCB
 	EXTERN vTaskSwitchContext
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -183,62 +183,65 @@ vClearInterruptMask:
 /*-----------------------------------------------------------*/
 PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
+	ldr r3, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r3]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 	ldr r1, [r3]							/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 	mrs r2, psp								/* Read PSP in r2. */
 	cbz r0, save_ns_context					/* No secure context to save. */
 	push {r0-r2, r14}
-	bl SecureContext_SaveContext
+	bl SecureContext_SaveContext			/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 	pop {r0-r3}								/* LR is now in r3. */
 	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	lsls r1, r3, #25						/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
+	ldr r1, [r3]							/* Read pxCurrentTCB. */
 #if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	subs r2, r2, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mrs r3, control							/* r3 = CONTROL. */
 	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	stmia r2!, {r0, r1, r3, r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 #else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	subs r2, r2, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+	stmia r2!, {r0, r1, r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
 #endif /* configENABLE_MPU */
 	b select_next_task
 	save_ns_context:
 		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
 	#if ( configENABLE_FPU == 1 )
 		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
 		it eq
-		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
+		vstmdbeq r2!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
 	#endif /* configENABLE_FPU */
 	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		subs r2, r2, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
+		adds r2, r2, #16					/* r2 = r2 + 16. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		stm r2, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mrs r3, control						/* r3 = CONTROL. */
 		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #16					/* r1 = r1 - 16. */
+		subs r2, r2, #16					/* r2 = r2 - 16. */
-		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+		stmia r2!, {r0, r1, r3, r4}			/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		subs r2, r2, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #12					/* r1 = r1 + 12. */
+		adds r2, r2, #12					/* r2 = r2 + 12. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		stm r2, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r1, r1, #12					/* r1 = r1 - 12. */
+		subs r2, r2, #12					/* r2 = r2 - 12. */
-		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+		stmia r2!, {r0, r1, r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
 	#endif /* configENABLE_MPU */
 	select_next_task:
@ -250,77 +253,81 @@ PendSV_Handler:
 		mov r0, #0							/* r0 = 0. */
 		msr basepri, r0						/* Enable interrupts. */
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+		ldr r2, [r1]						/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 	#if ( configENABLE_MPU == 1 )
 		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
+		str r4, [r3]						/* Disable MPU. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r4, [r1]						/* r4 = *r1 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		ldr r3, =0xe000edc0					/* r3 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
+		str r4, [r3]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		ldr r3, =0xe000ed98					/* r3 = 0xe000ed98 [Location of RNR]. */
 		movs r4, #4							/* r4 = 4. */
-		str r4, [r2]						/* Program RNR = 4. */
+		str r4, [r3]						/* Program RNR = 4. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		ldmia r1!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+		stmia r3!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
+		str r4, [r3]						/* Enable MPU. */
 		dsb									/* Force memory writes before continuing. */
 	#endif /* configENABLE_MPU */
 	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		ldmia r2!, {r0, r1, r3, r4}			/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
 		msr control, r3						/* Restore the CONTROL register value for the task. */
 		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		bl SecureContext_LoadContext		/* Restore the secure context. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		pop {r1,r4}
+		push {r2, r4}
 		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 		pop {r2, r4}
 		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		ldmia r2!, {r0, r1, r4}				/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
+		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		bl SecureContext_LoadContext		/* Restore the secure context. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
-		pop {r1,r3}
+		push {r2, r4}
-		mov lr, r3							/* LR = r3. */
+		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		pop {r2, r4}
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		mov lr, r4							/* LR = r4. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#endif /* configENABLE_MPU */
 	restore_ns_context:
-		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+		ldmia r2!, {r4-r11}					/* Restore the registers that are not automatically restored. */
 	#if ( configENABLE_FPU == 1 )
 		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
 		it eq
-		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
+		vldmiaeq r2!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
 	#endif /* configENABLE_FPU */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 /*-----------------------------------------------------------*/
@ -334,9 +341,9 @@ SVC_Handler:
 vPortFreeSecureContext:
 	/* r0 = uint32_t *pulTCB. */
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r2, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	ldr r1, [r2]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	cmp r1, #0								/* Raise svc if task's xSecureContext is not NULL. */
 	it ne
 	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
 	bx lr									/* Return. */
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/non_secure/portasm.h
+++ b/portable/ARMv8M/non_secure/portasm.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
+++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -35,55 +35,62 @@
    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
 #endif
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
 void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
 void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
 {
-    /* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    __asm volatile
    (
        " .syntax unified                   \n"
        "                                   \n"
-        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
-        "	cbz r1, load_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        " cbz r1, load_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
-        "	ldmia r0!, {r1, r2}						\n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+        " ldmia r0!, {r1, r2}               \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
        "                                   \n"
        #if ( configENABLE_MPU == 1 )
-            "	ldmia r1!, {r3}							\n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            " ldmia r1!, {r3}               \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-            "	msr control, r3							\n"/* CONTROL = r3. */
+            " msr control, r3               \n" /* CONTROL = r3. */
        #endif /* configENABLE_MPU */
-        "	msr psplim, r2							\n"/* PSPLIM = r2. */
+        "                                   \n"
-        "	msr psp, r1								\n"/* PSP = r1. */
+        " msr psplim, r2                    \n" /* PSPLIM = r2. */
        " msr psp, r1                       \n" /* PSP = r1. */
        "                                   \n"
        " load_ctx_therad_mode:             \n"
-        "	nop										\n"
+        "    bx lr                          \n"
        "                                   \n"
        ::: "r0", "r1", "r2"
    );
 }
 /*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
 {
-    /* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    __asm volatile
    (
        " .syntax unified                   \n"
        "                                   \n"
-        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
-        "	cbz r1, save_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        " cbz r1, save_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
-        "	mrs r1, psp								\n"/* r1 = PSP. */
+        " mrs r1, psp                       \n" /* r1 = PSP. */
        "                                   \n"
        #if ( configENABLE_MPU == 1 )
-            "	mrs r2, control							\n"/* r2 = CONTROL. */
+            " mrs r2, control               \n" /* r2 = CONTROL. */
-            "	subs r1, r1, #4							\n"/* Make space for the CONTROL value on the stack. */
+            " subs r1, r1, #4               \n" /* Make space for the CONTROL value on the stack. */
-            "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+            " str r1, [r0]                  \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
-            "	stmia r1!, {r2}							\n"/* Store CONTROL value on the stack. */
+            " stmia r1!, {r2}               \n" /* Store CONTROL value on the stack. */
        #else /* configENABLE_MPU */
-            "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+            " str r1, [r0]                  \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
        #endif /* configENABLE_MPU */
-        "	movs r1, %0								\n"/* r1 = securecontextNO_STACK. */
+        "                                   \n"
-        "	msr psplim, r1							\n"/* PSPLIM = securecontextNO_STACK. */
+        " movs r1, %0                       \n" /* r1 = securecontextNO_STACK. */
-        "	msr psp, r1								\n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        " msr psplim, r1                    \n" /* PSPLIM = securecontextNO_STACK. */
        " msr psp, r1                       \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
        "                                   \n"
        " save_ctx_therad_mode:             \n"
-        "	nop										\n"
+        "   bx lr                           \n"
        "                                   \n"
        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
    );
--- a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
+++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -31,56 +31,64 @@
 /* Secure port macros. */
 #include "secure_port_macros.h"
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
 void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
 void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
 {
-    /* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    __asm volatile
    (
        " .syntax unified                   \n"
        "                                   \n"
-        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
-        "	cbz r1, load_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        " cbz r1, load_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
-        "	ldmia r0!, {r1, r2}						\n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+        " ldmia r0!, {r1, r2}               \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
        "                                   \n"
        #if ( configENABLE_MPU == 1 )
-            "	ldmia r1!, {r3}							\n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            " ldmia r1!, {r3}               \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-            "	msr control, r3							\n"/* CONTROL = r3. */
+            " msr control, r3               \n" /* CONTROL = r3. */
        #endif /* configENABLE_MPU */
-        "	msr psplim, r2							\n"/* PSPLIM = r2. */
+        "                                   \n"
-        "	msr psp, r1								\n"/* PSP = r1. */
+        " msr psplim, r2                    \n" /* PSPLIM = r2. */
        " msr psp, r1                       \n" /* PSP = r1. */
        "                                   \n"
        " load_ctx_therad_mode:             \n"
-        "	nop										\n"
+        "    bx lr                          \n"
        "                                   \n"
        ::: "r0", "r1", "r2"
    );
 }
 /*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
 {
-    /* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    __asm volatile
    (
        " .syntax unified                   \n"
        "                                   \n"
-        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
-        "	cbz r1, save_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        " cbz r1, save_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
-        "	mrs r1, psp								\n"/* r1 = PSP. */
+        " mrs r1, psp                       \n" /* r1 = PSP. */
        "                                   \n"
        #if ( configENABLE_FPU == 1 )
-            "	vstmdb r1!, {s0}						\n"/* Trigger the defferred stacking of FPU registers. */
+            " vstmdb r1!, {s0}              \n" /* Trigger the defferred stacking of FPU registers. */
-            "	vldmia r1!, {s0}						\n"/* Nullify the effect of the pervious statement. */
+            " vldmia r1!, {s0}              \n" /* Nullify the effect of the pervious statement. */
        #endif /* configENABLE_FPU */
        "                                   \n"
        #if ( configENABLE_MPU == 1 )
-            "	mrs r2, control							\n"/* r2 = CONTROL. */
+            " mrs r2, control               \n" /* r2 = CONTROL. */
-            "	stmdb r1!, {r2}							\n"/* Store CONTROL value on the stack. */
+            " stmdb r1!, {r2}               \n" /* Store CONTROL value on the stack. */
        #endif /* configENABLE_MPU */
-        "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+        "                                   \n"
-        "	movs r1, %0								\n"/* r1 = securecontextNO_STACK. */
+        " str r1, [r0]                      \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
-        "	msr psplim, r1							\n"/* PSPLIM = securecontextNO_STACK. */
+        " movs r1, %0                       \n" /* r1 = securecontextNO_STACK. */
-        "	msr psp, r1								\n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        " msr psplim, r1                    \n" /* PSPLIM = securecontextNO_STACK. */
        " msr psp, r1                       \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
        "                                   \n"
        " save_ctx_therad_mode:             \n"
-        "	nop										\n"
+        "    bx lr                          \n"
        "                                   \n"
        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
    );
--- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
+++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
@ -1,48 +0,0 @@
 /*
 * FreeRTOS Kernel V10.4.3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 * 1 tab == 4 spaces!
 */
 /* Secure context includes. */
 #include "secure_context.h"
 /* Secure port macros. */
 #include "secure_port_macros.h"
 /* Functions implemented in assembler file. */
 extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
 extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
 secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
 {
    SecureContext_LoadContextAsm( xSecureContextHandle );
 }
 /*-----------------------------------------------------------*/
 secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
 {
    SecureContext_SaveContextAsm( xSecureContextHandle );
 }
 /*-----------------------------------------------------------*/
--- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
+++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -28,6 +28,13 @@
    SECTION .text:CODE:NOROOT(2)
    THUMB
 /* Including FreeRTOSConfig.h here will cause build errors if the header file
 contains code not understood by the assembler - for example the 'extern' keyword.
 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
 the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
    PUBLIC SecureContext_LoadContextAsm
    PUBLIC SecureContext_SaveContextAsm
@ -37,14 +44,16 @@
 /*-----------------------------------------------------------*/
 SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    mrs r1, ipsr                    /* r1 = IPSR. */
    cbz r1, load_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+    ldmia r0!, {r1, r2}             /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
 #if ( configENABLE_MPU == 1 )
    ldmia r1!, {r3}                 /* Read CONTROL register value from task's stack. r3 = CONTROL. */
    msr control, r3                 /* CONTROL = r3. */
 #endif /* configENABLE_MPU */
    msr psplim, r2                  /* PSPLIM = r2. */
    msr psp, r1                     /* PSP = r1. */
@ -53,18 +62,20 @@ SecureContext_LoadContextAsm:
 /*-----------------------------------------------------------*/
 SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    mrs r1, ipsr                    /* r1 = IPSR. */
    cbz r1, save_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */
    mrs r1, psp                     /* r1 = PSP. */
 #if ( configENABLE_MPU == 1 )
    mrs r2, control                 /* r2 = CONTROL. */
    subs r1, r1, #4                 /* Make space for the CONTROL value on the stack. */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
    stmia r1!, {r2}                 /* Store CONTROL value on the stack. */
 #else /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
 #endif /* configENABLE_MPU */
    movs r1, #0                     /* r1 = securecontextNO_STACK. */
    msr psplim, r1                  /* PSPLIM = securecontextNO_STACK. */
    msr psp, r1                     /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
--- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
+++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
@ -1,48 +0,0 @@
 /*
 * FreeRTOS Kernel V10.4.3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 * 1 tab == 4 spaces!
 */
 /* Secure context includes. */
 #include "secure_context.h"
 /* Secure port macros. */
 #include "secure_port_macros.h"
 /* Functions implemented in assembler file. */
 extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
 extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
 secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
 {
    SecureContext_LoadContextAsm( xSecureContextHandle );
 }
 /*-----------------------------------------------------------*/
 secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
 {
    SecureContext_SaveContextAsm( xSecureContextHandle );
 }
 /*-----------------------------------------------------------*/
--- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
+++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -28,19 +28,28 @@
    SECTION .text:CODE:NOROOT(2)
    THUMB
 /* Including FreeRTOSConfig.h here will cause build errors if the header file
 contains code not understood by the assembler - for example the 'extern' keyword.
 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
 the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
    PUBLIC SecureContext_LoadContextAsm
    PUBLIC SecureContext_SaveContextAsm
 /*-----------------------------------------------------------*/
 SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    mrs r1, ipsr                        /* r1 = IPSR. */
    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
 #if ( configENABLE_MPU == 1 )
    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */
    msr control, r3                     /* CONTROL = r3. */
 #endif /* configENABLE_MPU */
    msr psplim, r2                      /* PSPLIM = r2. */
    msr psp, r1                         /* PSP = r1. */
@ -49,19 +58,22 @@ SecureContext_LoadContextAsm:
 /*-----------------------------------------------------------*/
 SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
+    /* pxSecureContext value is in r0. */
    mrs r1, ipsr                        /* r1 = IPSR. */
    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */
    mrs r1, psp                         /* r1 = PSP. */
 #if ( configENABLE_FPU == 1 )
    vstmdb r1!, {s0}                    /* Trigger the defferred stacking of FPU registers. */
    vldmia r1!, {s0}                    /* Nullify the effect of the pervious statement. */
 #endif /* configENABLE_FPU */
 #if ( configENABLE_MPU == 1 )
    mrs r2, control                     /* r2 = CONTROL. */
    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */
 #endif /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+
    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
    movs r1, #0                         /* r1 = securecontextNO_STACK. */
    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */
    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
--- a/portable/ARMv8M/secure/context/secure_context.c
+++ b/portable/ARMv8M/secure/context/secure_context.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -49,37 +49,119 @@
 * Bit[1] - 1 --> Thread mode uses PSP.
 */
 #define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
 /**
 * @brief Size of stack seal values in bytes.
 */
 #define securecontextSTACK_SEAL_SIZE               8
 /**
 * @brief Stack seal value as recommended by ARM.
 */
 #define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5
 /**
 * @brief Maximum number of secure contexts.
 */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
    #define secureconfigMAX_SECURE_CONTEXTS        8UL
 #endif
 /*-----------------------------------------------------------*/
 /**
- * @brief Structure to represent secure context.
+ * @brief Pre-allocated array of secure contexts.
 *
 * @note Since stack grows down, pucStackStart is the highest address while
 * pucStackLimit is the first addess of the allocated memory.
 */
-typedef struct SecureContext
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
 /*-----------------------------------------------------------*/
 /**
 * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
 *
 * This function ensures that only one secure context is allocated for a task.
 *
 * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
 *
 * @return Index of a free secure context in the xSecureContexts array.
 */
 static uint32_t ulGetSecureContext( void * pvTaskHandle );
 /**
 * @brief Return the secure context to the secure context pool (xSecureContexts).
 *
 * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
 */
 static void vReturnSecureContext( uint32_t ulSecureContextIndex );
 /* These are implemented in assembly. */
 extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
 extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
 /*-----------------------------------------------------------*/
 static uint32_t ulGetSecureContext( void * pvTaskHandle )
 {
-    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    /* Start with invalid index. */
-    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
-    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+
-} SecureContext_t;
+    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
    {
        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
            ( xSecureContexts[ i ].pucStackStart == NULL ) &&
            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
        {
            ulSecureContextIndex = i;
        }
        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
        {
            /* A task can only have one secure context. Do not allocate a second
             * context for the same task. */
            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
            break;
        }
    }
    return ulSecureContextIndex;
 }
 /*-----------------------------------------------------------*/
 static void vReturnSecureContext( uint32_t ulSecureContextIndex )
 {
    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
 }
 /*-----------------------------------------------------------*/
 secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 {
-    uint32_t ulIPSR;
+    uint32_t ulIPSR, i;
    static uint32_t ulSecureContextsInitialized = 0;
    /* Read the Interrupt Program Status Register (IPSR) value. */
    secureportREAD_IPSR( ulIPSR );
    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
     * when the processor is running in the Thread Mode. */
-    if( ulIPSR != 0 )
+    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
    {
        /* Ensure to initialize secure contexts only once. */
        ulSecureContextsInitialized = 1;
        /* No stack for thread mode until a task's context is loaded. */
        secureportSET_PSPLIM( securecontextNO_STACK );
        secureportSET_PSP( securecontextNO_STACK );
        /* Initialize all secure contexts. */
        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
        {
            xSecureContexts[ i ].pucCurrentStackPointer = NULL;
            xSecureContexts[ i ].pucStackLimit = NULL;
            xSecureContexts[ i ].pucStackStart = NULL;
            xSecureContexts[ i ].pvTaskHandle = NULL;
        }
        #if ( configENABLE_MPU == 1 )
            {
                /* Configure thread mode to use PSP and to be unprivileged. */
@ -87,7 +169,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
            }
        #else /* configENABLE_MPU */
            {
-                /* Configure thread mode to use PSP and to be privileged.. */
+                /* Configure thread mode to use PSP and to be privileged. */
                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
            }
        #endif /* configENABLE_MPU */
@ -97,54 +179,68 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 #if ( configENABLE_MPU == 1 )
    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
-                                                                                       uint32_t ulIsTaskPrivileged )
+                                                                                       uint32_t ulIsTaskPrivileged,
                                                                                       void * pvTaskHandle )
 #else /* configENABLE_MPU */
-    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
                                                                                       void * pvTaskHandle )
 #endif /* configENABLE_MPU */
 {
    uint8_t * pucStackMemory = NULL;
-    uint32_t ulIPSR;
+    uint8_t * pucStackLimit;
-    SecureContextHandle_t xSecureContextHandle = NULL;
+    uint32_t ulIPSR, ulSecureContextIndex;
    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
    #if ( configENABLE_MPU == 1 )
        uint32_t * pulCurrentStackPointer = NULL;
    #endif /* configENABLE_MPU */
-    /* Read the Interrupt Program Status Register (IPSR) value. */
+    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
     * Register (PSPLIM) value. */
    secureportREAD_IPSR( ulIPSR );
    secureportREAD_PSPLIM( pucStackLimit );
    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-     * when the processor is running in the Thread Mode. */
+     * when the processor is running in the Thread Mode.
-    if( ulIPSR != 0 )
+     * Also do nothing, if a secure context us already loaded. PSPLIM is set to
     * securecontextNO_STACK when no secure context is loaded. */
    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
    {
-        /* Allocate the context structure. */
+        /* Ontain a free secure context. */
-        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
-        if( xSecureContextHandle != NULL )
+        /* Were we able to get a free context? */
        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
        {
            /* Allocate the stack space. */
-            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
            if( pucStackMemory != NULL )
            {
                /* Since stack grows down, the starting point will be the last
                 * location. Note that this location is next to the last
-                 * allocated byte because the hardware decrements the stack
+                 * allocated byte for stack (excluding the space for seal values)
-                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * because the hardware decrements the stack pointer before
-                 * operation will decrement the stack pointer to 0x1 and then
+                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * write at 0x1. */
+                 * decrement the stack pointer to 0x1 and then write at 0x1. */
-                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
                /* Seal the created secure process stack. */
                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
                /* The stack cannot go beyond this location. This value is
                 * programmed in the PSPLIM register on context switch.*/
-                xSecureContextHandle->pucStackLimit = pucStackMemory;
+                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
                #if ( configENABLE_MPU == 1 )
                    {
                        /* Store the correct CONTROL value for the task on the stack.
                         * This value is programmed in the CONTROL register on
                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
                        pulCurrentStackPointer--;
                        if( ulIsTaskPrivileged )
@ -158,22 +254,18 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                        /* Store the current stack pointer. This value is programmed in
                         * the PSP register on context switch. */
-                        xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
                    }
                #else /* configENABLE_MPU */
                    {
                        /* Current SP is set to the starting of the stack. This
                         * value programmed in the PSP register on context switch. */
-                        xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
                    }
                #endif /* configENABLE_MPU */
-            }
+
-            else
+                /* Ensure to never return 0 as a valid context handle. */
-            {
+                xSecureContextHandle = ulSecureContextIndex + 1UL;
                /* Free the context to avoid memory leak and make sure to return
                 * NULL to indicate failure. */
                vPortFree( xSecureContextHandle );
                xSecureContextHandle = NULL;
            }
        }
    }
@ -182,9 +274,9 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
 {
-    uint32_t ulIPSR;
+    uint32_t ulIPSR, ulSecureContextIndex;
    /* Read the Interrupt Program Status Register (IPSR) value. */
    secureportREAD_IPSR( ulIPSR );
@ -193,14 +285,66 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
     * when the processor is running in the Thread Mode. */
    if( ulIPSR != 0 )
    {
-        /* Ensure that valid parameters are passed. */
+        /* Only free if a valid context handle is passed. */
-        secureportASSERT( xSecureContextHandle != NULL );
+        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
        {
            ulSecureContextIndex = xSecureContextHandle - 1UL;
            /* Ensure that the secure context being deleted is associated with
             * the task. */
            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
            {
                /* Free the stack space. */
-        vPortFree( xSecureContextHandle->pucStackLimit );
+                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
-        /* Free the context itself. */
+                /* Return the secure context back to the free secure contexts pool. */
-        vPortFree( xSecureContextHandle );
+                vReturnSecureContext( ulSecureContextIndex );
            }
        }
    }
 }
 /*-----------------------------------------------------------*/
 secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
 {
    uint8_t * pucStackLimit;
    uint32_t ulSecureContextIndex;
    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
    {
        ulSecureContextIndex = xSecureContextHandle - 1UL;
        secureportREAD_PSPLIM( pucStackLimit );
        /* Ensure that no secure context is loaded and the task is loading it's
         * own context. */
        if( ( pucStackLimit == securecontextNO_STACK ) &&
            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
        {
            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
        }
    }
 }
 /*-----------------------------------------------------------*/
 secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
 {
    uint8_t * pucStackLimit;
    uint32_t ulSecureContextIndex;
    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
    {
        ulSecureContextIndex = xSecureContextHandle - 1UL;
        secureportREAD_PSPLIM( pucStackLimit );
        /* Ensure that task's context is loaded and the task is saving it's own
         * context. */
        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
        {
            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
        }
    }
 }
 /*-----------------------------------------------------------*/
--- a/portable/ARMv8M/secure/context/secure_context.h
+++ b/portable/ARMv8M/secure/context/secure_context.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -35,15 +35,35 @@
 #include "FreeRTOSConfig.h"
 /**
- * @brief PSP value when no task's context is loaded.
+ * @brief PSP value when no secure context is loaded.
 */
 #define securecontextNO_STACK               0x0
 /**
- * @brief Opaque handle.
+ * @brief Invalid context ID.
 */
-struct SecureContext;
+#define securecontextINVALID_CONTEXT_ID     0UL
-typedef struct SecureContext * SecureContextHandle_t;
+/*-----------------------------------------------------------*/
 /**
 * @brief Structure to represent a secure context.
 *
 * @note Since stack grows down, pucStackStart is the highest address while
 * pucStackLimit is the first address of the allocated memory.
 */
 typedef struct SecureContext
 {
    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
    uint8_t * pucStackStart;          /**< First location of the stack memory. */
    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */
 } SecureContext_t;
 /*-----------------------------------------------------------*/
 /**
 * @brief Opaque handle for a secure context.
 */
 typedef uint32_t SecureContextHandle_t;
 /*-----------------------------------------------------------*/
 /**
@ -71,9 +91,11 @@ void SecureContext_Init( void );
 */
 #if ( configENABLE_MPU == 1 )
    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
-                                                         uint32_t ulIsTaskPrivileged );
+                                                         uint32_t ulIsTaskPrivileged,
                                                         void * pvTaskHandle );
 #else /* configENABLE_MPU */
-    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
                                                         void * pvTaskHandle );
 #endif /* configENABLE_MPU */
 /**
@ -85,7 +107,7 @@ void SecureContext_Init( void );
 * @param[in] xSecureContextHandle Context handle corresponding to the
 * context to be freed.
 */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
 /**
 * @brief Loads the given context.
@ -96,7 +118,7 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
 * @param[in] xSecureContextHandle Context handle corresponding to the context
 * to be loaded.
 */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
 /**
 * @brief Saves the given context.
@ -107,6 +129,6 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
 * @param[in] xSecureContextHandle Context handle corresponding to the context
 * to be saved.
 */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
 #endif /* __SECURE_CONTEXT_H__ */
--- a/portable/ARMv8M/secure/heap/secure_heap.c
+++ b/portable/ARMv8M/secure/heap/secure_heap.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -37,7 +37,9 @@
 /**
 * @brief Total heap size.
 */
-#define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+#ifndef secureconfigTOTAL_HEAP_SIZE
    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
 #endif
 /* No test marker by default. */
 #ifndef mtCOVERAGE_TEST_MARKER
@ -446,9 +448,3 @@ size_t xPortGetMinimumEverFreeHeapSize( void )
    return xMinimumEverFreeBytesRemaining;
 }
 /*-----------------------------------------------------------*/
 void vPortInitialiseBlocks( void )
 {
    /* This just exists to keep the linker quiet. */
 }
 /*-----------------------------------------------------------*/
--- a/portable/ARMv8M/secure/heap/secure_heap.h
+++ b/portable/ARMv8M/secure/heap/secure_heap.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -48,4 +48,18 @@ void * pvPortMalloc( size_t xWantedSize );
 */
 void vPortFree( void * pv );
 /**
 * @brief Get the free heap size.
 *
 * @return Free heap size.
 */
 size_t xPortGetFreeHeapSize( void );
 /**
 * @brief Get the minimum ever free heap size.
 *
 * @return Minimum ever free heap size.
 */
 size_t xPortGetMinimumEverFreeHeapSize( void );
 #endif /* __SECURE_HEAP_H__ */
--- a/portable/ARMv8M/secure/init/secure_init.c
+++ b/portable/ARMv8M/secure/init/secure_init.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/secure/init/secure_init.h
+++ b/portable/ARMv8M/secure/init/secure_init.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/ARMv8M/secure/macros/secure_port_macros.h
+++ b/portable/ARMv8M/secure/macros/secure_port_macros.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
@ -67,6 +67,12 @@
 #define secureportSET_PSP( pucCurrentStackPointer ) \
    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
 /**
 * @brief Read the PSPLIM value in the given variable.
 */
 #define secureportREAD_PSPLIM( pucOutStackLimit ) \
    __asm volatile ( "mrs %0, psplim"  : "=r" ( pucOutStackLimit ) )
 /**
 * @brief Set the PSPLIM to the given value.
 */
--- a/portable/BCC/16BitDOS/Flsh186/port.c
+++ b/portable/BCC/16BitDOS/Flsh186/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/BCC/16BitDOS/PC/port.c
+++ b/portable/BCC/16BitDOS/PC/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/BCC/16BitDOS/PC/prtmacro.h
+++ b/portable/BCC/16BitDOS/PC/prtmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/BCC/16BitDOS/common/portasm.h
+++ b/portable/BCC/16BitDOS/common/portasm.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/BCC/16BitDOS/common/portcomn.c
+++ b/portable/BCC/16BitDOS/common/portcomn.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_CM3/port.c
+++ b/portable/CCS/ARM_CM3/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_CM3/portasm.asm
+++ b/portable/CCS/ARM_CM3/portasm.asm
@ -1,5 +1,5 @@
 ;/*
-; * FreeRTOS Kernel V10.4.3
+; * FreeRTOS Kernel V10.4.3 LTS Patch 3
 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_CM3/portmacro.h
+++ b/portable/CCS/ARM_CM3/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_CM4F/port.c
+++ b/portable/CCS/ARM_CM4F/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_CM4F/portasm.asm
+++ b/portable/CCS/ARM_CM4F/portasm.asm
@ -1,5 +1,5 @@
 ;/*
-; * FreeRTOS Kernel V10.4.3
+; * FreeRTOS Kernel V10.4.3 LTS Patch 3
 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_CM4F/portmacro.h
+++ b/portable/CCS/ARM_CM4F/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_Cortex-R4/port.c
+++ b/portable/CCS/ARM_Cortex-R4/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_Cortex-R4/portASM.asm
+++ b/portable/CCS/ARM_Cortex-R4/portASM.asm
@ -1,5 +1,5 @@
 ;/*
-; * FreeRTOS Kernel V10.4.3
+; * FreeRTOS Kernel V10.4.3 LTS Patch 3
 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ b/portable/CCS/ARM_Cortex-R4/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/MSP430X/data_model.h
+++ b/portable/CCS/MSP430X/data_model.h
@ -1,5 +1,5 @@
 ;/*
-; * FreeRTOS Kernel V10.4.3
+; * FreeRTOS Kernel V10.4.3 LTS Patch 3
 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/MSP430X/port.c
+++ b/portable/CCS/MSP430X/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/MSP430X/portext.asm
+++ b/portable/CCS/MSP430X/portext.asm
@ -1,5 +1,5 @@
 ;/*
-; * FreeRTOS Kernel V10.4.3
+; * FreeRTOS Kernel V10.4.3 LTS Patch 3
 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CCS/MSP430X/portmacro.h
+++ b/portable/CCS/MSP430X/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/ColdFire_V1/port.c
+++ b/portable/CodeWarrior/ColdFire_V1/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/ColdFire_V1/portasm.S
+++ b/portable/CodeWarrior/ColdFire_V1/portasm.S
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/ColdFire_V2/port.c
+++ b/portable/CodeWarrior/ColdFire_V2/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/ColdFire_V2/portasm.S
+++ b/portable/CodeWarrior/ColdFire_V2/portasm.S
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/HCS12/port.c
+++ b/portable/CodeWarrior/HCS12/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/CodeWarrior/HCS12/portmacro.h
+++ b/portable/CodeWarrior/HCS12/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/Common/mpu_wrappers.c
+++ b/portable/Common/mpu_wrappers.c
--- a/portable/GCC/ARM7_AT91FR40008/port.c
+++ b/portable/GCC/ARM7_AT91FR40008/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ b/portable/GCC/ARM7_AT91FR40008/portISR.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_AT91SAM7S/port.c
+++ b/portable/GCC/ARM7_AT91SAM7S/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_LPC2000/port.c
+++ b/portable/GCC/ARM7_LPC2000/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/portable/GCC/ARM7_LPC2000/portISR.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/portable/GCC/ARM7_LPC2000/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_LPC23xx/port.c
+++ b/portable/GCC/ARM7_LPC23xx/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_LPC23xx/portISR.c
+++ b/portable/GCC/ARM7_LPC23xx/portISR.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ b/portable/GCC/ARM7_LPC23xx/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/portable/GCC/ARM_CA53_64_BIT/port.c
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM_CA53_64_BIT/portASM.S
+++ b/portable/GCC/ARM_CA53_64_BIT/portASM.S
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@ -1,5 +1,5 @@
 /*
- * FreeRTOS Kernel V10.4.3
+ * FreeRTOS Kernel V10.4.3 LTS Patch 3
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
--- a/Show more
+++ b/Show more
Author	SHA1	Message	Date
Gaurav Aggarwal	0437c8257a	[AUTO][RELEASE]: Bump file header version to "10.4.3 LTS Patch 3"	2022-09-16 18:13:25 +00:00
Gaurav Aggarwal	292c794e98	[AUTO][RELEASE]: Bump task.h version macros to "10.4.3 LTS Patch 3"	2022-09-16 18:13:24 +00:00
Gaurav Aggarwal	9fa8dcb33c	Update History.txt as per PR feedback Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	ac6efdd544	Fix failed CI check Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	14f9cc660f	Update History.txt Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	94223d7930	Update History.txt Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	7a98bd8d78	Added checks for xIndex in ThreadLocalStorage APIs It was possible for a third party that already independently gained the ability to execute injected code to read from or write to arbitrary addresses by passing a negative argument as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or vTaskSetThreadLocalStoragePointer respectively. This commit adds checks to ensure that passing a negative argument as the xIndex parameter does not cause arbitrary read or write. We thank Certibit Consulting, LLC for reporting this issue. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	da73aa6329	Restrict unpriv task to invoke code with privilege It was possible for an unprivileged task to invoke any function with privilege by passing it as a parameter to MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate, MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. This commit ensures that MPU_xTaskCreate and MPU_xTaskCreateStatic can only create unprivileged tasks. It also removes the following APIs: 1. MPU_xTimerCreate 2. MPU_xTimerCreateStatic 3. MPU_xTimerPendFunctionCall We thank Huazhong University of Science and Technology for reporting this issue. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	51ea2bfe62	Remove local stack variable form MPU wrappers It was possible for a third party that had already independently gained the ability to execute injected code to achieve further privilege escalation by branching directly inside a FreeRTOS MPU API wrapper function with a manually crafted stack frame. This commit removes the local stack variable `xRunningPrivileged` so that a manually crafted stack frame cannot be used for privilege escalation by branching directly inside a FreeRTOS MPU API wrapper. We thank Certibit Consulting, LLC, Huazhong University of Science and Technology and the SecLab team at Northeastern University for reporting this issue. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	c4ad77f694	Make RAM regions non-executable This commit makes the privileged RAM and stack regions non-executable. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	acd9279fc2	Use highest numbered MPU regions for kernel ARMv7-M allows overlapping MPU regions. When 2 MPU regions overlap, the MPU configuration of the higher numbered MPU region is applied. For example, if a memory area is covered by 2 MPU regions 0 and 1, the memory permissions for MPU region 1 are applied. We use 5 MPU regions for kernel code and kernel data protections and leave the remaining for the application writer. We were using lowest numbered MPU regions (0-4) for kernel protections and leaving the remaining for the application writer. The application writer could configure those higher numbered MPU regions to override kernel protections. This commit changes the code to use highest numbered MPU regions for kernel protections and leave the remaining for the application writer. This ensures that the application writer cannot override kernel protections. We thank the SecLab team at Northeastern University for reporting this issue. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-09-16 22:18:35 +05:30
Gaurav Aggarwal	1e08439294	Update History.txt for release date Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-11-12 10:56:46 -08:00
Gaurav Aggarwal	5f93abd3b5	[AUTO][RELEASE]: Bump file header version to "10.4.3 LTS Patch 2"	2021-10-06 19:33:51 -07:00
Gaurav Aggarwal	65b00127ad	[AUTO][RELEASE]: Bump task.h version macros to "10.4.3 LTS Patch 2"	2021-10-06 19:33:45 -07:00
Gaurav Aggarwal	07e866c2ce	Update History.txt for 10.4.3 LTS Patch 2 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-10-06 19:16:30 -07:00
Gaurav Aggarwal	ba50511821	Change xPortRaisePrivilege and vPortResetPrivilege to macros This prevents non-kernel code from calling these functions. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-10-06 19:13:48 -07:00
Gaurav Aggarwal	628059b775	Update History.txt Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-09-10 11:53:24 -07:00
Gaurav Aggarwal	dff28505b7	[AUTO][RELEASE]: Bump file header version to "10.4.3 LTS Patch 1"	2021-08-19 11:22:55 -07:00
Gaurav Aggarwal	fedc1652f4	[AUTO][RELEASE]: Bump task.h version macros to "10.4.3 LTS Patch 1"	2021-08-19 11:22:49 -07:00
Gaurav Aggarwal	0ab31da2fd	Update History.txt for 10.4.3 LTS Patch 1 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-08-19 10:45:18 -07:00
Gaurav Aggarwal	8341ffdc61	Fix free secure context for Cortex-M23 ports Update the branching condition to correctly free secure context when there is one. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-08-18 17:46:27 -07:00
Gaurav Aggarwal	faa92f7df2	Implement secure stack sealing as per ARM's recommendation Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-08-18 17:36:55 -07:00
Gaurav Aggarwal	f87404b56f	Associate secure context with task handle The secure side context management code now checks that the secure context being saved or restored belongs to the task being switched-out or switched-in respectively. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-08-18 17:31:22 -07:00
Gaurav Aggarwal	66466793d5	Pre-allocate secure-side context structures This commit improves ARMv8-M security by pre-allocating secure-side task context structures and changing how tasks reference a secure-side context structure when calling a secure function. The new configuration constant secureconfigMAX_SECURE_CONTEXTS sets the number of secure context structures to pre-allocate. secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2021-08-18 16:21:55 -07:00