Compare commits

..

58 commits

Author SHA1 Message Date
Kody Stribrny
f1043c49d5
MISRA 17.12 fixes, justifications for other reporting issues. (#1372)
* [8.6] Suppress declaration without definitions warnings

This is expected from the portable header as it is
implemented by the port.

* [21.3] Document unsupressed deviation

Deviations which are unsupressed should be
documented for user awareness.

* [2.2] Disclose dead code warning

* [2.1] Justify unreachable code in example

* [17.12] Add addressing operator to callback function

This is required to disambiguate a function call and a
function to-be called

* [4.12] Explain deviation for dynamic allocation

* [8.6] Remove suppression, instead explain reporting

* Suppress false null dereference
Coverity provides a false positive
of pxQueueSetContainer being null.
2026-02-24 13:59:45 -08:00
wirelinker
0f8efd98cc
Correct minor mistakes in code comments (#1371)
This commit revises some comments in the following files:
    - event_groups.c
    - include/queue.h
    - include/task.h

Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
2026-02-20 11:11:15 -08:00
Armchina_JidongMei
850d29477c
Add Arm China STAR-MC3 port support (#1363)
* Add Arm China STAR-MC3 port support:
Fix corresponding issue #1359

* Optimize for STAR-MC3 Code Reviw:
1 Rename form STAR_MC3 to ARM_STAR_MC3
2 Modify kernel_checker.py to pass license check

* Fix left issue of STAR-MC3 Code Review

* Rename STAR_MC3 to ARM_STAR_MC3 for portable/ARMv8M/ directory

---------

Co-authored-by: Kody Stribrny <89810515+kstribrnAmzn@users.noreply.github.com>
2026-02-20 10:33:34 -08:00
Ahmed Ismail
6cd736cfeb
Arm-Cortex-R82: Add MPU support (#1347)
* arm-cortex-r82: Add MPU support

This commit introduces support for the Memory Protection Unit (MPU)
to the ARM Cortex-R82 port. The MPU enhances system security
by allowing the definition of memory regions with specific access
permissions. The following changes have been made:
- Added MPU configuration functions in `port.c` to set up memory
  regions and their attributes.
- Updated `portASM.S` to include assembly routines for MPU
  and context switching with MPU support.
- Created `mpu_wrappers_v2_asm.c` to provide assembly wrappers for
  MPU operations.
- Updated `portmacro.h` to include MPU-related macros and definitions.
- Modified `task.h` to include MPU-related task attributes.
- Updated `CMakeLists.txt` to include the new MPU source file.
- Enhanced the `README.md` with instructions on MPU configuration.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* cortex-r82: Minor code improvements

This commit includes minor code improvements to enhance readability
and maintainability of the Cortex-R82 port files. Changes include
refactoring variable names, optimizing comments, and improving code
structure without altering functionality.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* tasks: Disable stack-depth check if MPU wrappers is set

This stack-depth check should not be performed for ports
where portUSING_MPU_WRAPPERS is set to 1.
In this case, pxTopOfStack and pxNewTCB->pxTopOfStack reside
in different memory regions: pxTopOfStack is in unprivileged SRAM,
while pxNewTCB->pxTopOfStack is in privileged SRAM.
This is because pxPortInitialiseStack() returns the address of
`ullContext` array rather than the decremented pxTopOfStack,
as is done in the non-MPU case.
Consequently, this check is not valid in this scenario.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

---------

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
2026-02-11 10:18:55 +05:30
Florian La Roche
d33d04b14c remove stray semicolon from gcc-ARM_CRx_MPU port.c
Remove stray semicolon from gcc-ARM_CRx_MPU port.c.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
2026-01-29 17:28:28 -08:00
Mike Bloom
67f59a5f58
Add missing include to fix compile error (#1358) 2026-01-18 18:38:16 +00:00
jasonpcarroll
5282247346
Add assert to check for overflow in xStreamBufferSendFromISR. (#1357)
Co-authored-by: czjaso <czjaso@amazon.com>
2026-01-13 13:35:01 -08:00
Maxim De Clercq
8a416d79c0
fix: Add big-endian support to ARM_CRx_No_GIC port (#1355)
This change makes sure the Data endianness bit is set in the SPSR
register when the program is being compiled for big-endian.

Signed-off-by: Maxim De Clercq <maximdeclercq00@gmail.com>
2026-01-12 21:22:07 +05:30
Bernd Edlinger
d5c3c98ae4
Add CFI frame unwind info in portable/IAR/RXv2/port_asm.s (#1341)
This allows the IAR debugger to display the callstack beyond
__interrupt_27 when a breakpoint in vTaskSwitchContext is made.
2026-01-12 17:53:32 +05:30
Graham Sanderson
c53a6b0547
RP2040: Add xPortIsInsideInterrupt to match other ARM ports (#1356)
Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
2026-01-12 12:28:27 +05:30
Kody Stribrny
1dbc77697f
[Fix] Reset correct priority on disinherit timeout (#1338)
This commit corrects vTaskPriorityDisinheritAfterTimeout
to reset the previously inherited priority when the task
disiheriting timeout was the only task at that priority.
Without this change the ready list for the inherited
priority will remain set when no task is ready at that priority.
This can have consequences later as the ready priority flags are
assumed to be accurate.

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-12-31 10:07:49 -08:00
Sidharth
26f9a2fdd3
Add cast in stack allocation for task creation (#1340)
for negative portSTACK_GROWTH, add cast to stack allocation, just like it is in positive portSTACK_GROWTH
2025-12-31 12:43:24 +05:30
Harsh Soni
14b30f209f
fix: Add missing macro guards in task.h (#1342)
- Add missing conditions to prevent unintended access to
  certain APIs in task.h
- The condition is mentioned in the API description but was
  absent in the code
2025-12-29 23:37:57 +05:30
AniruddhaKanhere
3ace38969b Add asserts to check stack overflow at task creation
This commit adds assert to allow developers to check for overflow of
undersized task stack during task creation.
2025-12-24 14:19:20 -08:00
nordync
a9cb459206
Win32: Guard timeapi.h include for MinGW compatibility (#1345)
* bugfix/mingw-timeapi

* fix: clean up Windows timer includes

- Removed legacy GCC-specific include block.
- Added compiler-specific headers:
  - MSVC (_MSC_VER): includes <timeapi.h> and links winmm.lib
  - Other compilers: includes <mmsystem.h>
- Ensures cross-compiler compatibility and avoids duplicate headers.

---------

Co-authored-by: Metehan Öztürk <mete_pukkada@outlook.com>
Co-authored-by: Monika Singh <moninom@amazon.com>
2025-12-23 12:01:31 -08:00
Kody Stribrny
536914b2a4
Add catch up behavior to xTaskDelayUntil. (#1348)
Adds an explanation for why xTaskDelayUntil
can break from the configured frequency when
catching up for past events. More will be added
to the website documentation.
2025-12-23 09:30:36 -08:00
Armchina_JidongMei
7d6890e650
Add ARM Cortex-M52 port support FreeRTOS#1305 (#1334)
Add ARM Cortex-M52 port support

Add ARM_CM52 and ARM_CM52_NTZ port implementations for GCC and IAR compilers
2025-12-19 17:52:58 +05:30
Saiiijchan
fed39c5ea7
Refine comments related to taskYIELD in queue.h (#1333)
Replace taskYIELD with portYIELD_FROM_ISR

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-11-12 13:51:08 +05:30
Saiiijchan
439af33c52
riscv: refine vector context layout on stack (#1329)
Vector general register layout:

Before:
+--------------+  <-- High Address
|      v7      |
+--------------+
|      v6      |
+--------------+
|      ...     |
+--------------+
|      v0      |
+--------------+  <-- v0 - v7
|      v15     |
+--------------+
|      v14     |
+--------------+
|      ...     |
+--------------+
|      v8      |
+--------------+  <-- v8 - v15
|      ...     |
+--------------+
|      v24     |
+--------------+  <-- Low address

After:
+--------------+  <-- High Address
|      v31     |
+--------------+
|      v30     |
+--------------+
|      ...     |
+--------------+
|      v1      |
+--------------+
|      v0      |
+--------------+ <-- Low Address

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-11-04 08:44:16 -08:00
Gaurav-Aggarwal-AWS
c8d31ddcff
Use saved mstatus for FPU/VPU state determination (#1330)
According to the RISC-V Privileged Architecture Specification (20211203),
writing Initial or Clean to the FS field of mstatus may result in the FS
value getting set to Dirty in some implementations. This means we cannot
rely on reading back the same FS value after writing to mstatus.

Previously, the context restore code would:
1. Write an FS value to mstatus
2. Read mstatus again at a later point
3. Use the read FS value to determine FPU status

This change updates the context restore code to use the mstatus value
from the saved context instead of re-reading mstatus after writing to
it. This required chaning the location of the mstatus slot in the
context.

Fixes: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1327

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-11-03 12:32:08 +05:30
Sheng Tai
8b63f94d8d
Fix: Propagate PICO_SDK_VERSION_* to parent scope in RP2040 port (#1326) 2025-10-29 14:35:00 -07:00
Kody Stribrny
13074875c2 Prefer xTaskDelayUntil in config template
xTaskDelayUntil is more featured and should
be preferred by new users. This change was inspired by
https://forums.freertos.org/t/include-xtaskdelayuntil-vs-include-vtaskdelayuntil/24656.
2025-10-27 20:27:19 -07:00
Pascal Reich
e5987bbdb2
Remove Unused Code and Preprocessor Directives in RP2040 Port (#1324)
* Remove redundant code and preprocessor directives

* Remove more redundant code and directives
2025-10-08 18:06:45 +05:30
Ths.quiniou
a1f6e1f64f
fix[RL78 Port] incorrect register image for pvParameters in FAR model (#1316) (#1317)
In the RL78 FAR data model, pxPortInitialiseStack() did not initialize
the register image for the task parameter (pvParameters) correctly.
A:DE registers were saved with dummy values instead of the actual pointer.

Effect: on first context restore the function prologue read a corrupted
parameter. NEAR builds were not affected.

This patch aligns the FAR path with the calling convention and compiler
version:
 - IAR V2: pass pvParameters via registers → DE = low 16 bits, A = high 8
 - IAR V1 (fallback): keep legacy stack write
Also keeps the original stack-frame layout and updates the comment to
reflect that pointer sizes depend on __DATA_MODEL__.

Result: tasks in FAR receive the correct parameter at entry; NEAR remains
unchanged.

Co-authored-by: Thomas Quiniou <tquiniou@fdi-access.com>
2025-10-06 18:37:11 +05:30
Ahmed Ismail
a8ae21c88e
armv8-r: Add Arm Cortex-R82 non-MPU port (#1289)
The goal of this commit is to add the GCC/ARMClang non-MPU
port variant for ARM Cortex-R82 processor which is
ARMv8-R AArch64 based.
The work done is inspired by the GCC ARM_AARCH64 FreeRTOS port.

This port has the following features:
* Uses single security state (non TrustZone).
* Supports SMP (Symmetric multi-processing).
* Doesn't support Hypervisor (EL2).
* Doesn't support neither PMSA (MPU) nor VMSA (MMU).

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
2025-09-29 20:10:22 +05:30
mathiasgredal
3d44975181
RP2040: Fix use of deprecated volatile semantics for C++20 (#1318) (#1319)
Co-authored-by: Mathias Gredal <matg@universal-robots.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-09-17 12:44:14 +05:30
razrbro
692c4b070f
Fix: avoid set but unused variable warning in pxPortInitialiseStack (#1320) 2025-09-17 11:19:04 +05:30
Ahmed Ismail
44ae6cf61a
cortex-M ports: Clarify hardware-saved exception frame size variable (#1314)
* cortex-M ports: Clarify hardware-saved exception frame size variable

- Rename ulStackFrameSize to ulHardwareSavedExceptionFrameSize to
reflect the hardware-saved exception frame (8 or 26 words based
on FPU/lazy stacking).
- Add comments explaining standard vs extended frames.
- Apply across Cortex-M ports.
- No functional change, improves readability.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* kernel-checker-script: Modify Arm copyright header regex

Arm's copyright header regex is modified with the following:

* Accept both single year copyright headers (e.g., "2024")
and year range copyright headers (e.g., "2024-2025").

* Accept both single-line copyright header and also
multi-line header.

* Add the escape backslash to accept only literal dot
not any character.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

---------

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-09-09 14:25:42 +08:00
Kim Lindberg Schwaner
ccabdec2f8
Fix risk of Win32 timer setup call getting ignored (#1311)
If a user configures the configASSERT macro to expand to nothing,
a call to the Win32 API SetWaitableTimer() doesn't get compiled.

This can happen if, for example, configASSERT(x) set defined as
assert(x) (from assert.h) which expands to nothing when NDEBUG is
set (common for "release" builds).
2025-08-15 11:09:28 -07:00
DuYicheng
386c1bca66
Change the macro from portMAX_DELAY to SIZE_MAX in order to initialize size_t-type variable correctly (#1310) 2025-08-15 12:37:23 +05:30
Ahmed Ismail
43947413b9
event-groups: Fix multiple definitions (#1307)
This commit does the following:
* Remove xEventGroupClearBitsFromISR and
xEventGroupSetBitsFromISR functions direct mapping
to xTimerPendFunctionCallFromISR in case the trace
facility is feature not set. This should match the
current implementation in which the application calling
xEventGroupClearBitsFromISR
without defining the trace macros
(i.e. traceENTER_xEventGroupClearBitsFromISR is
a blank function in this case) will end up calling
xTimerPendFunctionCallFromISR function directly.
This enhances the readability of the code by not
guarding the xEventGroup<Set/Clear>BitsFromISR
functions' declaration and definition based on
the trace facility macro (i.e. configUSE_TRACE_FACILITY).

* Refactor the guarding macros for MPU_xEventGroupClearBitsFromISR
and MPU_xEventGroupSetBitsFromISR functions to match the
change above.

The current implementation leads to redefinition warnings
as `event_groups.h`redefines xEventGroupClearBitsFromISR
and xEventGroupSetBitsFromISR based on
`configUSE_TRACE_FACILITY' after they have been defined based
on configUSE_MPU_WRAPPERS_V1 in `mpu_wrappers.h`. The
implemented changes should resolve these warnings.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
2025-08-14 10:40:59 -07:00
Dennis Lambe Jr.
c91ee8d724
Fix CMake build for GCC_ARM_CRx_MPU (#1308) (#1309)
Add GCC_ARM_CRX_MPU to the set of FREERTOS_PORT patterns that trigger
adding mpu_wrappers.c and mpu_wrappers_v2.c to freertos_kernel_port
target_sources.
2025-08-14 10:35:53 +05:30
creiter64
e9440d4079
Move windows headers to port.c (#1302)
* [MSVC-MingW] Move windows headers to port.c

This prevents the inclusion of windows.h. into all header files using
FreeRTOS.h and thus defining several macros conflicting with common
definitions.

* [MSVC-MingW] Include correct header for compiler intrinsics

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-08-05 19:11:54 +08:00
Dennis Lambe Jr.
c5bec0e4b2
LLVM assembler compatibility for ARM_CRx_MPU (#1303)
GNU as makes unrecognized sections loadable and writable by default, but
LLVM's assembler requires specifying flags explicitly. Without them, the
linker generates "has non-ABS relocation" errors when trying to link the
resulting object files.
2025-08-05 16:02:03 +05:30
Gaurav-Aggarwal-AWS
2da35debfd
Add missing cast to BaseType_t (#1301)
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-07-31 10:32:23 +08:00
Gaurav-Aggarwal-AWS
32e581636f
Delete thread key on process exit (#1297)
Previously, the shared thread key was deleted in xPortStartScheduler
after scheduler was ended. This created a race condition where
prvThreadKeyDestructor (responsible for freeing thread-specific heap
memory) would not be called if xPortStartScheduler deleted the key
before the last task deletion, as destructors are not invoked after key
deletion (see https://github.com/walac/glibc/blob/master/nptl/pthread_create.c#L145-L150).

Move thread key deletion to process exit to ensure all thread-specific
memory is properly freed.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-07-24 11:07:27 +05:30
Gaurav-Aggarwal-AWS
684b34ca8d
Define security extension configs before portable.h (#1294)
Define configENABLE_PAC and configENABLE_BTI before including portable.h
to prevent "used before definition" warnings when these macros are not
set in FreeRTOSConfig.h.

Fixes: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1293

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-07-14 16:20:18 +05:30
Aniruddha Kanhere
f5e6151b14
Update artifact path in the backup action (#1292)
* Add artifact backup action

* Fix artifact path
2025-07-09 09:53:13 -07:00
Florian La Roche
48a4939c9f
Fix compiler warning (#1291)
- In list.h fix a typo in comments.
- In portable/ThirdParty/GCC/Posix/port.c fix compiler warning about
  "gcc -Wwrite-strings".

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2025-07-09 11:16:00 +05:30
Aniruddha Kanhere
e3a362b1d1
Add artifact backup action (#1290) 2025-07-07 18:15:46 +05:30
Gaurav-Aggarwal-AWS
7225fbcbb9
Fix datatype of queue item length macros (#1286)
The uxItemSize parameter in xQueueGenericCreate and
xQueueGeneenericCreateStatic APIs expects a UBaseType_t type.
Previously, the semSEMAPHORE_QUEUE_ITEM_LENGTH macro incorrectly cast
the value to uint8_t, causing type mismatch warnings. This change
resolves the issue by properly casting the value to UBaseType_t.

This issue was reported here: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1285.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-06-30 18:11:30 +05:30
Florian La Roche
a882b10526
fix possible NULL pointer dereference after call to configASSERT() (#1284)
Compiling with clang static code analysis, possible NULL pointer
dereference are found. Since configASSERT() can possibly return
and continue "normal" operation, the code in queue.c and
stream_buffer.c can be adjusted to avoid NULL pointer exceptions.

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
2025-06-30 12:05:46 +05:30
Dakshit Babbar
0ae0715ac9
Update codecov badge url (#1283) 2025-06-16 20:39:05 +05:30
Rahul Kar
62bd622ffc
Update download locations to outside repository content (#1280)
Update curl command to download in a non user accessible folder
2025-06-05 23:23:47 +05:30
Simon Brizard
2615dcde13
fix[IAR/RL78 Port] Compilation fails on portasm.s file (#1278)
The indentation on ASM macro is not authorized by IAR compiler
2025-05-12 21:20:46 +05:30
Archit Gupta
03dc002c9b
Remove formatting bot workflow (#1274) 2025-05-09 14:09:08 -07:00
Gaurav-Aggarwal-AWS
e3a0e3e86a
Revert "FreeRTOS SMP: direct access to current TCB inside stack macros (#1270)" (#1272)
This reverts commit 4162ca49d6.
2025-05-05 15:45:15 +05:30
Matth9814
4162ca49d6
FreeRTOS SMP: direct access to current TCB inside stack macros (#1270)
FreeRTOS SMP: direct access to current TCB inside stack macros
2025-04-30 13:12:08 +05:30
Florian La Roche
d03233f209
fix warnings from "gcc -Wconversion" (#1271)
fix warnings from "gcc -Wconversion"

Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
2025-04-28 09:51:58 +05:30
Mario Luzeiro
4ee6a1f22f
MPLAB PIC32MZ-EF - Adds an assert to catch register overflow (#1265) (#1267)
Add an assert to catch register overflow (#1265)
2025-04-25 17:05:15 +05:30
arctic-alpaca
03db672b8f
Fix race in POSIX port vPortEndScheduler (#1262)
* Fix race in POSIX port `vPortEndScheduler`

The `vPortEndScheduler` checks whether it's a FreeRTOS thread after signalling the scheduler thread to stop. This creates a race between the check and the destruction of the thread key. By moving the signal to the scheduler thread after the check, the race is prevented.

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-04-03 14:32:44 +05:30
Jonathan Cubides
0030d609a4
Add support for Vector context save support on RISC-V (#1260)
port: riscv: Add vector context save support
2025-03-27 15:22:22 +05:30
ErickReyesR
b9aa064591
FreeRTOS MPU: Remove MPU region number check (#1261)
FreeRTOS MPU: Remove MPU region number check

This change removes the assertion and runtime check that enforces
matching between configTOTAL_MPU_REGIONS and physical MPU
regions,. This allows applications running on devices with 16 MPU
regions to manage 8 MPU regions while leaving the remaining 8
for the kernel.

Signed-off-by: Erick Reyes <erickreyes@google.com>
2025-03-19 15:01:22 +05:30
Gaurav-Aggarwal-AWS
dacce186cf
Use UBaseType_t for ullMachineTimerCompareRegisterBase (#1258)
Use architecture-dependent UBaseType_t instead of fixed type for
ullMachineTimerCompareRegisterBase. This type is defined to uint32_t or
uint64_t based on XLEN, resolving warnings on 32-bit platforms.

Reported by landretk@ on the PR FreeRTOS/FreeRTOS-Kernel#1176.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2025-03-17 16:41:11 +05:30
Saiiijchan
64fd9291ef
RISC-V: refine fpu reg context offset (#1257)
RISC-V: refine fpu reg context offset

pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-03-13 21:10:51 +05:30
Saiiijchan
bb47bc02f2
RISC-V: refine fpu offset according to portFPU_REG_SIZE (#1256)
Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
Co-authored-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-03-13 11:22:38 +05:30
Jonathan Cubides
4d9cd906d3
RISCV Add FPU context save (#1250)
* port: riscv: Split the number of registers and the size of the context

* port: riscv: Create some macros for the FPU context

* port: riscv: Add a couple of macros that store fpu context

* port: riscv: Update the stack init function to include the fpu context size

* port: riscv: Add a chip_specific_extensions file that includes the F extension

* Update dictionary to include some risc-v instructions

* port: riscv: Fix a few typos

* port: riscv: Apply @aggarg's sugestions
2025-03-06 10:34:48 -08:00
Stefan Innerhofer
742729ed29
Add an assert o catch overflow of recursive mutex counter (#1254)
Add an assert o catch overflow of recursive mutex counter.
2025-03-04 15:25:19 +05:30
765 changed files with 59700 additions and 8254 deletions

View file

@ -23,11 +23,13 @@ AIRCR
ALMIEN
ALMV
ANDC
andi
ANDCCR
APIC
APROCFREQ
APSR
ARMCM
ARMEB
Armv
ARMVFP
ASTRINGZ
@ -47,6 +49,7 @@ bcpc
BCPC
beevt
BEEVT
beqz
BERR
bfextu
Biagioni
@ -67,6 +70,7 @@ CANTX
capitalisation
cbmc
CBMC
cbnz
cbor
CBOR
CCIE
@ -105,6 +109,8 @@ CLKS
CLKSOURCE
CLKSTA
CLRB
clrex
CLREX
CLRF
clrm
CLRPSW
@ -298,6 +304,7 @@ FADD
FCMD
fcolor
FCSE
fcsr
fdiagnostics
fdiv
FDIV
@ -375,6 +382,7 @@ IFSR
imajeff
INACK
INDF
initialisations
inpw
INTE
INTFRCH
@ -427,6 +435,7 @@ ldrbs
LDRBS
LDRNE
ldsr
ldxr
lidt
LINKR
LJMP
@ -502,6 +511,7 @@ movs
movw
MOVWF
movx
MPIDR
MPLAB
MPUCTRL
MQTT
@ -646,6 +656,8 @@ PPUDR
PPUER
PPUSR
ppux
Prbar
PRBAR
PRCR
PREA
PREB
@ -653,11 +665,15 @@ PRIA
Prioritised
PRIS
PRIVDEFENA
Prlar
PRLAR
PROCDLY
PRODH
PRODL
PROGE
Prokic
Prselr
PRSELR
prtmacro
psha
psplim
@ -700,6 +716,7 @@ REENT
REGA
RELD
Renesas
restoreallgpregisters
reta
reti
RETP
@ -767,6 +784,8 @@ SCBR
SCDR
SCER
SCSR
Sctlr
SCTLR
SDCC
SECU
SENDA
@ -776,6 +795,7 @@ SETINTENA
SETPSW
SETR
setvect
sevl
SFRC
SHLL
SHLR
@ -783,6 +803,7 @@ SHPR
SHTIM
SIFIVE
sinclude
slli
SODR
SOFTIRQ
SPCK
@ -805,6 +826,7 @@ STTBRK
STTDLY
STTOUT
STTTO
stxr
SVACC
svcne
SVDIS
@ -921,6 +943,7 @@ UNSUB
UNSUBACK
unsubscriptions
unsuspended
unupdated
UPAC
URAD
URAT
@ -934,6 +957,7 @@ USRIO
utest
utilises
utilising
vcsr
VDDCORE
vect
Vect
@ -944,6 +968,7 @@ visualisation
vldmdbeq
vldmia
vldmiaeq
vlenb
VMSRNE
vpop
VPOPNE
@ -951,6 +976,7 @@ vpush
VPUSHNE
VRPM
Vrtc
vsetvl
vstmdbeq
vstmiaeq
VTOR

View file

@ -1,3 +1,5 @@
https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus
https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads
https://www.microchip.com
https://www.microchip.com/support

View file

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#/*
# * FreeRTOS Kernel V11.2.0
# * FreeRTOS Kernel <DEVELOPMENT BRANCH>
# * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
# *
# * SPDX-License-Identifier: MIT
@ -112,13 +112,22 @@ KERNEL_ARM_COLLAB_FILES_PATTERNS = [
r'.*portable/.*/ARM_CM23*',
r'.*portable/.*/ARM_CM33*',
r'.*portable/.*/ARM_CM35*',
r'.*portable/.*/ARM_CM52*',
r'.*portable/.*/ARM_CM55*',
r'.*portable/.*/ARM_CM85*',
r'.*portable/.*/ARM_CM0*',
r'.*portable/.*/ARM_CM3_MPU*',
r'.*portable/.*/ARM_CM4_MPU*',
r'.*portable/.*/ARM_CM4F_MPU*',
r'.*portable/.*/ARM_CR82*',
r'.*portable/.*/ARM_STAR_MC3*',
r'.*include/task\.h$',
r'.*tasks\.c$',
]
KERNEL_HEADER = [
'/*\n',
' * FreeRTOS Kernel V11.2.0\n',
' * FreeRTOS Kernel <DEVELOPMENT BRANCH>\n',
' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n',
' *\n',
' * SPDX-License-Identifier: MIT\n',
@ -150,8 +159,9 @@ KERNEL_HEADER = [
FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d Arm Limited and/or its affiliates( \*\/)?$)|" + \
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm.com>( \*\/)?$)"
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d(-20\d\d)? Arm Limited and/or its affiliates( +<open-source-office@arm\.com>)?( \*\/)?$)|" + \
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(c\) 20\d\d(-20\d\d)? Arm Technology \(China\) Co., Ltd.All Rights Reserved\.( \*\/)?$)|" + \
r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm\.com>( \*\/)?$)"
class KernelHeaderChecker(HeaderChecker):
@ -193,6 +203,8 @@ class KernelHeaderChecker(HeaderChecker):
]
if (len(lines) > 0) and (lines[0].find("#!") == 0):
lines.remove(lines[0])
if (len(lines) > 0) and (len(lines[-1].strip()) == 0):
lines.remove(lines[-1])
# Split lines in sections.
headers = dict()
@ -210,7 +222,9 @@ class KernelHeaderChecker(HeaderChecker):
text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"])
spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"])
if text_equal and spdx_equal and len(headers["copyright"]) == 3:
if text_equal and spdx_equal:
# Some files do not have "open-source-office@arm.com" line.
if len(headers["copyright"]) == 3 or len(headers["copyright"]) == 2:
isValid = True
return isValid

View file

@ -18,6 +18,8 @@ on:
jobs:
release-packager:
permissions:
id-token: write
name: Release Packager
runs-on: ubuntu-latest
steps:
@ -117,6 +119,14 @@ jobs:
./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
exit $?
- name: Backup Release Asset
uses: FreeRTOS/CI-CD-Github-Actions/artifact-backup@main
with:
# This is dependent on the release script putting this zip file
# in this exact location.
artifact_path: ./FreeRTOS-KernelV${{ github.event.inputs.version_number }}.zip
release_tag: ${{ github.event.inputs.version_number }}
- name: Cleanup
env:
VERSION_NUMBER: ${{ github.event.inputs.version_number }}

View file

@ -7,7 +7,7 @@ on:
workflow_dispatch:
jobs:
formatting:
runs-on: ubuntu-20.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4.1.1
- name: Check Formatting of FreeRTOS-Kernel Files

View file

@ -42,11 +42,22 @@ jobs:
# ${{ env.stepName }}
echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
wget -nv -qO- https://scan.coverity.com/download/linux64 --post-data "token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" | tar -zx --one-top-level=cov_scan --strip-components 1
echo "cov_scan_path=$(pwd)/cov_scan/bin" >> $GITHUB_ENV
wget -nv -q -O "$HOME/cov-analysis.tar.gz" https://scan.coverity.com/download/linux64 --post-data="token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel"
EXPECTED_MD5="e4418004b073140d67390cffba79c3b2"
GENERATED_MD5=$(md5sum "$HOME/cov-analysis.tar.gz" | awk '{print $1}')
if [ "$GENERATED_MD5" = "$EXPECTED_MD5" ]; then
tar -zxf "$HOME/cov-analysis.tar.gz" --one-top-level=cov_scan -C "$HOME"
echo "cov_scan_path=$HOME/cov_scan/bin" >> $GITHUB_ENV
sudo rm -f "$HOME/cov-analysis.tar.gz"
echo "::endgroup::"
echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
else
echo -e "${{ env.bashFail }} MD5 checksum verification failed for cov-analysis.tar.gz ${{ env.bashEnd }}"
echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
exit -1
fi
- env:
stepName: Coverity Build

View file

@ -1,25 +0,0 @@
name: Format Pull Request Files
on:
issue_comment:
types: [created]
env:
bashPass: \033[32;1mPASSED -
bashInfo: \033[33;1mINFO -
bashFail: \033[31;1mFAILED -
bashEnd: \033[0m
jobs:
Formatting:
name: Run Formatting Check
if: ${{ github.event.issue.pull_request &&
( ( github.event.comment.body == '/bot run uncrustify' ) ||
( github.event.comment.body == '/bot run formatting' ) ) }}
runs-on: ubuntu-20.04
steps:
- name: Apply Formatting Fix
id: check-formatting
uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
with:
exclude-dirs: portable

View file

@ -5,7 +5,7 @@ on: [push, pull_request]
jobs:
kernel-checker:
name: FreeRTOS Kernel Header Checks
runs-on: ubuntu-20.04
runs-on: ubuntu-latest
steps:
# Install python 3
- name: Tool Setup

View file

@ -156,14 +156,27 @@ jobs:
run: |
# ${{ env.stepName }}
echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
curl -L -O https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
sudo apt update -y
sudo apt install -y p7zip-full
pushd $HOME
curl -L -o msp430-gcc-full-linux-x64-installer-9.3.1.2.7z https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
EXPECTED_MD5="2db2f99b4cd5c541ca0389ee20c67527"
GENERATED_MD5=$(md5sum msp430-gcc-full-linux-x64-installer-9.3.1.2.7z | awk '{print $1}')
if [ "$GENERATED_MD5" = "$EXPECTED_MD5" ]; then
7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run
sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended
echo "::endgroup::"
popd
echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
else
popd
echo -e "${{ env.bashFail }} MD5 checksum verification failed for msp430-gcc-full-linux-x64-installer-9.3.1.2.7z ${{ env.bashEnd }}"
echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
exit -1
fi
- name: Build msp430_GCC Demo
shell: bash
@ -211,21 +224,23 @@ jobs:
sudo apt install -y autogen gawk libgmp-dev libmpc-dev libmpfr-dev
sudo apt install -y patchutils sharutils zlib1g-dev autoconf2.64
pushd $HOME
# Download the mb-gcc toolchain from github
curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
curl -L -o binutils-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
curl -L -o gcc-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
curl -L -o libnewlib-microblaze-dev.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
curl -L -o libnewlib-microblaze-doc.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
curl -L -o libnewlib-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
curl -L -o newlib-source.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
popd
# Install the packages for the toolchain
sudo apt install -y ./binutils-microblaze*.deb;
sudo apt install -y ./gcc-microblaze*.deb;
sudo apt install -y ./libnewlib-microblaze-dev*.deb;
sudo apt install -y ./libnewlib-microblaze-doc*.deb;
sudo apt install -y ./libnewlib-microblaze*.deb;
sudo apt install -y ./newlib-source*.deb;
sudo apt install -y $HOME/binutils-microblaze.deb;
sudo apt install -y $HOME/gcc-microblaze.deb;
sudo apt install -y $HOME/libnewlib-microblaze-dev.deb;
sudo apt install -y $HOME/libnewlib-microblaze-doc.deb;
sudo apt install -y $HOME/libnewlib-microblaze.deb;
sudo apt install -y $HOME/newlib-source.deb;
# Validate that the toolchain is in the path and can be called
which mb-gcc

View file

@ -3,7 +3,7 @@ on: [push, pull_request]
jobs:
run:
runs-on: ubuntu-20.04
runs-on: ubuntu-latest
steps:
- name: Checkout Parent Repository
uses: actions/checkout@v4.1.1

View file

@ -76,6 +76,10 @@ if(NOT FREERTOS_PORT)
" GCC_ARM_CM35P_NONSECURE - Compiler: GCC Target: ARM Cortex-M35P non-secure\n"
" GCC_ARM_CM35P_SECURE - Compiler: GCC Target: ARM Cortex-M35P secure\n"
" GCC_ARM_CM35P_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M35P non-trustzone non-secure\n"
" GCC_ARM_CM52_NONSECURE - Compiler: GCC Target: ARM Cortex-M52 non-secure\n"
" GCC_ARM_CM52_SECURE - Compiler: GCC Target: ARM Cortex-M52 secure\n"
" GCC_ARM_CM52_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M52 non-trustzone non-secure\n"
" GCC_ARM_CM52_TFM - Compiler: GCC Target: ARM Cortex-M52 non-secure for TF-M\n"
" GCC_ARM_CM55_NONSECURE - Compiler: GCC Target: ARM Cortex-M55 non-secure\n"
" GCC_ARM_CM55_SECURE - Compiler: GCC Target: ARM Cortex-M55 secure\n"
" GCC_ARM_CM55_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M55 non-trustzone non-secure\n"
@ -84,9 +88,14 @@ if(NOT FREERTOS_PORT)
" GCC_ARM_CM85_SECURE - Compiler: GCC Target: ARM Cortex-M85 secure\n"
" GCC_ARM_CM85_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M85 non-trustzone non-secure\n"
" GCC_ARM_CM85_TFM - Compiler: GCC Target: ARM Cortex-M85 non-secure for TF-M\n"
" GCC_ARM_STAR_MC3_NONSECURE - Compiler: GCC Target: Arm China STAR-MC3 non-secure\n"
" GCC_ARM_STAR_MC3_SECURE - Compiler: GCC Target: Arm China STAR-MC3 secure\n"
" GCC_ARM_STAR_MC3_NTZ_NONSECURE - Compiler: GCC Target: Arm China STAR-MC3 non-trustzone non-secure\n"
" GCC_ARM_STAR_MC3_TFM - Compiler: GCC Target: Arm China STAR-MC3 non-secure for TF-M\n"
" GCC_ARM_CR5 - Compiler: GCC Target: ARM Cortex-R5\n"
" GCC_ARM_CRX_MPU - Compiler: GCC Target: ARM Cortex-Rx with MPU\n"
" GCC_ARM_CRX_NOGIC - Compiler: GCC Target: ARM Cortex-Rx no GIC\n"
" GCC_ARM_CR82 - Compiler: GCC Target: ARM Cortex-R82\n"
" GCC_ARM7_AT91FR40008 - Compiler: GCC Target: ARM7 Atmel AT91R40008\n"
" GCC_ARM7_AT91SAM7S - Compiler: GCC Target: ARM7 Atmel AT91SAM7S\n"
" GCC_ARM7_LPC2000 - Compiler: GCC Target: ARM7 LPC2000\n"
@ -142,6 +151,10 @@ if(NOT FREERTOS_PORT)
" IAR_ARM_CM35P_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-secure\n"
" IAR_ARM_CM35P_SECURE - Compiler: IAR Target: ARM Cortex-M35P secure\n"
" IAR_ARM_CM35P_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-trustzone non-secure\n"
" IAR_ARM_CM52_NONSECURE - Compiler: IAR Target: ARM Cortex-M52 non-secure\n"
" IAR_ARM_CM52_SECURE - Compiler: IAR Target: ARM Cortex-M52 secure\n"
" IAR_ARM_CM52_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M52 non-trustzone non-secure\n"
" IAR_ARM_CM52_TFM - Compiler: IAR Target: ARM Cortex-M52 non-secure for TF-M\n"
" IAR_ARM_CM55_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-secure\n"
" IAR_ARM_CM55_SECURE - Compiler: IAR Target: ARM Cortex-M55 secure\n"
" IAR_ARM_CM55_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-trustzone non-secure\n"
@ -150,6 +163,10 @@ if(NOT FREERTOS_PORT)
" IAR_ARM_CM85_SECURE - Compiler: IAR Target: ARM Cortex-M85 secure\n"
" IAR_ARM_CM85_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M85 non-trustzone non-secure\n"
" IAR_ARM_CM85_TFM - Compiler: IAR Target: ARM Cortex-M85 non-secure for TF-M\n"
" IAR_ARM_STAR_MC3_NONSECURE - Compiler: IAR Target: Arm China STAR-MC3 non-secure\n"
" IAR_ARM_STAR_MC3_SECURE - Compiler: IAR Target: Arm China STAR-MC3 secure\n"
" IAR_ARM_STAR_MC3_NTZ_NONSECURE - Compiler: IAR Target: Arm China STAR-MC3 non-trustzone non-secure\n"
" IAR_ARM_STAR_MC3_TFM - Compiler: IAR Target: Arm China STAR-MC3 non-secure for TF-M\n"
" IAR_ARM_CRX_NOGIC - Compiler: IAR Target: ARM Cortex-Rx no GIC\n"
" IAR_ATMEGA323 - Compiler: IAR Target: ATMega323\n"
" IAR_ATMEL_SAM7S64 - Compiler: IAR Target: Atmel SAM7S64\n"

View file

@ -19,6 +19,7 @@ grep 'MISRA Ref 8.4.1' . -rI
```
#### Dir 4.7
MISRA C:2012 Dir 4.7: If a function returns error information, then that error
information shall be tested.
@ -143,3 +144,90 @@ _Ref 21.6.1_
- The Standard Library function snprintf is used in vTaskListTasks and
vTaskGetRunTimeStatistics APIs, both of which are utility functions only and
are not considered part of core kernel implementation.
### Unsuppressed Deviations
Certain deviating code is left unsuppressed for awareness. These violations
will be reported when audited by a MISRA-checking static analysis tool.
Some of these unsuppressed exceptions correspond to example code provided
either for demonstration or verification of the FreeRTOS kernel. This code
is not considered part of the kernel implementation and should not be used
in an application.
Other unsuppressed violations are left present in the kernel implementation
as implementations, code, or other missing functionality being flagged for
violations will be present with the porting layer provided by the
application. The presence of these errors after providing a port indicates
a valid MISRA issue.
#### Rule 2.1
MISRA C:2012 Dir 2.1: A project shall not contain unreachable code
_Ref 2.1_
- Simplified example contains unreachable code for demonstration of
FreeRTOS scheduler. A production implementation should not contain
this.
Affected Files:
- examples/cmake_example/main.c
#### Rule 2.2
MISRA C:2012 Dir 2.2: There shall be no dead code.
_Ref 2.2_
- `vPortEndScheduler` is erroneously determined to be dead code due to
the use of a simplified verification port.
Affected Files:
- tasks.c
#### Dir 4.12
MISRA C:2012 Dir 4.12: Dynamic allocation shall not be used
_Ref 4.12_
- Heap memory solutions utilize pvPortMalloc/vPortFree to provide heap
memory for dynamic object allocation. These functions may rely upon
the malloc/free of the underlying port. Static allocation is recommended
for MISRA compliant applications.
Affected Files:
- portable/MemMang/heap_*.c
#### Rule 8.6
MISRA C:2012 Rule 8.6: An identifier with external linkage shall have exactly
one external definition.
_Ref 8.6.1_
- Port layer function declarations are provided without corresponding
implementations to provide for ease of porting to a device. These definitions
cannot be implemented until a port is selected.
#### Rule 21.3
MISRA C-2012 Rule 21.3: The memory allocation and deallocation functions of
<stdlib.h> shall not be used.
_Ref 21.3_
- See justification from Directive 4.12
Affected Files:
- portable/MemMang/heap_*.c
#### Rule 21.6
MISRA C-2012 Rule 21.6: The Standard Library input/output functions shall not
be used.
_Ref 21.6.1_
- The Standard Library function `printf` is used in examples to provide a
simple getting started demonstration. This example is not considered part
of the kernel implementation.
Affected Files:
- examples/cmake_example/main.c

View file

@ -1,5 +1,5 @@
[![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
[![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
[![codecov](https://app.codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
## Getting started

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -72,7 +72,7 @@
* The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is
* pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
* are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the
* wait condition is met if any of the bits set in uxBitsToWait for are also set
* wait condition is met if any of the bits set in uxBitsToWaitFor are also set
* in uxCurrentEventBits.
*/
static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
@ -501,7 +501,7 @@
}
/*-----------------------------------------------------------*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToClear )
@ -511,14 +511,14 @@
traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
xReturn = xTimerPendFunctionCallFromISR( &vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
traceRETURN_xEventGroupClearBitsFromISR( xReturn );
return xReturn;
}
#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
@ -812,7 +812,7 @@
}
/*-----------------------------------------------------------*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet,
@ -823,14 +823,14 @@
traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
xReturn = xTimerPendFunctionCallFromISR( &vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
traceRETURN_xEventGroupSetBitsFromISR( xReturn );
return xReturn;
}
#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -69,7 +69,7 @@ int main( void )
( void ) printf( "Example FreeRTOS Project\n" );
( void ) xTaskCreateStatic( exampleTask,
( void ) xTaskCreateStatic( &exampleTask,
"example",
configMINIMAL_STACK_SIZE,
NULL,

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -415,6 +415,8 @@
* number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__
* )" or it can simple disable interrupts and sit in a loop to halt all
* execution on the failing line for viewing in a debugger. */
/* *INDENT-OFF* */
#define configASSERT( x ) \
if( ( x ) == 0 ) \
{ \
@ -422,6 +424,7 @@
for( ; ; ) \
; \
}
/* *INDENT-ON* */
/******************************************************************************/
/* FreeRTOS MPU specific definitions. *****************************************/
@ -599,10 +602,10 @@
/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE)
* support, or 0 to leave the MVE support disabled. This option is only
* applicable to Cortex-M55 and Cortex-M85 ports as M-Profile Vector Extension
* (MVE) is available only on these architectures. configENABLE_MVE must be left
* undefined, or defined to 0 for the Cortex-M23,Cortex-M33 and Cortex-M35P
* ports. */
* applicable to Cortex-M52, Cortex-M55, Cortex-M85 and STAR-MC3 ports as
* M-Profile Vector Extension (MVE) is available only on these architectures.
* configENABLE_MVE must be left undefined, or defined to 0 for the
* Cortex-M23,Cortex-M33 and Cortex-M35P ports. */
#define configENABLE_MVE 1
/******************************************************************************/
@ -650,7 +653,7 @@
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_xTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -101,6 +101,16 @@
#define configASSERT_DEFINED 1
#endif
/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
* support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
#ifndef configENABLE_PAC
#define configENABLE_PAC 0
#endif
#ifndef configENABLE_BTI
#define configENABLE_BTI 0
#endif
/* Basic FreeRTOS definitions. */
#include "projdefs.h"
@ -3040,16 +3050,6 @@
#define configCONTROL_INFINITE_LOOP()
#endif
/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
* support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
#ifndef configENABLE_PAC
#define configENABLE_PAC 0
#endif
#ifndef configENABLE_BTI
#define configENABLE_BTI 0
#endif
/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
* dynamically allocated RAM, in which case when any task is deleted it is known
* that both the task's stack and TCB need to be freed. Sometimes the

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -246,7 +246,10 @@ void vCoRoutineSchedule( void );
* \defgroup crSTART crSTART
* \ingroup Tasks
*/
/* *INDENT-OFF* */
#define crEND() }
/* *INDENT-ON* */
/*
* These macros are intended for internal use by the co-routine implementation

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -452,13 +452,10 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
* \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
* \ingroup EventGroup
*/
#if ( configUSE_TRACE_FACILITY == 1 )
#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
#else
#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )
#endif
#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/**
* event_groups.h
@ -607,14 +604,11 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
* \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
* \ingroup EventGroup
*/
#if ( configUSE_TRACE_FACILITY == 1 )
#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet,
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#else
#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )
#endif
#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/**
* event_groups.h

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -44,7 +44,7 @@
*
* In addition to it's value, each list item contains a pointer to the next
* item in the list (pxNext), a pointer to the list it is in (pxContainer)
* and a pointer to back to the object that contains it. These later two
* and a pointer back to the object that contains it. These later two
* pointers are included for efficiency of list manipulation. There is
* effectively a two way link between the object containing the list item and
* the list item itself.

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -409,13 +409,16 @@ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet,
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet,
BaseType_t * pxHigherPriorityTaskWoken ) FREERTOS_SYSTEM_CALL;
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/* MPU versions of message/stream_buffer.h API functions. */
size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
const void * pvTxData,

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -202,8 +202,8 @@ typedef struct QueueDefinition * QueueSetMemberHandle_t;
* char ucData[ 20 ];
* };
*
#define QUEUE_LENGTH 10
#define ITEM_SIZE sizeof( uint32_t )
* #define QUEUE_LENGTH 10
* #define ITEM_SIZE sizeof( uint32_t )
*
* // xQueueBuffer will hold the queue structure.
* StaticQueue_t xQueueBuffer;
@ -217,8 +217,8 @@ typedef struct QueueDefinition * QueueSetMemberHandle_t;
* QueueHandle_t xQueue1;
*
* // Create a queue capable of containing 10 uint32_t values.
* xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
* ITEM_SIZE // The size of each item in the queue
* xQueue1 = xQueueCreateStatic( QUEUE_LENGTH, // The number of items the queue can hold.
* ITEM_SIZE, // The size of each item in the queue.
* &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
* &xQueueBuffer ); // The buffer that will hold the queue structure.
*
@ -1026,7 +1026,11 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
* // Now the buffer is empty we can switch context if necessary.
* if( xHigherPriorityTaskWoken )
* {
* taskYIELD ();
* // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
* // switch should be requested. The macro used is port specific and
* // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
* // refer to the documentation page for the port being used.
* portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* }
* @endcode
@ -1098,7 +1102,11 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
* // Now the buffer is empty we can switch context if necessary.
* if( xHigherPriorityTaskWoken )
* {
* taskYIELD ();
* // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
* // switch should be requested. The macro used is port specific and
* // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
* // refer to the documentation page for the port being used.
* portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* }
* @endcode
@ -1429,23 +1437,27 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
* // ISR that outputs all the characters received on the queue.
* void vISR_Routine( void )
* {
* BaseType_t xTaskWokenByReceive = pdFALSE;
* BaseType_t xHigherPriorityTaskWoken = pdFALSE;
* char cRxedChar;
*
* while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
* while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xHigherPriorityTaskWoken) )
* {
* // A character was received. Output the character now.
* vOutputCharacter( cRxedChar );
*
* // If removing the character from the queue woke the task that was
* // posting onto the queue xTaskWokenByReceive will have been set to
* // posting onto the queue xHigherPriorityTaskWoken will have been set to
* // pdTRUE. No matter how many times this loop iterates only one
* // task will be woken.
* }
*
* if( xTaskWokenByReceive != ( char ) pdFALSE;
* if( xHigherPrioritytaskWoken == pdTRUE );
* {
* taskYIELD ();
* // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
* // switch should be requested. The macro used is port specific and
* // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
* // refer to the documentation page for the port being used.
* portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* }
* @endcode

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@ -37,8 +37,8 @@
typedef QueueHandle_t SemaphoreHandle_t;
#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U )
#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U )
#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( UBaseType_t ) 1U )
#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0U )
#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U )

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,6 +1,7 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@ -53,9 +54,9 @@
* The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
* values will reflect the last released version number.
*/
#define tskKERNEL_VERSION_NUMBER "V11.2.0"
#define tskKERNEL_VERSION_NUMBER "V11.1.0+"
#define tskKERNEL_VERSION_MAJOR 11
#define tskKERNEL_VERSION_MINOR 2
#define tskKERNEL_VERSION_MINOR 1
#define tskKERNEL_VERSION_BUILD 0
/* MPU region parameters passed in ulParameters
@ -68,6 +69,9 @@
#if defined( portARMV8M_MINOR_VERSION ) && ( portARMV8M_MINOR_VERSION >= 1 )
#define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U )
#endif /* portARMV8M_MINOR_VERSION >= 1 */
#define tskMPU_REGION_NON_SHAREABLE ( 1U << 6U )
#define tskMPU_REGION_OUTER_SHAREABLE ( 1U << 7U )
#define tskMPU_REGION_INNER_SHAREABLE ( 1U << 8U )
/* MPU region permissions stored in MPU settings to
* authorize access requests. */
@ -602,12 +606,12 @@ typedef enum
* \defgroup xTaskCreateRestricted xTaskCreateRestricted
* \ingroup Tasks
*/
#if ( portUSING_MPU_WRAPPERS == 1 )
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
UBaseType_t uxCoreAffinityMask,
TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
@ -897,7 +901,8 @@ void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
*
* @return Value which can be used to check whether the task was actually delayed.
* Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not
* be delayed if the next expected wake time is in the past.
* be delayed if the next expected wake time is in the past. This prevents periodic
* tasks from accumulating delays and allows them to resume their regular timing pattern.
*
* Example usage:
* @code{c}
@ -2612,9 +2617,8 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
* notification value at that index being updated. ulValue is not used and
* xTaskNotifyIndexed() always returns pdPASS in this case.
*
* pulPreviousNotificationValue -
* Can be used to pass out the subject task's notification value before any
* bits are modified by the notify function.
* @param pulPreviousNotificationValue Can be used to pass out the subject
* task's notification value before any bits are modified by the notify function.
*
* @return Dependent on the value of eAction. See the description of the
* eAction parameter.
@ -2759,6 +2763,9 @@ BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
* updated. ulValue is not used and xTaskNotify() always returns pdPASS in
* this case.
*
* @param pulPreviousNotificationValue Can be used to pass out the subject
* task's notification value before any bits are modified by the notify function.
*
* @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set
* *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
* task to which the notification was sent to leave the Blocked state, and the

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

2
list.c
View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,4 +1,4 @@
name : "FreeRTOS-Kernel"
version: "V11.2.0"
version: "V11.0.1+"
description: "FreeRTOS Kernel."
license: "MIT"

View file

@ -1,11 +1,11 @@
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each
FreeRTOS release.
FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories
prior to each FreeRTOS release.
If your Armv8-M and Armv8.1-M application uses TrustZone then use the files from the
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories.
If your Armv8-M and Armv8.1-M application does not use TrustZone then use the files from
the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.
the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories.

View file

@ -1,5 +1,5 @@
#/*
# * FreeRTOS Kernel V11.2.0
# * FreeRTOS Kernel <DEVELOPMENT BRANCH>
# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
# *
# * SPDX-License-Identifier: MIT
@ -33,8 +33,8 @@ _THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
_COMPILERS_ = ['GCC', 'IAR']
_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM35P', 'ARM_CM35P_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM35P', 'ARM_CM33', 'ARM_CM23']
_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM52', 'ARM_CM52_NTZ', 'ARM_CM35P', 'ARM_CM35P_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ', 'ARM_STAR_MC3', 'ARM_STAR_MC3_NTZ']
_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM52', 'ARM_CM35P', 'ARM_CM33', 'ARM_CM23', 'ARM_STAR_MC3']
# Files to be compiled in the Secure Project
_SECURE_COMMON_FILE_PATHS_ = [
@ -48,16 +48,20 @@ _SECURE_PORTABLE_FILE_PATHS_ = {
'GCC':{
'ARM_CM23' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM23')],
'ARM_CM33' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM35P':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM35P' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM52' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM55' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')]
'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
'ARM_STAR_MC3' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')]
},
'IAR':{
'ARM_CM23' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM23')],
'ARM_CM33' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM35P':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM35P' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM52' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM55' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')]
'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
'ARM_STAR_MC3' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')]
}
}
@ -78,6 +82,12 @@ _NONSECURE_PORTABLE_FILE_PATHS_ = {
'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM35P', 'portmacro.h')],
'ARM_CM52' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM52', 'portmacro.h')],
'ARM_CM52_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM52', 'portmacro.h')],
'ARM_CM55' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')],
@ -89,7 +99,13 @@ _NONSECURE_PORTABLE_FILE_PATHS_ = {
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')],
'ARM_CM85_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')]
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')],
'ARM_STAR_MC3' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_STAR_MC3', 'portmacro.h')],
'ARM_STAR_MC3_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'),
os.path.join('non_secure', 'portable', 'GCC', 'ARM_STAR_MC3', 'portmacro.h')]
},
'IAR':{
'ARM_CM23' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23')],
@ -102,6 +118,12 @@ _NONSECURE_PORTABLE_FILE_PATHS_ = {
'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM35P', 'portmacro.h')],
'ARM_CM52' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM52', 'portmacro.h')],
'ARM_CM52_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM52', 'portmacro.h')],
'ARM_CM55' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')],
@ -113,7 +135,13 @@ _NONSECURE_PORTABLE_FILE_PATHS_ = {
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')],
'ARM_CM85_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')]
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')],
'ARM_STAR_MC3' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_STAR_MC3', 'portmacro.h')],
'ARM_STAR_MC3_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
os.path.join('non_secure', 'portable', 'IAR', 'ARM_STAR_MC3', 'portmacro.h')]
},
}

View file

@ -1,11 +1,11 @@
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to
each FreeRTOS release.
FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories
prior to each FreeRTOS release.
If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories.
If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.
the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories.

View file

@ -1,7 +1,7 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2024 Arm Limited and/or its affiliates
* Copyright 2024-2025 Arm Limited and/or its affiliates
* <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
@ -230,7 +230,7 @@ typedef void ( * portISR_t )( void );
#if ( portARMV8M_MINOR_VERSION >= 1 )
/* Enable Privileged eXecute Never MPU attribute for the selected memory
/* Enable Privileged eXecute Never MPU attribute for the selected memory
* region. */
#define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
#endif /* portARMV8M_MINOR_VERSION >= 1 */
@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -291,7 +288,7 @@ typedef void ( * portISR_t )( void );
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
/**
/**
* @brief Initial EXC_RETURN value.
*
* FF FF FF FD
@ -308,7 +305,7 @@ typedef void ( * portISR_t )( void );
#define portINITIAL_EXC_RETURN ( 0xfffffffd )
#else
/**
/**
* @brief Initial EXC_RETURN value.
*
* FF FF FF BC
@ -401,7 +398,7 @@ static void prvTaskExitError( void );
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
/**
* @brief Extract MPU region's access permissions from the Region Base Address
* Register (RBAR) value.
*
@ -414,7 +411,7 @@ static void prvTaskExitError( void );
#if ( configENABLE_MPU == 1 )
/**
/**
* @brief Setup the Memory Protection Unit (MPU).
*/
static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
@ -422,7 +419,7 @@ static void prvTaskExitError( void );
#if ( configENABLE_FPU == 1 )
/**
/**
* @brief Setup the Floating Point Unit (FPU).
*/
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
@ -430,7 +427,7 @@ static void prvTaskExitError( void );
#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
/**
/**
* @brief Configures PACBTI features.
*
* This function configures the Pointer Authentication, and Branch Target
@ -491,7 +488,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
/**
* @brief Sets up the system call stack so that upon returning from
* SVC, the system call stack is used.
*
@ -507,7 +504,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
/**
* @brief Raise SVC for exiting from a system call.
*/
void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
@ -516,7 +513,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
/**
* @brief Sets up the task stack so that upon returning from
* SVC, the task stack is used again.
*
@ -530,7 +527,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
#if ( configENABLE_MPU == 1 )
/**
/**
* @brief Checks whether or not the calling task is privileged.
*
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
@ -542,7 +539,7 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
@ -557,7 +554,7 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
#if ( configENABLE_TRUSTZONE == 1 )
/**
/**
* @brief Saved as part of the task context to indicate which context the
* task is using on the secure side.
*/
@ -579,18 +576,18 @@ PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
#if ( configUSE_TICKLESS_IDLE == 1 )
/**
/**
* @brief The number of SysTick increments that make up one tick period.
*/
PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
/**
/**
* @brief The maximum number of tick periods that can be suppressed is
* limited by the 24 bit resolution of the SysTick timer.
*/
PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
/**
/**
* @brief Compensate for the CPU cycles that pass while the SysTick is
* stopped (low power functionality only).
*/
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
@ -1210,7 +1200,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulSystemCallStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
@ -1246,12 +1236,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
{
pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
/* Hardware Saved Stack Frame Size upon Exception entry:
* - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
* - With FPU (lazy stacking): basic frame + S0S15 + FPSCR + reserved word = 26 words.
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
{
if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
ulHardwareSavedExceptionFrameSize = 26;
__asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
@ -1261,20 +1255,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
else
{
/* Standard frame i.e. FPU not in use. */
ulStackFrameSize = 8;
ulHardwareSavedExceptionFrameSize = 8;
}
}
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
ulHardwareSavedExceptionFrameSize = 8;
}
#endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize;
/* Copy the stack frame. */
for( i = 0; i < ulStackFrameSize; i++ )
for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
{
pulSystemCallStack[ i ] = pulTaskStack[ i ];
}
@ -1310,7 +1304,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
/* Remember the location where we should copy the stack frame when we exit from
* the system call. */
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize;
/* Record if the hardware used padding to force the stack pointer
* to be double word aligned. */
@ -1360,7 +1354,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
extern TaskHandle_t pxCurrentTCB;
xMPU_SETTINGS * pxMpuSettings;
uint32_t * pulTaskStack;
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
@ -1392,12 +1386,16 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
{
pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
/* Hardware Saved Stack Frame Size upon Exception entry:
* - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words.
* - With FPU (lazy stacking): basic frame + S0S15 + FPSCR + reserved word = 26 words.
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
{
if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
ulHardwareSavedExceptionFrameSize = 26;
__asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
@ -1407,20 +1405,20 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
else
{
/* Standard frame i.e. FPU not in use. */
ulStackFrameSize = 8;
ulHardwareSavedExceptionFrameSize = 8;
}
}
#else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
{
ulStackFrameSize = 8;
ulHardwareSavedExceptionFrameSize = 8;
}
#endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize;
/* Copy the stack frame. */
for( i = 0; i < ulStackFrameSize; i++ )
for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ )
{
pulTaskStack[ i ] = pulSystemCallStack[ i ];
}

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2024 Arm Limited and/or its affiliates
* <open-source-office@arm.com>

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2024 Arm Limited and/or its affiliates
* <open-source-office@arm.com>

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -0,0 +1,80 @@
/*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*------------------------------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the given hardware
* and compiler.
*
* These settings should not be altered.
*------------------------------------------------------------------------------
*/
#ifndef configENABLE_MVE
#error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
#endif /* configENABLE_MVE */
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M52"
#define portHAS_ARMV8M_MAIN_EXTENSION 1
#define portARMV8M_MINOR_VERSION 1
#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -0,0 +1,80 @@
/*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*------------------------------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the given hardware
* and compiler.
*
* These settings should not be altered.
*------------------------------------------------------------------------------
*/
#ifndef configENABLE_MVE
#error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
#endif /* configENABLE_MVE */
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
#define portARCH_NAME "STAR-MC3"
#define portHAS_ARMV8M_MAIN_EXTENSION 1
#define portARMV8M_MINOR_VERSION 1
#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2024 Arm Limited and/or its affiliates
* <open-source-office@arm.com>

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2024 Arm Limited and/or its affiliates
* <open-source-office@arm.com>

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -0,0 +1,87 @@
/*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*------------------------------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the given hardware
* and compiler.
*
* These settings should not be altered.
*------------------------------------------------------------------------------
*/
#ifndef configENABLE_MVE
#error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
#endif /* configENABLE_MVE */
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
#define portARCH_NAME "Cortex-M52"
#define portHAS_ARMV8M_MAIN_EXTENSION 1
#define portARMV8M_MINOR_VERSION 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
#pragma diag_suppress=Be006
#pragma diag_suppress=Pa082
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -0,0 +1,87 @@
/*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/*------------------------------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the given hardware
* and compiler.
*
* These settings should not be altered.
*------------------------------------------------------------------------------
*/
#ifndef configENABLE_MVE
#error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
#endif /* configENABLE_MVE */
/*-----------------------------------------------------------*/
/**
* Architecture specifics.
*/
#define portARCH_NAME "STAR-MC3"
#define portHAS_ARMV8M_MAIN_EXTENSION 1
#define portARMV8M_MINOR_VERSION 1
#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
#pragma diag_suppress=Be006
#pragma diag_suppress=Pa082
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
#endif /* PORTMACRO_H */

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Copyright 2024 Arm Limited and/or its affiliates
* <open-source-office@arm.com>

View file

@ -1,11 +1,11 @@
This directory tree contains the master copy of the FreeRTOS Armv8-M and
Armv8.1-M ports.
Do not use the files located here! These file are copied into separate
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to
each FreeRTOS release.
FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories
prior to each FreeRTOS release.
If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories.
If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.
the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories.

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

View file

@ -1,5 +1,5 @@
/*
* FreeRTOS Kernel V11.2.0
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT

Some files were not shown because too many files have changed in this diff Show more