diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt index 2c0785406..488722aa0 100644 --- a/.github/.cSpellWords.txt +++ b/.github/.cSpellWords.txt @@ -433,6 +433,7 @@ LDRAS ldrb ldrbs LDRBS +ldrex LDRNE ldsr ldxr diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py index 12383c2af..373ba6036 100755 --- a/.github/scripts/kernel_checker.py +++ b/.github/scripts/kernel_checker.py @@ -1,7 +1,8 @@ #!/usr/bin/env python3 #/* -# * FreeRTOS Kernel V11.3.0 +# * FreeRTOS Kernel # * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# * Copyright 2026 Arm Limited and/or its affiliates # * # * SPDX-License-Identifier: MIT # * @@ -127,7 +128,7 @@ KERNEL_ARM_COLLAB_FILES_PATTERNS = [ KERNEL_HEADER = [ '/*\n', - ' * FreeRTOS Kernel V11.3.0\n', + ' * FreeRTOS Kernel \n', ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n', ' *\n', ' * SPDX-License-Identifier: MIT\n', @@ -157,9 +158,10 @@ KERNEL_HEADER = [ FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$" +ARM_COLLAB_YEAR_REGEX = r"20\d\d(?:-20\d\d|, 20\d\d)?" FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \ - r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d(-20\d\d)? Arm Limited and/or its affiliates( +)?( \*\/)?$)|" + \ + rf"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright { ARM_COLLAB_YEAR_REGEX } Arm Limited and/or its affiliates( +)?( \*\/)?$)|" + \ r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(c\) 20\d\d(-20\d\d)? Arm Technology \(China\) Co., Ltd.All Rights Reserved\.( \*\/)?$)|" + \ r"(^(;|#)?( *(\/\*|\*|#|\/\/))? ( \*\/)?$)" diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml index 3759e5f48..6ebee34ea 100644 --- a/.github/workflows/auto-release.yml +++ b/.github/workflows/auto-release.yml @@ -169,7 +169,7 @@ jobs: creator: Amazon Web Services, Inc. download-location: git+https://github.com/${{ github.repository_owner }}/${{ github.event.repository.name }}.git@${{ github.event.inputs.version_number }} homepage: https://github.com/${{ github.repository_owner }}/${{ github.event.repository.name }} - namespace-prefix: https://github.com/${{ github.repository_owner }}/${{ github.event.repository.name }}/releases/download/${{ github.event.inputs.version_number }}/ + namespace-prefix: https://github.com/${{ github.repository_owner }}/${{ github.event.repository.name }}/releases/download/V${{ github.event.inputs.version_number }}/ include-file-hashes: true - name: Commit SBOM file @@ -208,7 +208,7 @@ jobs: # This is dependent on the release script putting this zip file # in this exact location. artifact_path: ./FreeRTOS-KernelV${{ github.event.inputs.version_number }}.zip - release_tag: ${{ github.event.inputs.version_number }} + release_tag: V${{ github.event.inputs.version_number }} - name: Delete release preparation branch if: always() diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml index 9371e9cea..e120aceac 100644 --- a/.github/workflows/kernel-demos.yml +++ b/.github/workflows/kernel-demos.yml @@ -13,6 +13,10 @@ jobs: name: WIN32 MSVC runs-on: windows-latest steps: + - name: Enable long paths on Windows + if: runner.os == 'Windows' + run: git config --system core.longpaths true + - name: Checkout the FreeRTOS/FreeRTOS Repository uses: actions/checkout@v4.1.1 with: @@ -42,6 +46,10 @@ jobs: name: WIN32 MingW runs-on: windows-latest steps: + - name: Enable long paths on Windows + if: runner.os == 'Windows' + run: git config --system core.longpaths true + - name: Checkout the FreeRTOS/FreeRTOS Repository uses: actions/checkout@v4.1.1 with: diff --git a/CMakeLists.txt b/CMakeLists.txt index 914333746..86471b775 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -25,7 +25,7 @@ if(NOT TARGET freertos_config ) " INTERFACE\n" " include) # The config file directory\n" " target_compile_definitions(freertos_config\n" - " PUBLIC\n" + " INTERFACE\n" " projCOVERAGE_TEST=0)\n") else() message(WARNING " Using deprecated 'FREERTOS_CONFIG_FILE_DIRECTORY' - please update your project CMakeLists.txt file:\n" @@ -34,7 +34,7 @@ if(NOT TARGET freertos_config ) " INTERFACE\n" " include) # The config file directory\n" " target_compile_definitions(freertos_config\n" - " PUBLIC\n" + " INTERFACE\n" " projCOVERAGE_TEST=0)\n") endif() endif() diff --git a/FreeRTOS-Kernel-V11.3.0-repository-SPDX2.3.spdx b/FreeRTOS-Kernel-V11.3.0-repository-SPDX2.3.spdx deleted file mode 100644 index b79bef661..000000000 --- a/FreeRTOS-Kernel-V11.3.0-repository-SPDX2.3.spdx +++ /dev/null @@ -1,6230 +0,0 @@ -## Document Information -SPDXVersion: SPDX-2.3 -DataLicense: CC0-1.0 -SPDXID: SPDXRef-DOCUMENT -DocumentName: FreeRTOS-Kernel V11.3.0 repository SBOM -DocumentNamespace: https://github.com/FreeRTOS/FreeRTOS-Kernel/releases/download/11.3.0/FreeRTOS-Kernel-V11.3.0-repository-SPDX2.3.spdx - -## Creation Information -Creator: Tool: sbom-generator -Creator: Organization: Amazon Web Services, Inc. -Created: 2026-03-30T23:50:05Z - -## Package Information -PackageName: FreeRTOS-Kernel -SPDXID: SPDXRef-Package -PackageVersion: V11.3.0 -PackageDownloadLocation: git+https://github.com/FreeRTOS/FreeRTOS-Kernel.git@11.3.0 -FilesAnalyzed: true -PackageVerificationCode: 719092a897757522424a344a1711af2a128e14ce -PackageHomePage: https://github.com/FreeRTOS/FreeRTOS-Kernel -PackageSourceInfo: The package verification code was generated from the repository being cloned with --recurse-submodules. -PackageLicenseConcluded: Apache-2.0 AND BSD-3-Clause AND MIT -PackageLicenseDeclared: MIT -PackageDescription: FreeRTOS Kernel. - -## File Information -FileName: ./stream_buffer.c -SPDXID: SPDXRef-File-1 -FileChecksum: SHA1: 9aff5a84ffc6948288c7d283e3a72b588b113959 -LicenseConcluded: MIT -FileCopyrightText: Copyright (C) 2021 Amazon.com, Inc. or its affiliates. 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All Rights Reserved. - ./portable/ThirdParty/GCC/ARC_EM_HS/port.c - MIT - - - SPDXRef-File-108 - - SHA1 - 0759987beb68fdd9823992ca9cf1339dd478177c - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S - MIT - - - SPDXRef-File-109 - - SHA1 - 8d61fb9862ede5c199117506022a70c3e2e7552c - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c - MIT - - - SPDXRef-File-110 - - SHA1 - 82381398311a146ad226612b884d2d2c6e221fc3 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c - Apache-2.0 - - - SPDXRef-File-111 - - SHA1 - 2795a86fece6cf49d75f262d27d8356c341b7a76 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S - Apache-2.0 - - - SPDXRef-File-112 - - SHA1 - d9df771315aa1623052ad29a6a590cb50134bc04 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c - MIT - - - SPDXRef-File-113 - - SHA1 - 33a76060e7c12a8f952dbac91e9ad7e17aa805ee - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h - Apache-2.0 - - - SPDXRef-File-114 - - SHA1 - 53e73f1b68dbebe770940c465270e40078540823 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c - Apache-2.0 - - - SPDXRef-File-115 - - SHA1 - 51fed0de72edfa2119b6ef614550f568bbc5ca73 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c - NOASSERTION - - - SPDXRef-File-116 - - SHA1 - 82de1101421f63c007496c392411372c0397c1ed - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S - MIT - - - SPDXRef-File-117 - - SHA1 - 13f7f754fe25a193d66b6817e32d351dade58231 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S - MIT - - - SPDXRef-File-118 - - SHA1 - f582da35aff4f062249eb121d656222e9decd52e - - Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/Xtensa_ESP32/port.c - MIT - - - SPDXRef-File-119 - - SHA1 - 7fcf87f31249861a7c1a4bceb0f0d3946e0f8490 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h - Apache-2.0 - - - SPDXRef-File-120 - - SHA1 - d357f8b209017a2b7dc28555a862ad56cc63f92c - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S - Apache-2.0 - - - SPDXRef-File-121 - - SHA1 - 71ec865f3fc020424b26bc0e6a9a3beb7ade39b4 - - NOASSERTION - ./portable/ThirdParty/GCC/ATmega/readme.md - NOASSERTION - - - SPDXRef-File-122 - - SHA1 - 1136ee2211b69b03febd5aa2ca3a70adb11c0808 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/ATmega/portmacro.h - MIT - - - SPDXRef-File-123 - - SHA1 - 0b46f9fe95c659ae2373d8189d16531035f8f93a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/ATmega/port.c - MIT - - - SPDXRef-File-124 - - SHA1 - 799692789f5108f61156c069ec569742e27d72d2 - - NOASSERTION - ./portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt - NOASSERTION - - - SPDXRef-File-125 - - SHA1 - 46a2e0e43f9810882fb18a24d366f87e9b0ecb17 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h - MIT - - - SPDXRef-File-126 - - SHA1 - 77883d10ec5e648bc3c64a3c28bb489ce01bbf33 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h - Apache-2.0 - - - SPDXRef-File-127 - - SHA1 - 581af014a0bc66c577b1002078b0e57a6c3bf5ec - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h - MIT - - - SPDXRef-File-128 - - SHA1 - 09590b4be6041afc151b2bad05b24f804a37e169 - - Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h - MIT - - - SPDXRef-File-129 - - SHA1 - 3224c6f480593ed587943d28b57762ed89d5ee13 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h - MIT - - - SPDXRef-File-130 - - SHA1 - 51134ee994b251efe162d4132a6e2d2be5c3c456 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h - Apache-2.0 - - - SPDXRef-File-131 - - SHA1 - 34696e7b601d632d03b56c6d178e9ae558e13cf5 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h - MIT - - - SPDXRef-File-132 - - SHA1 - e086501b570dd11705b7f4c378aee507bf938915 - - Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h - MIT - - - SPDXRef-File-133 - - SHA1 - c2bc7505a847a82fd1db6f80690e652c026e5480 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h - MIT - - - SPDXRef-File-134 - - SHA1 - 03c2d625715bf67450017c182defe1dd483c0df9 - - NOASSERTION - ./portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h - MIT - - - SPDXRef-File-135 - - SHA1 - a46be77cd9ed23ea973e60b5747d3088f79a2da1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/Posix/utils/wait_for_event.c - MIT - - - SPDXRef-File-136 - - SHA1 - 47534f6d965b78479a6e157f4ed15f775acae940 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/Posix/utils/wait_for_event.h - MIT - - - SPDXRef-File-137 - - SHA1 - b932f7844d306d0df788365e1becc1dc93d032bd - - Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h - BSD-3-Clause - - - SPDXRef-File-138 - - SHA1 - 067025166392447e041d20da52e954139f825ada - - Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/RP2040/include/portmacro.h - MIT - - - SPDXRef-File-139 - - SHA1 - 9c95f7ef44f4c0d5b46181fe23d9146cb9be3217 - - Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ThirdParty/GCC/RP2040/include/rp2040_config.h - MIT - - - SPDXRef-File-140 - - SHA1 - 32100bfc4be2ab31275f5ac5b1950e125b802e7b - - Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. - ./portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h - MIT - - - SPDXRef-File-141 - - SHA1 - 505ca4364ba05965d796d88547d32329b4062390 - - Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. - ./portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S - MIT - - - SPDXRef-File-142 - - SHA1 - c6b49a067c84f32d2005d53ef925d9b014567c94 - - Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. - ./portable/ThirdParty/CDK/T-HEAD_CK802/port.c - MIT - - - SPDXRef-File-143 - - SHA1 - 1396cba3744281c635c7699e8015622d7849ea9d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MikroC/ARM_CM4F/portmacro.h - MIT - - - SPDXRef-File-144 - - SHA1 - 70b2a0759ace9a302e9e1a7732215bd47f98c1bb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MikroC/ARM_CM4F/port.c - MIT - - - SPDXRef-File-145 - - SHA1 - 1833d687eeffabb051475e8ffbda846fa34b6a04 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MZ/ISR_Support.h - MIT - - - SPDXRef-File-146 - - SHA1 - f1ac03d2554303b95f6598c98d92d35b7b68093d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MZ/portmacro.h - MIT - - - SPDXRef-File-147 - - SHA1 - 30f7ae5b8e4b7242f67d8e389c712062b49c49e5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MZ/port.c - MIT - - - SPDXRef-File-148 - - SHA1 - f13a83148ee75610d080ebf184d30cd47001eb92 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MZ/port_asm.S - MIT - - - SPDXRef-File-149 - - SHA1 - e36f417c3d02b4f369cab0de05b665ce4c50cd39 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MX/ISR_Support.h - MIT - - - SPDXRef-File-150 - - SHA1 - 6802de5e2f60e50d56ace85a583fbcbc3e05ee83 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MX/portmacro.h - MIT - - - SPDXRef-File-151 - - SHA1 - 9dc04419f82ab898f2f95830cb6318aa2b08f64e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MX/port.c - MIT - - - SPDXRef-File-152 - - SHA1 - e6e9ac4f3720b1a6a6f9c3c119fb91a6b8270e78 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MX/port_asm.S - MIT - - - SPDXRef-File-153 - - SHA1 - da39a3ee5e6b4b0d3255bfef95601890afd80709 - - NOASSERTION - ./portable/MPLAB/PIC18F/stdio.h - NOASSERTION - - - SPDXRef-File-154 - - SHA1 - 2954238d210fab16fda395027c54f45f23395cd7 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC18F/portmacro.h - MIT - - - SPDXRef-File-155 - - SHA1 - c2325a19470d735a479572a355e9a9e46a8ea152 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC18F/port.c - MIT - - - SPDXRef-File-156 - - SHA1 - 7205e5d6fdfa3d054063f8c420dbfb817e551832 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S - MIT - - - SPDXRef-File-157 - - SHA1 - 2c5e5b8728e3c427bc6d1dc784bf992809f6a4e0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC24_dsPIC/portmacro.h - MIT - - - SPDXRef-File-158 - - SHA1 - 97407c9d10c21fca0d828602b48ca96342a01d87 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC24_dsPIC/port.c - MIT - - - SPDXRef-File-159 - - SHA1 - 2051c7d9db262797b5c80cf858a90550cfbdc331 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S - MIT - - - SPDXRef-File-160 - - SHA1 - 34d488d89f0557f6acc303788b09659869399658 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MEC14xx/ISR_Support.h - MIT - - - SPDXRef-File-161 - - SHA1 - 1a0b798ae88d5b7d4a38e8e8fdfb3226b584358e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MEC14xx/portmacro.h - MIT - - - SPDXRef-File-162 - - SHA1 - 946d2e00d6e77fb85de8037981e12011e4fff533 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MEC14xx/port.c - MIT - - - SPDXRef-File-163 - - SHA1 - 54abacd45cf756af2eb62459b8fbe729880e2445 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/MPLAB/PIC32MEC14xx/port_asm.S - MIT - - - SPDXRef-File-164 - - SHA1 - 70d7afcceed549e5c2dbb45ebf3b5355afc8f5ae - - NOASSERTION - ./portable/ARMv8M/secure/ReadMe.txt - NOASSERTION - - - SPDXRef-File-165 - - SHA1 - 70d7afcceed549e5c2dbb45ebf3b5355afc8f5ae - - NOASSERTION - ./portable/ARMv8M/non_secure/ReadMe.txt - NOASSERTION - - - SPDXRef-File-166 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-167 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/port.c - MIT - - - SPDXRef-File-168 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portasm.h - MIT - - - SPDXRef-File-169 - - SHA1 - 5467869f595c355ca5cd2558fa23fa8b7b463f06 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h - MIT - - - SPDXRef-File-170 - - SHA1 - eaf6f2e8dc05dc195e80e31f424a0406fa171291 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h - MIT - - - SPDXRef-File-171 - - SHA1 - 3116e01bcd409ee990e7d7ad21178bc3b3347015 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h - MIT - - - SPDXRef-File-172 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-173 - - SHA1 - fc426db137af5159a90dce64724708f4da5d2c49 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h - MIT - - - SPDXRef-File-174 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s - MIT - - - SPDXRef-File-175 - - SHA1 - a5bd3d2298d36124c76fa002757d5872cfd57b03 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-176 - - SHA1 - afd53177c067e21294c878058b9447f753bc133a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h - MIT - - - SPDXRef-File-177 - - SHA1 - 2817bb68d12e9428a66fbed3b76c5ebb63d49923 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s - MIT - - - SPDXRef-File-178 - - SHA1 - d4ee3bdccc76e179d3eeade9942d79348a4dcfdd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h - MIT - - - SPDXRef-File-179 - - SHA1 - a5bd3d2298d36124c76fa002757d5872cfd57b03 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-180 - - SHA1 - afd53177c067e21294c878058b9447f753bc133a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h - MIT - - - SPDXRef-File-181 - - SHA1 - 5ce90aadb349b87b34592ed5ccfd1600a73d5c78 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s - MIT - - - SPDXRef-File-182 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-183 - - SHA1 - fc426db137af5159a90dce64724708f4da5d2c49 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h - MIT - - - SPDXRef-File-184 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s - MIT - - - SPDXRef-File-185 - - SHA1 - acdb03138085ee730b8de11f66be84784f654da1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h - MIT - - - SPDXRef-File-186 - - SHA1 - 80db952dbdf457088e07814b3dd036d3bc5cae7b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h - MIT - - - SPDXRef-File-187 - - SHA1 - 791a8d0ec284343d92cbe7fd79808d24302b847d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h - MIT - - - SPDXRef-File-188 - - SHA1 - e06005b54cbc757e1c3eadb192063ac2dabff4df - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h - MIT - - - SPDXRef-File-189 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-190 - - SHA1 - 28f07bd406f46fb42aa197fcf0afd0a2483a820b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h - MIT - - - SPDXRef-File-191 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c - MIT - - - SPDXRef-File-192 - - SHA1 - f3483ef423d1e0b5c02b484ac9e7a5c9a686d158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-193 - - SHA1 - 5c85e2a198183e1323d2336dcdb5eafbee255728 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h - MIT - - - SPDXRef-File-194 - - SHA1 - 39466b68bd1963d8c679d7e87a2d03e1e385c00c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c - MIT - - - SPDXRef-File-195 - - SHA1 - 7735f98b36fc191ee55d5bca216c0de62279681d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h - MIT - - - SPDXRef-File-196 - - SHA1 - f3483ef423d1e0b5c02b484ac9e7a5c9a686d158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-197 - - SHA1 - 5c85e2a198183e1323d2336dcdb5eafbee255728 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h - MIT - - - SPDXRef-File-198 - - SHA1 - d5c023e3537339a5a871d80e20d872c701e89fe9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c - MIT - - - SPDXRef-File-199 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-200 - - SHA1 - 28f07bd406f46fb42aa197fcf0afd0a2483a820b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h - MIT - - - SPDXRef-File-201 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c - MIT - - - SPDXRef-File-202 - - SHA1 - 8ff9c9cfa7a1283acae499a9b417d40d52049700 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h - MIT - - - SPDXRef-File-203 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/context/secure_context.c - MIT - - - SPDXRef-File-204 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/context/secure_context.h - MIT - - - SPDXRef-File-205 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/heap/secure_heap.c - MIT - - - SPDXRef-File-206 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/heap/secure_heap.h - MIT - - - SPDXRef-File-207 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/macros/secure_port_macros.h - MIT - - - SPDXRef-File-208 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/init/secure_init.h - MIT - - - SPDXRef-File-209 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/init/secure_init.c - MIT - - - SPDXRef-File-210 - - SHA1 - 86bb923c664cae925e0a784f349cd66ffbc6190d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s - MIT - - - SPDXRef-File-211 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s - MIT - - - SPDXRef-File-212 - - SHA1 - c3d22d9788edd71a064b306083e257eabb811e07 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c - MIT - - - SPDXRef-File-213 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c - MIT - - - SPDXRef-File-214 - - SHA1 - ec5b8680760702596f712547c6355cad8f6f466c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA5_No_GIC/portASM.h - MIT - - - SPDXRef-File-215 - - SHA1 - 14f32ede385873ba7ee2bfccb73da7f7e49b2f2c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA5_No_GIC/portmacro.h - MIT - - - SPDXRef-File-216 - - SHA1 - 91916a36ea7c3f246d6c603f8f1a91b0ec9f6f6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA5_No_GIC/port.c - MIT - - - SPDXRef-File-217 - - SHA1 - e5a7bb5b5e49b785ba4f3adc41f211b22d4856ef - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA5_No_GIC/portASM.s - MIT - - - SPDXRef-File-218 - - SHA1 - 883874cd7df7a85e0a063303f00c3af04695017d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/78K0R/ISR_Support.h - MIT - - - SPDXRef-File-219 - - SHA1 - 1989f9fcfddf09d360129a2e5e294a7b00d9328f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/78K0R/portasm.s26 - MIT - - - SPDXRef-File-220 - - SHA1 - 04c5fdb39c6c33cf703e70f457965fbe7ea28d87 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/78K0R/portmacro.h - MIT - - - SPDXRef-File-221 - - SHA1 - d21122a7270632bf8c94352a95784852adf2a4c1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/78K0R/port.c - MIT - - - SPDXRef-File-222 - - SHA1 - c94bd29d4c2b673048c52db5265b94751ab2f51f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX600/port_asm.s - MIT - - - SPDXRef-File-223 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/IAR/RX600/readme.txt - NOASSERTION - - - SPDXRef-File-224 - - SHA1 - 48e143c08b804003939259113e707f0a2b8f347d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX600/portmacro.h - MIT - - - SPDXRef-File-225 - - SHA1 - d2cb7ddbe407a79afeaaa5bec080c96f191ba726 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX600/port.c - MIT - - - SPDXRef-File-226 - - SHA1 - 16ca5f9845c3f367071b968fda397b2391771ecb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RL78/portmacro.h - MIT - - - SPDXRef-File-227 - - SHA1 - 37cdda6f8471e92372eb5f099af88ce2371bd1b0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RL78/portasm.s - MIT - - - SPDXRef-File-228 - - SHA1 - 64b3e1508ef4691010e7cea08d5e9bc9c2d7efe3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RL78/port.c - MIT - - - SPDXRef-File-229 - - SHA1 - 951332a03d1122c7ba73f617cd91ddecde86e555 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR71x/ISR_Support.h - MIT - - - SPDXRef-File-230 - - SHA1 - 553f48233508f9a8e56722ede221a175e6b49ccd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR71x/portmacro.h - MIT - - - SPDXRef-File-231 - - SHA1 - 710aa708696da8e628cd07121b466b788bfa34d8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR71x/port.c - MIT - - - SPDXRef-File-232 - - SHA1 - 2d530bf3868fd69de83ccf69764fa475b911fefb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR71x/portasm.s79 - MIT - - - SPDXRef-File-233 - - SHA1 - 388748e3188af915d1a5c65122de4b779ffd5cdd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430/portext.s43 - MIT - - - SPDXRef-File-234 - - SHA1 - 1b8f354208fa2ec3621a94ebefbe64312e18b5aa - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430/portmacro.h - MIT - - - SPDXRef-File-235 - - SHA1 - e0bdb1169012a8f82ee2c56881c03180d2173eb6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430/port.c - MIT - - - SPDXRef-File-236 - - SHA1 - d7f3224969f068f439eb6101d657642e11aa3e13 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430/portasm.h - MIT - - - SPDXRef-File-237 - - SHA1 - c039f8e0473b1b87d10973a01386baa35c5ceefc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA9/portASM.h - MIT - - - SPDXRef-File-238 - - SHA1 - 0892865030ec0b708fbedf55e8e30b8dc2e8ca34 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA9/portmacro.h - MIT - - - SPDXRef-File-239 - - SHA1 - 285264c66637bf51c5f4779232004d62657b0dd7 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA9/port.c - MIT - - - SPDXRef-File-240 - - SHA1 - c74e0824e246fcb868d23d1501d5ae8cb6d2fec5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CA9/portASM.s - MIT - - - SPDXRef-File-241 - - SHA1 - 1f842d852e4a8c307ef68221c866c427a24a6ded - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM9XE/ISR_Support.h - MIT - - - SPDXRef-File-242 - - SHA1 - 2461d0fb14385d6689ecd92e4425af8066bac8c2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM9XE/portmacro.h - MIT - - - SPDXRef-File-243 - - SHA1 - 9e514e174577ca949c2858fa76d5d9562d8f0c90 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM9XE/port.c - MIT - - - SPDXRef-File-244 - - SHA1 - 006d9ffd6603d6099354bef9fbe69b2a812a98a6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM9XE/portasm.s79 - MIT - - - SPDXRef-File-245 - - SHA1 - 951332a03d1122c7ba73f617cd91ddecde86e555 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR75x/ISR_Support.h - MIT - - - SPDXRef-File-246 - - SHA1 - 6276ba2c63dd94e153753411cdb008938a8492a7 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR75x/portmacro.h - MIT - - - SPDXRef-File-247 - - SHA1 - db525b590b0fdb582027130733770cf5f0c03643 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR75x/port.c - MIT - - - SPDXRef-File-248 - - SHA1 - e5fb596745f9bb85b089e76ab42a85988cea1a70 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR75x/portasm.s79 - MIT - - - SPDXRef-File-249 - - SHA1 - 0152bf77a66f703c3e3690ff4cdfde2cf45584c1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM3/portmacro.h - MIT - - - SPDXRef-File-250 - - SHA1 - ff9d1ff113cf6a8b8f54599eba515b4754e3fa55 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM3/portasm.s - MIT - - - SPDXRef-File-251 - - SHA1 - e74c4ace191eb7c775db50f5a75aa04a0f148836 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM3/port.c - MIT - - - SPDXRef-File-252 - - SHA1 - 951332a03d1122c7ba73f617cd91ddecde86e555 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/LPC2000/ISR_Support.h - MIT - - - SPDXRef-File-253 - - SHA1 - e3450a332ff24f2211ec50870ca2cac7e0c71ce9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/LPC2000/portmacro.h - MIT - - - SPDXRef-File-254 - - SHA1 - 56eac93dc61de943e824fc5ac88114fffdbd5cc0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/LPC2000/port.c - MIT - - - SPDXRef-File-255 - - SHA1 - 0673f2157e9044d593ff06391c1e4e2df215c86c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/LPC2000/portasm.s79 - MIT - - - SPDXRef-File-256 - - SHA1 - 951332a03d1122c7ba73f617cd91ddecde86e555 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM7S64/ISR_Support.h - MIT - - - SPDXRef-File-257 - - SHA1 - d9b1dace3467e5de556f18b0dd7a9da5ba7b1420 - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h - NOASSERTION - - - SPDXRef-File-258 - - SHA1 - 0137385290b2d5dd64b6c45ca98644f38717267e - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h - NOASSERTION - - - SPDXRef-File-259 - - SHA1 - 9bc1ba0b952002fe25107eaef59ded23fa4b0e67 - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/AT91SAM7S64.h - NOASSERTION - - - SPDXRef-File-260 - - SHA1 - aa24f6eef62fea2f4adc76f6134e1d97ff314cbf - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h - NOASSERTION - - - SPDXRef-File-261 - - SHA1 - f58afee0f0faa8c638ccce345f2fa5d11c8a8a74 - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/AT91SAM7X256.h - NOASSERTION - - - SPDXRef-File-262 - - SHA1 - 5da7d15e884522b0ab68a4ba942a528c0424daea - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h - NOASSERTION - - - SPDXRef-File-263 - - SHA1 - db0f6d363f4e3a1632e2f31034ddb2dc283c14cb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM7S64/portmacro.h - MIT - - - SPDXRef-File-264 - - SHA1 - 5093db31874fbe6dc0e3d38026e0ddf6222b8528 - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/AT91SAM7X128.h - NOASSERTION - - - SPDXRef-File-265 - - SHA1 - 18ca9bbd4d78a05b5d96d1319c93e61fe81910c4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM7S64/port.c - MIT - - - SPDXRef-File-266 - - SHA1 - 886773b83461bb3ce54d3e8404bb4e84f25d956b - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h - NOASSERTION - - - SPDXRef-File-267 - - SHA1 - 4ea1af4063fe29debeceb7eab976ab7a50a1512a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AtmelSAM7S64/portasm.s79 - MIT - - - SPDXRef-File-268 - - SHA1 - 935da46260be7dcf2d6a11cbbe7cda14b2ab23e8 - - NOASSERTION - ./portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h - NOASSERTION - - - SPDXRef-File-269 - - SHA1 - 10c67087cc9e97094a9d3d03f3e9ec686a6ec163 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-270 - - SHA1 - 54502862cf3be8a1db7c7ff459afce132657d032 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F_MPU/portmacro.h - MIT - - - SPDXRef-File-271 - - SHA1 - b2f127fffd950d7c0f013961b5c886126d98d9c6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F_MPU/portasm.s - MIT - - - SPDXRef-File-272 - - SHA1 - 297480e492c2b39cb426c07c510e80b965612ad3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F_MPU/port.c - MIT - - - SPDXRef-File-273 - - SHA1 - be3fb7ccd8a19b4083d3323266f5471c10475396 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ATMega323/portmacro.h - MIT - - - SPDXRef-File-274 - - SHA1 - f673a6074c58d2480f28203db0804f40d00c02c1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ATMega323/port.c - MIT - - - SPDXRef-File-275 - - SHA1 - 0abbd75b43863c55fb9d42f036219b2eb17a9d79 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ATMega323/portmacro.s90 - MIT - - - SPDXRef-File-276 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/IAR/RX700v3_DPFPU/readme.txt - NOASSERTION - - - SPDXRef-File-277 - - SHA1 - 23111250a112cf634c4a24ab209cc6339c9f131e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX700v3_DPFPU/portmacro.h - MIT - - - SPDXRef-File-278 - - SHA1 - ba97d13af515323278131e703f19a104ec97e8d0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX700v3_DPFPU/port.c - MIT - - - SPDXRef-File-279 - - SHA1 - ecae9dd9502bdc89f3621d10a54a52b1dfa7e337 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX100/port_asm.s - MIT - - - SPDXRef-File-280 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/IAR/RX100/readme.txt - NOASSERTION - - - SPDXRef-File-281 - - SHA1 - 697c8055341dd0d98dab33e8081ecd4c39e705c0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX100/portmacro.h - MIT - - - SPDXRef-File-282 - - SHA1 - 527a20f438ff8195df0dce7c1f170bd1f9aeea71 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RX100/port.c - MIT - - - SPDXRef-File-283 - - SHA1 - dd61e5d2e6757e5884829fc2c0e4f040cee22a7a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR91x/ISR_Support.h - MIT - - - SPDXRef-File-284 - - SHA1 - 4f9b9778f1c0ac4858040ae3c550f9c4b3aea34d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR91x/portmacro.h - MIT - - - SPDXRef-File-285 - - SHA1 - 27be5aeb7d049fd85c7cdae4c5bfa96682915f4b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR91x/port.c - MIT - - - SPDXRef-File-286 - - SHA1 - fe66c084d7545243f8f14c4b85f417d101910a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/STR91x/portasm.s79 - MIT - - - SPDXRef-File-287 - - SHA1 - 18cabf2ff17bf983de7368804b856e342e2e9198 - - NOASSERTION - ./portable/IAR/ARM_CM7/ReadMe.txt - NOASSERTION - - - SPDXRef-File-288 - - SHA1 - bcbeacd4467f15562ae570bc15ecd9109e182b9f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CRx_No_GIC/portmacro.h - MIT - - - SPDXRef-File-289 - - SHA1 - 9176fa24897841ba15d2e28dd73e7bbabdec2bbd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CRx_No_GIC/port.c - MIT - - - SPDXRef-File-290 - - SHA1 - c668e6bf09b6e21b7af7817a15d5188072893098 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CRx_No_GIC/portASM.s - MIT - - - SPDXRef-File-291 - - SHA1 - d571576934a63a5ba83ef22014a6eac566b1c584 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430X/portext.s43 - MIT - - - SPDXRef-File-292 - - SHA1 - 71554fa3af3ff47eeb8cb5265d79d7b015a4baa8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430X/data_model.h - MIT - - - SPDXRef-File-293 - - SHA1 - 38b91021595924efadc0a698fdc82b41108e7dde - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430X/portmacro.h - MIT - - - SPDXRef-File-294 - - SHA1 - 8193f9b594a5f7a48a6bc37af230f15aaf6313a2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/MSP430X/port.c - MIT - - - SPDXRef-File-295 - - SHA1 - 433a7d5096eea61850b808819fa30c2ea5124951 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR32_UC3/portmacro.h - MIT - - - SPDXRef-File-296 - - SHA1 - 369314614fd4ff145ed4bd6b2dd33d7d22fd88d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR32_UC3/read.c - MIT - - - SPDXRef-File-297 - - SHA1 - 8ce9b01e624e20974004da50533e25b1070635d0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR32_UC3/exception.s82 - MIT - - - SPDXRef-File-298 - - SHA1 - c69575b928e4f759865ce81fa07f8a6920258aea - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR32_UC3/port.c - MIT - - - SPDXRef-File-299 - - SHA1 - 7e8b74b7c9042e9c8939a37ef5909761b41489f2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR32_UC3/write.c - MIT - - - SPDXRef-File-300 - - SHA1 - 11123d2bba003644ac4591b4305a8eb47c8b2dcb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RXv2/port_asm.s - MIT - - - SPDXRef-File-301 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/IAR/RXv2/readme.txt - NOASSERTION - - - SPDXRef-File-302 - - SHA1 - 2dcce100310c8e278abcd92fd107f4bbe05bd258 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RXv2/portmacro.h - MIT - - - SPDXRef-File-303 - - SHA1 - e2c6d57419990c2527244ed7f028db1dc1d3e82c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RXv2/port.c - MIT - - - SPDXRef-File-304 - - SHA1 - 872d1027199898c5ea98f78d16f723365b83fc92 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/V850ES/portasm_Hx2.s85 - MIT - - - SPDXRef-File-305 - - SHA1 - f4385cd968640f15d0131288a439593afc43e0d3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/V850ES/ISR_Support.h - MIT - - - SPDXRef-File-306 - - SHA1 - 1d8487cdfc2b63c1d9aae055776bce36a3307d33 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/V850ES/portasm_Fx3.s85 - MIT - - - SPDXRef-File-307 - - SHA1 - e108927243b5f34033412c0eda8a2ee3afbb298a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/V850ES/portmacro.h - MIT - - - SPDXRef-File-308 - - SHA1 - 7b17ed0a4bda8501ec1a429823be50e1185a9aaa - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/V850ES/port.c - MIT - - - SPDXRef-File-309 - - SHA1 - bd8bdb215101f6f99aa3dfd9af319016e7f3c142 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/V850ES/portasm.s85 - MIT - - - SPDXRef-File-310 - - SHA1 - e24a05a23e988d5f78eef7364ea9a0f816712d14 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_Mega0/porthardware.h - MIT - - - SPDXRef-File-311 - - SHA1 - 6db9ae8acad11fa910977ced5aa47fcd6b6b60ae - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_Mega0/portmacro.h - MIT - - - SPDXRef-File-312 - - SHA1 - 40ce2ce683e7aab0b398e6d3992dde912f4d6fc8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_Mega0/port.c - MIT - - - SPDXRef-File-313 - - SHA1 - c1a53ce841ec951ca3ab074e0b7127d521cfa2cf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_Mega0/portmacro.s90 - MIT - - - SPDXRef-File-314 - - SHA1 - df76a11f8e4820ce37710caacd3c6f73d5d915cb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM0/portmacro.h - MIT - - - SPDXRef-File-315 - - SHA1 - 3377d9d477e22a1bd3dc390ed7865f388ad53500 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM0/portasm.s - MIT - - - SPDXRef-File-316 - - SHA1 - f2b7442a12f652e0352cc9932c00f5f3e7135375 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM0/port.c - MIT - - - SPDXRef-File-317 - - SHA1 - b9a1211dff8b674e501b8c2567f5f1a92d5d1283 - - NOASSERTION - ./portable/IAR/RISC-V/Documentation.url - NOASSERTION - - - SPDXRef-File-318 - - SHA1 - 00dbb5b030777c4fff5d8fcfcb9a52d7f3c90e24 - - NOASSERTION - ./portable/IAR/RISC-V/chip_extensions.cmake - NOASSERTION - - - SPDXRef-File-319 - - SHA1 - 35e88a2394be58f0d3abb023cc1998169a368d11 - - NOASSERTION - ./portable/IAR/RISC-V/readme.txt - NOASSERTION - - - SPDXRef-File-320 - - SHA1 - 70a86e61e328139f0e99b79d9d605749f3af19f3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RISC-V/portmacro.h - MIT - - - SPDXRef-File-321 - - SHA1 - 04974a2ae0815eff1f459e7a45f1d2babaabc2e6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RISC-V/portContext.h - MIT - - - SPDXRef-File-322 - - SHA1 - ba2859bf0694d1dbcef321e8402f63daa54f8fca - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RISC-V/port.c - MIT - - - SPDXRef-File-323 - - SHA1 - d4e241558aa07075e7d840b0a655cbfd0942539c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RISC-V/portASM.s - MIT - - - SPDXRef-File-324 - - SHA1 - 89e6689f28671f49149cc11541457235724d5569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_AVRDx/porthardware.h - MIT - - - SPDXRef-File-325 - - SHA1 - 6db9ae8acad11fa910977ced5aa47fcd6b6b60ae - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_AVRDx/portmacro.h - MIT - - - SPDXRef-File-326 - - SHA1 - 7ccec3662d68869bf70907c4c344eebe930ef79d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_AVRDx/port.c - MIT - - - SPDXRef-File-327 - - SHA1 - 5ec86d81ba7ab9863e4ded4cc7a94e272944f197 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/AVR_AVRDx/portmacro.s90 - MIT - - - SPDXRef-File-328 - - SHA1 - a8d576f2c8c061980ad480f9c8393b69e9dc99c8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F/portmacro.h - MIT - - - SPDXRef-File-329 - - SHA1 - 68a36df7e3b8be9605f1963a20bcc161034768a1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F/portasm.s - MIT - - - SPDXRef-File-330 - - SHA1 - bd8943992a1370b2dfd27faafdfd066b7bb2151f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM4F/port.c - MIT - - - SPDXRef-File-331 - - SHA1 - 35e88a2394be58f0d3abb023cc1998169a368d11 - - NOASSERTION - ./portable/IAR/RISC-V/chip_specific_extensions/readme.txt - NOASSERTION - - - SPDXRef-File-332 - - SHA1 - bf91ffe657588b7c4a280d20159271a1a1c4fe39 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h - MIT - - - SPDXRef-File-333 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_context.c - MIT - - - SPDXRef-File-334 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_init.h - MIT - - - SPDXRef-File-335 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-336 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_context.h - MIT - - - SPDXRef-File-337 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_heap.c - MIT - - - SPDXRef-File-338 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_init.c - MIT - - - SPDXRef-File-339 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_port_macros.h - MIT - - - SPDXRef-File-340 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/secure/secure_heap.h - MIT - - - SPDXRef-File-341 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-342 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-343 - - SHA1 - acdb03138085ee730b8de11f66be84784f654da1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/non_secure/portmacro.h - MIT - - - SPDXRef-File-344 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/non_secure/portasm.s - MIT - - - SPDXRef-File-345 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/non_secure/port.c - MIT - - - SPDXRef-File-346 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55/non_secure/portasm.h - MIT - - - SPDXRef-File-347 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-348 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-349 - - SHA1 - acdb03138085ee730b8de11f66be84784f654da1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-350 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-351 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-352 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-353 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_context.c - MIT - - - SPDXRef-File-354 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_init.h - MIT - - - SPDXRef-File-355 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-356 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_context.h - MIT - - - SPDXRef-File-357 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_heap.c - MIT - - - SPDXRef-File-358 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_init.c - MIT - - - SPDXRef-File-359 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_port_macros.h - MIT - - - SPDXRef-File-360 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/secure/secure_heap.h - MIT - - - SPDXRef-File-361 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-362 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-363 - - SHA1 - fc426db137af5159a90dce64724708f4da5d2c49 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/non_secure/portmacro.h - MIT - - - SPDXRef-File-364 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/non_secure/portasm.s - MIT - - - SPDXRef-File-365 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/non_secure/port.c - MIT - - - SPDXRef-File-366 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33/non_secure/portasm.h - MIT - - - SPDXRef-File-367 - - SHA1 - 1a225262119568ac34db2b1b813b0e5ac081222c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM7/r0p1/portmacro.h - MIT - - - SPDXRef-File-368 - - SHA1 - 34cdb5f62912886701ad6458ca540ef48ee6d216 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM7/r0p1/portasm.s - MIT - - - SPDXRef-File-369 - - SHA1 - c7b206fcb83eb6e0be836137e9da7e47f395f314 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM7/r0p1/port.c - MIT - - - SPDXRef-File-370 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-371 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-372 - - SHA1 - 3116e01bcd409ee990e7d7ad21178bc3b3347015 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-373 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-374 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-375 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-376 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_context.c - MIT - - - SPDXRef-File-377 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_init.h - MIT - - - SPDXRef-File-378 - - SHA1 - 86bb923c664cae925e0a784f349cd66ffbc6190d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-379 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_context.h - MIT - - - SPDXRef-File-380 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_heap.c - MIT - - - SPDXRef-File-381 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_init.c - MIT - - - SPDXRef-File-382 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_port_macros.h - MIT - - - SPDXRef-File-383 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/secure/secure_heap.h - MIT - - - SPDXRef-File-384 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-385 - - SHA1 - a5bd3d2298d36124c76fa002757d5872cfd57b03 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-386 - - SHA1 - afd53177c067e21294c878058b9447f753bc133a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/non_secure/portmacro.h - MIT - - - SPDXRef-File-387 - - SHA1 - 5ce90aadb349b87b34592ed5ccfd1600a73d5c78 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/non_secure/portasm.s - MIT - - - SPDXRef-File-388 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/non_secure/port.c - MIT - - - SPDXRef-File-389 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23/non_secure/portasm.h - MIT - - - SPDXRef-File-390 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-391 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-392 - - SHA1 - d4ee3bdccc76e179d3eeade9942d79348a4dcfdd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-393 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-394 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-395 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-396 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-397 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-398 - - SHA1 - 5467869f595c355ca5cd2558fa23fa8b7b463f06 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-399 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-400 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-401 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-402 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_context.c - MIT - - - SPDXRef-File-403 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_init.h - MIT - - - SPDXRef-File-404 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-405 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_context.h - MIT - - - SPDXRef-File-406 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_heap.c - MIT - - - SPDXRef-File-407 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_init.c - MIT - - - SPDXRef-File-408 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_port_macros.h - MIT - - - SPDXRef-File-409 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/secure/secure_heap.h - MIT - - - SPDXRef-File-410 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-411 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-412 - - SHA1 - d4ee3bdccc76e179d3eeade9942d79348a4dcfdd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/non_secure/portmacro.h - MIT - - - SPDXRef-File-413 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/non_secure/portasm.s - MIT - - - SPDXRef-File-414 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/non_secure/port.c - MIT - - - SPDXRef-File-415 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM85/non_secure/portasm.h - MIT - - - SPDXRef-File-416 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-417 - - SHA1 - a5bd3d2298d36124c76fa002757d5872cfd57b03 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-418 - - SHA1 - afd53177c067e21294c878058b9447f753bc133a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-419 - - SHA1 - 2817bb68d12e9428a66fbed3b76c5ebb63d49923 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-420 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-421 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-422 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-423 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-424 - - SHA1 - fc426db137af5159a90dce64724708f4da5d2c49 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-425 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-426 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-427 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-428 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_context.c - MIT - - - SPDXRef-File-429 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_init.h - MIT - - - SPDXRef-File-430 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-431 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_context.h - MIT - - - SPDXRef-File-432 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_heap.c - MIT - - - SPDXRef-File-433 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_init.c - MIT - - - SPDXRef-File-434 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_port_macros.h - MIT - - - SPDXRef-File-435 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/secure/secure_heap.h - MIT - - - SPDXRef-File-436 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-437 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-438 - - SHA1 - 3116e01bcd409ee990e7d7ad21178bc3b3347015 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/non_secure/portmacro.h - MIT - - - SPDXRef-File-439 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/non_secure/portasm.s - MIT - - - SPDXRef-File-440 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/non_secure/port.c - MIT - - - SPDXRef-File-441 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM35P/non_secure/portasm.h - MIT - - - SPDXRef-File-442 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_context.c - MIT - - - SPDXRef-File-443 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_init.h - MIT - - - SPDXRef-File-444 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-445 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_context.h - MIT - - - SPDXRef-File-446 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_heap.c - MIT - - - SPDXRef-File-447 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_init.c - MIT - - - SPDXRef-File-448 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h - MIT - - - SPDXRef-File-449 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/secure/secure_heap.h - MIT - - - SPDXRef-File-450 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-451 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-452 - - SHA1 - eaf6f2e8dc05dc195e80e31f424a0406fa171291 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h - MIT - - - SPDXRef-File-453 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/non_secure/portasm.s - MIT - - - SPDXRef-File-454 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/non_secure/port.c - MIT - - - SPDXRef-File-455 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3/non_secure/portasm.h - MIT - - - SPDXRef-File-456 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_context.c - MIT - - - SPDXRef-File-457 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_init.h - MIT - - - SPDXRef-File-458 - - SHA1 - bf4e10f1ec1268cd572029ab73357a96d0c435d5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_context_port_asm.s - MIT - - - SPDXRef-File-459 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_context.h - MIT - - - SPDXRef-File-460 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_heap.c - MIT - - - SPDXRef-File-461 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_init.c - MIT - - - SPDXRef-File-462 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_port_macros.h - MIT - - - SPDXRef-File-463 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/secure/secure_heap.h - MIT - - - SPDXRef-File-464 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-465 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-466 - - SHA1 - 5467869f595c355ca5cd2558fa23fa8b7b463f06 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/non_secure/portmacro.h - MIT - - - SPDXRef-File-467 - - SHA1 - 89e129a39381b8f4425220e4aa424a98cbf5b6fc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/non_secure/portasm.s - MIT - - - SPDXRef-File-468 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/non_secure/port.c - MIT - - - SPDXRef-File-469 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_CM52/non_secure/portasm.h - MIT - - - SPDXRef-File-470 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-471 - - SHA1 - e38a9d692e8fb165b3dc4be2fad668b19b9ac569 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-472 - - SHA1 - eaf6f2e8dc05dc195e80e31f424a0406fa171291 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-473 - - SHA1 - 9c250853d64966f05fc221969678a31928ba4d0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s - MIT - - - SPDXRef-File-474 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-475 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-476 - - SHA1 - c70647c7682193555c1cdcce3d1d6ac4116039fb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/CCRH/F1Kx/portmacro.h - MIT - - - SPDXRef-File-477 - - SHA1 - 5dd9a5cbae0e842f69d8e408619adb5130d8dcce - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/CCRH/F1Kx/portasm.s - MIT - - - SPDXRef-File-478 - - SHA1 - 3a1495b5683982ce8345990f8a1faaf77881e387 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/CCRH/F1Kx/port.c - MIT - - - SPDXRef-File-479 - - SHA1 - fd06f580c4370fca3b4dcb60b3325f85c1f70136 - - NOASSERTION - ./portable/CCRH/F1Kx/README.md - NOASSERTION - - - SPDXRef-File-480 - - SHA1 - b05c3492072d7d62e34aca5599159f99b2020b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/BCC/16BitDOS/common/portasm.h - MIT - - - SPDXRef-File-481 - - SHA1 - 6b304a1ca669c3ae747a222e01f239a0fbdbb60d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/BCC/16BitDOS/common/portcomn.c - MIT - - - SPDXRef-File-482 - - SHA1 - fe20ef926076cb3d031798dce041a3e891841846 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/BCC/16BitDOS/Flsh186/prtmacro.h - MIT - - - SPDXRef-File-483 - - SHA1 - d58bad5e0037c8d63857233034cb74c1d747700a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/BCC/16BitDOS/Flsh186/port.c - MIT - - - SPDXRef-File-484 - - SHA1 - c77a978528672ff7ff566c54c5dceb56b36006d2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/BCC/16BitDOS/PC/prtmacro.h - MIT - - - SPDXRef-File-485 - - SHA1 - ddbbfc7d83dbab3def87b5b6f8aac29e74f15fba - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/BCC/16BitDOS/PC/port.c - MIT - - - SPDXRef-File-486 - - SHA1 - ee44162f4f89bd840a989fd50d91489358b8feda - - NOASSERTION - ./portable/WizC/PIC18/Install.bat - NOASSERTION - - - SPDXRef-File-487 - - SHA1 - 193a0808793c76eaaafe19a4ef5998a1df0fc43a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/WizC/PIC18/addFreeRTOS.h - MIT - - - SPDXRef-File-488 - - SHA1 - e9a20ba52f14a0d0bc9ddd0da17c9ef0fdc65916 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/WizC/PIC18/portmacro.h - MIT - - - SPDXRef-File-489 - - SHA1 - b227e02355c517456ffd1c4319955bfa41a5b089 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/WizC/PIC18/port.c - MIT - - - SPDXRef-File-490 - - SHA1 - f7eb58a2e09fd0e7d9851953b5b0d9eb55ee673e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/WizC/PIC18/Drivers/Tick/isrTick.c - MIT - - - SPDXRef-File-491 - - SHA1 - ed77a881df9527c406e33415252e5e1b3f451a4d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/WizC/PIC18/Drivers/Tick/Tick.c - MIT - - - SPDXRef-File-492 - - SHA1 - 6fe110813944487cd7aee50475b5a961746f8363 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/SDCC/Cygnal/portmacro.h - MIT - - - SPDXRef-File-493 - - SHA1 - 2d97571f39fd8ccea2c682c8c23cbc70beba8ca4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/SDCC/Cygnal/port.c - MIT - - - SPDXRef-File-494 - - SHA1 - 156148a5d5b1a849e3ae086444e78f99e6b2bf30 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Tasking/ARM_CM4F/port_asm.asm - MIT - - - SPDXRef-File-495 - - SHA1 - a995cc92503f7a97019cb7dac4482e6d722d8bcf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Tasking/ARM_CM4F/portmacro.h - MIT - - - SPDXRef-File-496 - - SHA1 - 187c25af1f4969e51f7fce99ff9a7220ea941e76 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Tasking/ARM_CM4F/port.c - MIT - - - SPDXRef-File-497 - - SHA1 - eee12a54801240a9534565a2996e5eb077c9c286 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/H8S2329/portmacro.h - MIT - - - SPDXRef-File-498 - - SHA1 - f13767152b2bce75380b1cd05989e499a7f58648 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/H8S2329/port.c - MIT - - - SPDXRef-File-499 - - SHA1 - f00ff69806624db8150c891c772888b8b29f0972 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX200/portmacro.h - MIT - - - SPDXRef-File-500 - - SHA1 - 58e4d8514097ce148b47a485ded346cdee6f43f3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX200/port.c - MIT - - - SPDXRef-File-501 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/GCC/RX600v2/readme.txt - NOASSERTION - - - SPDXRef-File-502 - - SHA1 - c2c9d3d68a8ca3a10bff0a08ceaebab4b97551b4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX600v2/portmacro.h - MIT - - - SPDXRef-File-503 - - SHA1 - 30588d826fb923b6b904ca9b74ccd1b55abc1f88 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX600v2/port.c - MIT - - - SPDXRef-File-504 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/GCC/RX600/readme.txt - NOASSERTION - - - SPDXRef-File-505 - - SHA1 - c2c9d3d68a8ca3a10bff0a08ceaebab4b97551b4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX600/portmacro.h - MIT - - - SPDXRef-File-506 - - SHA1 - 43038497b15d02209e9a69ef59ee9b056318dd0c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX600/port.c - MIT - - - SPDXRef-File-507 - - SHA1 - 8f4342acd5afc2c16c599d20cd0067db4d0422ab - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/NiosII/portmacro.h - MIT - - - SPDXRef-File-508 - - SHA1 - 399cefe5512be77fbbd09b503cfe06ba99e1987d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/NiosII/port.c - MIT - - - SPDXRef-File-509 - - SHA1 - adbaae68118d2ce6ddb3b7301473d59b197e7671 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/NiosII/port_asm.S - MIT - - - SPDXRef-File-510 - - SHA1 - f4d0a81019bd7f560b769ff22d78cc18cbacbe2c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RL78/isr_support.h - MIT - - - SPDXRef-File-511 - - SHA1 - c29a235c3ae2bec66354fa4e57a8471129c380e0 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RL78/portmacro.h - MIT - - - SPDXRef-File-512 - - SHA1 - b06a91c0dd325f1e9a902ed6112583ff8b13d55f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RL78/portasm.S - MIT - - - SPDXRef-File-513 - - SHA1 - 4abd4aa82cf9bd2cbac6d624ac8b4f0aaab80c52 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RL78/port.c - MIT - - - SPDXRef-File-514 - - SHA1 - 422f0868aaabe90c54ea426595d837f5c2e70c35 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_AT91FR40008/portISR.c - MIT - - - SPDXRef-File-515 - - SHA1 - 7d6be502db947100184589cb1eadb417b4758dd9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_AT91FR40008/portmacro.h - MIT - - - SPDXRef-File-516 - - SHA1 - b649d7cd8bf80e0b58fe362cf36e745f6ee1a2f9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_AT91FR40008/port.c - MIT - - - SPDXRef-File-517 - - SHA1 - 5d8ff3eea5a78e75614029ef37cd56ada7cf8b8a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CA9/portASM.S - MIT - - - SPDXRef-File-518 - - SHA1 - bf585ae224eb7a3e5b8d0801a7b0cd7ed210cefb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CA9/portmacro.h - MIT - - - SPDXRef-File-519 - - SHA1 - a70e0eb557a7e9ef6604711a0134cb189a0e9e93 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CA9/port.c - MIT - - - SPDXRef-File-520 - - SHA1 - 0496011bf343a85077440bfe45db1183bf036bd8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MSP430F449/portmacro.h - MIT - - - SPDXRef-File-521 - - SHA1 - 0fe05c7f69c3b35aec05a5ca97fa590bce6086b7 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MSP430F449/port.c - MIT - - - SPDXRef-File-522 - - SHA1 - c9b60a219fb535675310f024386aab518677fd0e - - NOASSERTION - ./portable/GCC/ARM_CA53_64_BIT/README.md - NOASSERTION - - - SPDXRef-File-523 - - SHA1 - 674a447de5d87d5100adcf23b107d109d8b2ce27 - - NOASSERTION - ./portable/GCC/ARM_CA53_64_BIT_SRE/README.md - NOASSERTION - - - SPDXRef-File-524 - - SHA1 - 7c6d42909daad880e02fb175a48b60a683dad4fa - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_AT91SAM7S/portISR.c - MIT - - - SPDXRef-File-525 - - SHA1 - 3973413c5770b9f7ac8fbe17ce292b3872b0f27e - - NOASSERTION - ./portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h - NOASSERTION - - - SPDXRef-File-526 - - SHA1 - 6c2419934078293b983a0d3247d1b1e59987bb29 - - NOASSERTION - ./portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h - NOASSERTION - - - SPDXRef-File-527 - - SHA1 - c414ce01ef472e83ba622c7a2c2b4c317b3039ac - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_AT91SAM7S/portmacro.h - MIT - - - SPDXRef-File-528 - - SHA1 - bfb6819c371f68f732dd07a9eacb43e9bfe6ef76 - - NOASSERTION - ./portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c - NOASSERTION - - - SPDXRef-File-529 - - SHA1 - 6b266e078041613f674b6ae55a24255ddd9197ad - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_AT91SAM7S/port.c - MIT - - - SPDXRef-File-530 - - SHA1 - 9c3bf3f197dafaaab16e9ee915470a4aa65e7e10 - - NOASSERTION - ./portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h - NOASSERTION - - - SPDXRef-File-531 - - SHA1 - d9cf69dad03e1953171b073a88fe3a434454a439 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/STR75x/portISR.c - MIT - - - SPDXRef-File-532 - - SHA1 - ebac9132501f634a1ade63e812e9243c35069e4e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/STR75x/portmacro.h - MIT - - - SPDXRef-File-533 - - SHA1 - 83124f4f1fc2407fc8950d3ef065fda0ea659105 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/STR75x/port.c - MIT - - - SPDXRef-File-534 - - SHA1 - ed51ec4231ed113601a5f32524727c3268aee41c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_LPC23xx/portISR.c - MIT - - - SPDXRef-File-535 - - SHA1 - c414ce01ef472e83ba622c7a2c2b4c317b3039ac - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_LPC23xx/portmacro.h - MIT - - - SPDXRef-File-536 - - SHA1 - 3144cd06494dd406eb82b5590e6d5e55ac52c6e9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_LPC23xx/port.c - MIT - - - SPDXRef-File-537 - - SHA1 - dae6540fa160860fa842649767ec6141d83cac6b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM3/portmacro.h - MIT - - - SPDXRef-File-538 - - SHA1 - 2d00378601a4c633ee1cdfc14cdfdf5e9e70276a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM3/port.c - MIT - - - SPDXRef-File-539 - - SHA1 - 2dc76cafc7b7a99842ed79c07215bf3f392653fa - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlaze/portmacro.h - MIT - - - SPDXRef-File-540 - - SHA1 - c4f1b1ddb03cbe925538bf4b949b56e606120a76 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlaze/portasm.s - MIT - - - SPDXRef-File-541 - - SHA1 - 74b5af36181313ee6f61b7be01629cbeadd4b4ec - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlaze/port.c - MIT - - - SPDXRef-File-542 - - SHA1 - c501ddc826f4db2c88e96d43cd4560a97bffb3e2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_AARCH64/portASM.S - MIT - - - SPDXRef-File-543 - - SHA1 - 06b598b2a7c04d745b8a841aec7857991d6b5354 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_AARCH64/portmacro.h - MIT - - - SPDXRef-File-544 - - SHA1 - bd95fee771ec579931a18b1f378f597bb1bb9354 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_AARCH64/port.c - MIT - - - SPDXRef-File-545 - - SHA1 - d642a6afc28b388cc2da97c084b711b65fc08275 - - NOASSERTION - ./portable/GCC/ARM_AARCH64/README.md - NOASSERTION - - - SPDXRef-File-546 - - SHA1 - 5d8593b0b08562235caa833e34497544703bba79 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR5/portASM.S - MIT - - - SPDXRef-File-547 - - SHA1 - 5e2e4c435ebdffe9ff81acda84a72a2c5621ca78 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR5/portmacro.h - MIT - - - SPDXRef-File-548 - - SHA1 - 8739dbebcef8d8319e9d2bfb4c26bf42a145796b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR5/port.c - MIT - - - SPDXRef-File-549 - - SHA1 - d429d17b46f5daceeea18b0f487d2459db46e016 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/CORTUS_APS3/portmacro.h - MIT - - - SPDXRef-File-550 - - SHA1 - c123314e9b83a354ce75cafc8ed35423312ed2b6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/CORTUS_APS3/port.c - MIT - - - SPDXRef-File-551 - - SHA1 - f8b5b30d7e0f216f7646b4bb141f8e3c7f5fb817 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV9/port_exceptions.c - MIT - - - SPDXRef-File-552 - - SHA1 - d8bf9d1e7821240bb9836dd99a3a725290434503 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV9/portmacro.h - MIT - - - SPDXRef-File-553 - - SHA1 - 564e7050bcc9c3b805642d18fcde064343edc6c6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV9/portasm.S - MIT - - - SPDXRef-File-554 - - SHA1 - 667673032f7c4cad153026307e681cca4a420a57 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV9/port.c - MIT - - - SPDXRef-File-555 - - SHA1 - 6b56ec6c6d5181d93959e37e4f18ba9fef7ff5dc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ColdFire_V2/portmacro.h - MIT - - - SPDXRef-File-556 - - SHA1 - 358e6469d04346227aa0263b2fb82a176035d51d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ColdFire_V2/portasm.S - MIT - - - SPDXRef-File-557 - - SHA1 - e2d25ad5ff261c09a1c3273e02763b1cf603e9cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ColdFire_V2/port.c - MIT - - - SPDXRef-File-558 - - SHA1 - f29775b08af1851ff4efebca8dc0927a3cf208e2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC405_Xilinx/FPU_Macros.h - MIT - - - SPDXRef-File-559 - - SHA1 - 1a89f539edf17f666b87b8e6a3acb39cf8d0ad43 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC405_Xilinx/portmacro.h - MIT - - - SPDXRef-File-560 - - SHA1 - a40826a442cd15915f3d4db056ae71639180ef70 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC405_Xilinx/portasm.S - MIT - - - SPDXRef-File-561 - - SHA1 - ffd62aadec1b0858dac19e9c889f4075c2193c40 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC405_Xilinx/port.c - MIT - - - SPDXRef-File-562 - - SHA1 - a9fb368620ad5d56ccb5c460b27e5c148a135c93 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_AARCH64_SRE/portASM.S - MIT - - - SPDXRef-File-563 - - SHA1 - f5e2699b38f2dac2b083594fd74a12dfd42b07bb - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_AARCH64_SRE/portmacro.h - MIT - - - SPDXRef-File-564 - - SHA1 - 553875487cacf3ba66c9231fb05ffb1c540734e2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_AARCH64_SRE/port.c - MIT - - - SPDXRef-File-565 - - SHA1 - 971b1b28dcdd83324ebd780fd235a662a4232a4e - - NOASSERTION - ./portable/GCC/ARM_AARCH64_SRE/README.md - NOASSERTION - - - SPDXRef-File-566 - - SHA1 - fe92a59dc08376f02f95a60ae589e68b79cc0423 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ATMega323/portmacro.h - MIT - - - SPDXRef-File-567 - - SHA1 - 55ae0064788569b83b68bf66cc5c8216a82ec87c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ATMega323/port.c - MIT - - - SPDXRef-File-568 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/GCC/RX700v3_DPFPU/readme.txt - NOASSERTION - - - SPDXRef-File-569 - - SHA1 - e7940d0bb9ddee20ce6c27e15ab0077c7a65cbcd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX700v3_DPFPU/portmacro.h - MIT - - - SPDXRef-File-570 - - SHA1 - d677316556576bfbdb83cfe8b71a000801d2e85d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX700v3_DPFPU/port.c - MIT - - - SPDXRef-File-571 - - SHA1 - f29775b08af1851ff4efebca8dc0927a3cf208e2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC440_Xilinx/FPU_Macros.h - MIT - - - SPDXRef-File-572 - - SHA1 - 1a89f539edf17f666b87b8e6a3acb39cf8d0ad43 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC440_Xilinx/portmacro.h - MIT - - - SPDXRef-File-573 - - SHA1 - a40826a442cd15915f3d4db056ae71639180ef70 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC440_Xilinx/portasm.S - MIT - - - SPDXRef-File-574 - - SHA1 - 5edc3861e6fe5fd3f8f6757967307a28e2df5fa4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/PPC440_Xilinx/port.c - MIT - - - SPDXRef-File-575 - - SHA1 - d7069e85cc0df6dfdc79fbb8450164248d9422b1 - - NOASSERTION - ./portable/GCC/RX100/readme.txt - NOASSERTION - - - SPDXRef-File-576 - - SHA1 - 41b69228953dfda24e7cfe55945cb044970afcd4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX100/portmacro.h - MIT - - - SPDXRef-File-577 - - SHA1 - 2b2e4093c642caf9f6a27b10f335bf53f0225f68 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RX100/port.c - MIT - - - SPDXRef-File-578 - - SHA1 - c2cb36c2752fe724e0c8eeb3d612adb8184a9a1d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV8/port_exceptions.c - MIT - - - SPDXRef-File-579 - - SHA1 - edec7530be3f7036bf5a72bc6f07df8f84791c64 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV8/portmacro.h - MIT - - - SPDXRef-File-580 - - SHA1 - 2bcbbb9080428c17141754f8e8564f64a449b38f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV8/portasm.S - MIT - - - SPDXRef-File-581 - - SHA1 - a8bdb1b3eaa2cfb4b9b511b42ff811ee1faffbed - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/MicroBlazeV8/port.c - MIT - - - SPDXRef-File-582 - - SHA1 - 8081eda244554cfdff614de7675da90269e787c1 - - NOASSERTION - ./portable/GCC/ARM_CM7/ReadMe.txt - NOASSERTION - - - SPDXRef-File-583 - - SHA1 - 4f7d9fe0e11c0e63abf60bf6dd2067edd1261171 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_No_GIC/portASM.S - MIT - - - SPDXRef-File-584 - - SHA1 - ddb4d47efb5e92f67024e4ebf69c2d604a1e032a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_No_GIC/portmacro.h - MIT - - - SPDXRef-File-585 - - SHA1 - 88ab14ee9897105f82e5edd3a4ea75c548d34485 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_No_GIC/port.c - MIT - - - SPDXRef-File-586 - - SHA1 - 724d03f3f0def60fec2d6f9784e6418dfd1a7ac9 - - Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_MPU/portASM.S - MIT - - - SPDXRef-File-587 - - SHA1 - fc42c50b6a1c91d5d0bbc7df750dc92475ee5a2d - - Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S - MIT - - - SPDXRef-File-588 - - SHA1 - 1eab2b8bb8e933fbe4f81e32263828ad894fcd23 - - Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_MPU/portmacro.h - MIT - - - SPDXRef-File-589 - - SHA1 - 70f64939a046a26d857eb728d7cc5b9f749d7567 - - Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_MPU/portmacro_asm.h - MIT - - - SPDXRef-File-590 - - SHA1 - d78c1db219e6b57d7672de2dd1ab2182670ace92 - - Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CRx_MPU/port.c - MIT - - - SPDXRef-File-591 - - SHA1 - 2d53cd9f4f5e4cc30bc31c7f6e47ff4664d63362 - - NOASSERTION - ./portable/GCC/MCF5235/readme.md - NOASSERTION - - - SPDXRef-File-592 - - SHA1 - e0bf7330eeaec8c307b3f19c361541bd0401bb89 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/HCS12/portmacro.h - MIT - - - SPDXRef-File-593 - - SHA1 - fb32f18b9066bde93cfc58901ead737e02234878 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/HCS12/port.c - MIT - - - SPDXRef-File-594 - - SHA1 - a85977bb58e9d80d87f2ceb49296215be1a85c42 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-595 - - SHA1 - f5b58c233b03c387a04fc27c93b456dcc9e146c6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR82/portASM.S - MIT - - - SPDXRef-File-596 - - SHA1 - b31bf23e24fbd76d04b7b00e4c67589da1f53658 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR82/portmacro.h - MIT - - - SPDXRef-File-597 - - SHA1 - 8b0beccbd49442a66fa2c492faa5a8f7dd51ab62 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CR82/port.c - MIT - - - SPDXRef-File-598 - - SHA1 - 3b97e25d4ad670cb77947490b899c78ae1389b46 - - NOASSERTION - ./portable/GCC/ARM_CR82/README.md - NOASSERTION - - - SPDXRef-File-599 - - SHA1 - d0c7415784d3a5dea1567acdb54b06ee5338794d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/AVR32_UC3/portmacro.h - MIT - - - SPDXRef-File-600 - - SHA1 - 415f64effc2e2ae94b3f393ff72b03588579767a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/AVR32_UC3/port.c - MIT - - - SPDXRef-File-601 - - SHA1 - 0632e665faef60390acc9607f58fc423084cb54c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/AVR32_UC3/exception.S - MIT - - - SPDXRef-File-602 - - SHA1 - d968cabe2546996c1fe8535cdabe70d63e7af195 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-603 - - SHA1 - d2a498209e9ed95b566f14bdd4406ac47cad0405 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM3_MPU/portmacro.h - MIT - - - SPDXRef-File-604 - - SHA1 - bf72f2cc24339476e8a5df1557e4f108f3eb92ca - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM3_MPU/port.c - MIT - - - SPDXRef-File-605 - - SHA1 - d968cabe2546996c1fe8535cdabe70d63e7af195 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-606 - - SHA1 - 3494eae2ac53b6d685d54e494b4bd5e8e7df5fe2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM4_MPU/portmacro.h - MIT - - - SPDXRef-File-607 - - SHA1 - 4caf802dce103e6858e5f8de1f35b113f3f30737 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM4_MPU/port.c - MIT - - - SPDXRef-File-608 - - SHA1 - 159c24aa16b5ae6350c72596459085da44eabddc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_LPC2000/portISR.c - MIT - - - SPDXRef-File-609 - - SHA1 - a5b171c3500b7e41a0c60c29020a1430a2d69dda - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_LPC2000/portmacro.h - MIT - - - SPDXRef-File-610 - - SHA1 - 62ec995cdc875390e1d14e0ed4ecee911902af88 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM7_LPC2000/port.c - MIT - - - SPDXRef-File-611 - - SHA1 - 942658ce0f7c45b5a16144a09a8f561c1b7282e3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/IA32_flat/ISR_Support.h - MIT - - - SPDXRef-File-612 - - SHA1 - 9b9958183bc0dc9822d62e4bc0091a36006412db - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/IA32_flat/portASM.S - MIT - - - SPDXRef-File-613 - - SHA1 - 9751eb92aa41a2c6c433da6f9184c639693ab0dc - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/IA32_flat/portmacro.h - MIT - - - SPDXRef-File-614 - - SHA1 - 0121359fb80dd60cfd889b8eed6f5e835ebbb419 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/IA32_flat/port.c - MIT - - - SPDXRef-File-615 - - SHA1 - 3bb5e30a40b53c72ef5077c26d10f9e2ec85854a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/TriCore_1782/porttrap.c - MIT - - - SPDXRef-File-616 - - SHA1 - 09be458703442b24a4a19e2ced735a2b15cffd83 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/TriCore_1782/portmacro.h - MIT - - - SPDXRef-File-617 - - SHA1 - 05641d7d567091e1b9805dbd8f18f54e34bedaf8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/TriCore_1782/port.c - MIT - - - SPDXRef-File-618 - - SHA1 - 876e6c843751e420b190e6755695d8bf05cf9aaa - - NOASSERTION - ./portable/GCC/AVR_Mega0/README.md - NOASSERTION - - - SPDXRef-File-619 - - SHA1 - cec462cb051119b33a929c72d4f96c234923d8ee - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-620 - - SHA1 - cc4a758f584ab513bb67d578de0e5ec6d0ef17b3 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM0/portmacro.h - MIT - - - SPDXRef-File-621 - - SHA1 - 015be3614dfbcccee25104c9215997e4dfbd1441 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM0/port.c - MIT - - - SPDXRef-File-622 - - SHA1 - 21703277d43ce710ae0308104fcee1cfc3ae661e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM0/portasm.c - MIT - - - SPDXRef-File-623 - - SHA1 - 70b1ea3819988e102cf8bcf34769fcb365fd90d1 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM0/portasm.h - MIT - - - SPDXRef-File-624 - - SHA1 - b9a1211dff8b674e501b8c2567f5f1a92d5d1283 - - NOASSERTION - ./portable/GCC/RISC-V/Documentation.url - NOASSERTION - - - SPDXRef-File-625 - - SHA1 - e4d8bedd520478aaf09f984706966ed0a810e0bb - - NOASSERTION - ./portable/GCC/RISC-V/chip_extensions.cmake - NOASSERTION - - - SPDXRef-File-626 - - SHA1 - bb960edcd239bba8a0d86bcd7acf718b101d0781 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. 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All Rights Reserved. - ./portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h - MIT - - - SPDXRef-File-636 - - SHA1 - 6fd838f1cd9477f6da9b0dba5d9fd3922fb34cbf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h - MIT - - - SPDXRef-File-637 - - SHA1 - 095439d4e8b977878b6259a49fdbb147248c7a92 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h - MIT - - - SPDXRef-File-638 - - SHA1 - 7d4f6564b327e2afeff19798505a72566ad3ed9f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h - MIT - - - SPDXRef-File-639 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_context.c - MIT - - - SPDXRef-File-640 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_init.h - MIT - - - SPDXRef-File-641 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_context.h - MIT - - - SPDXRef-File-642 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_heap.c - MIT - - - SPDXRef-File-643 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_init.c - MIT - - - SPDXRef-File-644 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_context_port.c - MIT - - - SPDXRef-File-645 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_port_macros.h - MIT - - - SPDXRef-File-646 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/secure/secure_heap.h - MIT - - - SPDXRef-File-647 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-648 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-649 - - SHA1 - 8ff9c9cfa7a1283acae499a9b417d40d52049700 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/non_secure/portmacro.h - MIT - - - SPDXRef-File-650 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/non_secure/port.c - MIT - - - SPDXRef-File-651 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/non_secure/portasm.c - MIT - - - SPDXRef-File-652 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55/non_secure/portasm.h - MIT - - - SPDXRef-File-653 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-654 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-655 - - SHA1 - 8ff9c9cfa7a1283acae499a9b417d40d52049700 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-656 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-657 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-658 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-659 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_context.c - MIT - - - SPDXRef-File-660 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_init.h - MIT - - - SPDXRef-File-661 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_context.h - MIT - - - SPDXRef-File-662 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_heap.c - MIT - - - SPDXRef-File-663 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_init.c - MIT - - - SPDXRef-File-664 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_context_port.c - MIT - - - SPDXRef-File-665 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_port_macros.h - MIT - - - SPDXRef-File-666 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/secure/secure_heap.h - MIT - - - SPDXRef-File-667 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-668 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-669 - - SHA1 - 28f07bd406f46fb42aa197fcf0afd0a2483a820b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/non_secure/portmacro.h - MIT - - - SPDXRef-File-670 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/non_secure/port.c - MIT - - - SPDXRef-File-671 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/non_secure/portasm.c - MIT - - - SPDXRef-File-672 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33/non_secure/portasm.h - MIT - - - SPDXRef-File-673 - - SHA1 - e4292552acd365f2fa84a0be9c9a072c24e08795 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM7/r0p1/portmacro.h - MIT - - - SPDXRef-File-674 - - SHA1 - a3d9d0879922b8308cc072ad161041fad36946e5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM7/r0p1/port.c - MIT - - - SPDXRef-File-675 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-676 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-677 - - SHA1 - e06005b54cbc757e1c3eadb192063ac2dabff4df - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-678 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-679 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-680 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-681 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_context.c - MIT - - - SPDXRef-File-682 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_init.h - MIT - - - SPDXRef-File-683 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_context.h - MIT - - - SPDXRef-File-684 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_heap.c - MIT - - - SPDXRef-File-685 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_init.c - MIT - - - SPDXRef-File-686 - - SHA1 - c3d22d9788edd71a064b306083e257eabb811e07 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_context_port.c - MIT - - - SPDXRef-File-687 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_port_macros.h - MIT - - - SPDXRef-File-688 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/secure/secure_heap.h - MIT - - - SPDXRef-File-689 - - SHA1 - f3483ef423d1e0b5c02b484ac9e7a5c9a686d158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-690 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-691 - - SHA1 - 5c85e2a198183e1323d2336dcdb5eafbee255728 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/non_secure/portmacro.h - MIT - - - SPDXRef-File-692 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/non_secure/port.c - MIT - - - SPDXRef-File-693 - - SHA1 - d5c023e3537339a5a871d80e20d872c701e89fe9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/non_secure/portasm.c - MIT - - - SPDXRef-File-694 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23/non_secure/portasm.h - MIT - - - SPDXRef-File-695 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-696 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-697 - - SHA1 - 7735f98b36fc191ee55d5bca216c0de62279681d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-698 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-699 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-700 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-701 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-702 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-703 - - SHA1 - 80db952dbdf457088e07814b3dd036d3bc5cae7b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-704 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-705 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-706 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-707 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_context.c - MIT - - - SPDXRef-File-708 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_init.h - MIT - - - SPDXRef-File-709 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_context.h - MIT - - - SPDXRef-File-710 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_heap.c - MIT - - - SPDXRef-File-711 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_init.c - MIT - - - SPDXRef-File-712 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_context_port.c - MIT - - - SPDXRef-File-713 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_port_macros.h - MIT - - - SPDXRef-File-714 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/secure/secure_heap.h - MIT - - - SPDXRef-File-715 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-716 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-717 - - SHA1 - 7735f98b36fc191ee55d5bca216c0de62279681d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/non_secure/portmacro.h - MIT - - - SPDXRef-File-718 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/non_secure/port.c - MIT - - - SPDXRef-File-719 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/non_secure/portasm.c - MIT - - - SPDXRef-File-720 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM85/non_secure/portasm.h - MIT - - - SPDXRef-File-721 - - SHA1 - f3483ef423d1e0b5c02b484ac9e7a5c9a686d158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-722 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-723 - - SHA1 - 5c85e2a198183e1323d2336dcdb5eafbee255728 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-724 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-725 - - SHA1 - 39466b68bd1963d8c679d7e87a2d03e1e385c00c - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-726 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-727 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-728 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-729 - - SHA1 - 28f07bd406f46fb42aa197fcf0afd0a2483a820b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-730 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-731 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-732 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-733 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_context.c - MIT - - - SPDXRef-File-734 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_init.h - MIT - - - SPDXRef-File-735 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_context.h - MIT - - - SPDXRef-File-736 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_heap.c - MIT - - - SPDXRef-File-737 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_init.c - MIT - - - SPDXRef-File-738 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_context_port.c - MIT - - - SPDXRef-File-739 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_port_macros.h - MIT - - - SPDXRef-File-740 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/secure/secure_heap.h - MIT - - - SPDXRef-File-741 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-742 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-743 - - SHA1 - e06005b54cbc757e1c3eadb192063ac2dabff4df - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/non_secure/portmacro.h - MIT - - - SPDXRef-File-744 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/non_secure/port.c - MIT - - - SPDXRef-File-745 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/non_secure/portasm.c - MIT - - - SPDXRef-File-746 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM35P/non_secure/portasm.h - MIT - - - SPDXRef-File-747 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_context.c - MIT - - - SPDXRef-File-748 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_init.h - MIT - - - SPDXRef-File-749 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_context.h - MIT - - - SPDXRef-File-750 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_heap.c - MIT - - - SPDXRef-File-751 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_init.c - MIT - - - SPDXRef-File-752 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c - MIT - - - SPDXRef-File-753 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h - MIT - - - SPDXRef-File-754 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/secure/secure_heap.h - MIT - - - SPDXRef-File-755 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-756 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-757 - - SHA1 - 791a8d0ec284343d92cbe7fd79808d24302b847d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h - MIT - - - SPDXRef-File-758 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/non_secure/port.c - MIT - - - SPDXRef-File-759 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/non_secure/portasm.c - MIT - - - SPDXRef-File-760 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3/non_secure/portasm.h - MIT - - - SPDXRef-File-761 - - SHA1 - 119a41b8c3d5f5acb637bb2d64d1323c612b5383 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_context.c - MIT - - - SPDXRef-File-762 - - SHA1 - 91b67c9859687072a2b00e5ff18149c13266894e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_init.h - MIT - - - SPDXRef-File-763 - - SHA1 - 64538102c99b593ec421f77fa212d822abe1645b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_context.h - MIT - - - SPDXRef-File-764 - - SHA1 - 1eaf707c8523b9312ac60965a2934c95391d9d6a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_heap.c - MIT - - - SPDXRef-File-765 - - SHA1 - 4d39a6ae367720c7ac7c24249fbd1f510ed5a304 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_init.c - MIT - - - SPDXRef-File-766 - - SHA1 - 8021926d279b1efb6fe5bfb8587b7621a92df7cd - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_context_port.c - MIT - - - SPDXRef-File-767 - - SHA1 - 0c6bd13bbe7f6f2c0e9b9546f3f13aa41db17a8b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_port_macros.h - MIT - - - SPDXRef-File-768 - - SHA1 - 978a0352555b87548415d844132e20a657804b75 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/secure/secure_heap.h - MIT - - - SPDXRef-File-769 - - SHA1 - 37301e4f15b7defd59dbb0c35f7e7666d8e7f596 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-770 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-771 - - SHA1 - 80db952dbdf457088e07814b3dd036d3bc5cae7b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/non_secure/portmacro.h - MIT - - - SPDXRef-File-772 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/non_secure/port.c - MIT - - - SPDXRef-File-773 - - SHA1 - 2cf2dd3c12eb65f566b3fe14e44f2b8dd3ac20de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/non_secure/portasm.c - MIT - - - SPDXRef-File-774 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_CM52/non_secure/portasm.h - MIT - - - SPDXRef-File-775 - - SHA1 - 074b5ab8f0ffa700140b0cbaace9991ca12dd98d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-776 - - SHA1 - 9b25ef388a63017a2b7de676fbc5a39d3dcfdfaf - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h - MIT - - - SPDXRef-File-777 - - SHA1 - 791a8d0ec284343d92cbe7fd79808d24302b847d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h - MIT - - - SPDXRef-File-778 - - SHA1 - 5332ddb298b6bfd49e0007dc416ab8f97a5b6c5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c - MIT - - - SPDXRef-File-779 - - SHA1 - 96beb008c4fa1f6fd5f3bd19a3d3758b53f04db5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c - MIT - - - SPDXRef-File-780 - - SHA1 - 3151d5318f825a654f570f832a7e9cf4f7ce2158 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h - MIT - - - SPDXRef-File-781 - - SHA1 - 2d800f52a712faa050ee36b922aafdd09571c81b - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/oWatcom/16BitDOS/common/portasm.h - MIT - - - SPDXRef-File-782 - - SHA1 - 5fcb68b2d27b2026ebda90662242fb794363ac5e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/oWatcom/16BitDOS/common/portcomn.c - MIT - - - SPDXRef-File-783 - - SHA1 - 4b406215a6411654198c5022320726618139b328 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/oWatcom/16BitDOS/Flsh186/portmacro.h - MIT - - - SPDXRef-File-784 - - SHA1 - ce9ec9a9767accb857b7fa83797699bbd5ece0b4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/oWatcom/16BitDOS/Flsh186/port.c - MIT - - - SPDXRef-File-785 - - SHA1 - bf3de1eda493f15ff04f7d284d327f8966b70e15 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/oWatcom/16BitDOS/PC/portmacro.h - MIT - - - SPDXRef-File-786 - - SHA1 - 0a33865c872f7080a387d48d35585b3d31cf857f - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/oWatcom/16BitDOS/PC/port.c - MIT - - - SPDXRef-File-787 - - SHA1 - 600b5ab051ce5f6b6acb64044693b2d593e70b82 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Paradigm/Tern_EE/small/portmacro.h - MIT - - - SPDXRef-File-788 - - SHA1 - 2c8985e90551f7d9468fba3bca00718fb6043806 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Paradigm/Tern_EE/small/port.c - MIT - - - SPDXRef-File-789 - - SHA1 - f08599fc559b2ceb448b4bc38f03186aa2263570 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Paradigm/Tern_EE/small/portasm.h - MIT - - - SPDXRef-File-790 - - SHA1 - 17ffbf93f3e7fd7dc797c46a3a675cbecdb34004 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Paradigm/Tern_EE/large_untested/portmacro.h - MIT - - - SPDXRef-File-791 - - SHA1 - 395039a788425b717d1d55ed3dc6f1b7abdc6756 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Paradigm/Tern_EE/large_untested/port.c - MIT - - - SPDXRef-File-792 - - SHA1 - 423f70dac29abc240afcbfd8bab997bbe6ae38de - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/Paradigm/Tern_EE/large_untested/portasm.h - MIT - - - SPDXRef-File-793 - - SHA1 - f6cc6e1569a9eac4e6e3aeb2809f1d91564bdef6 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CA9/portmacro.inc - MIT - - - SPDXRef-File-794 - - SHA1 - b7965bef7799ae78bb576e05d30524a59814f700 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CA9/portmacro.h - MIT - - - SPDXRef-File-795 - - SHA1 - 3dbbcefc0a8916d861b2a8db4c054691d505b672 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CA9/port.c - MIT - - - SPDXRef-File-796 - - SHA1 - 21fc6ce7198006fbeaed4d8a9dbc1f2b91ad3c2d - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CA9/portASM.s - MIT - - - SPDXRef-File-797 - - SHA1 - c3c69b9c92a9954665553e1b1ad3a342ed49e0f8 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CM3/portmacro.h - MIT - - - SPDXRef-File-798 - - SHA1 - c17cf842f614ebde52aae813a5c82b29a9e4e65e - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CM3/port.c - MIT - - - SPDXRef-File-799 - - SHA1 - 7279c2a0f29835e2055bd35766a1af161bd32a54 - - NOASSERTION - ./portable/RVDS/ARM_CM7/ReadMe.txt - NOASSERTION - - - SPDXRef-File-800 - - SHA1 - 831a69c81dfb5a4c3bfd900156afdba96649629a - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM7_LPC21xx/portmacro.inc - MIT - - - SPDXRef-File-801 - - SHA1 - 526e7e25c8d781a23fbf8a3f3ac1f0ff580781a2 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM7_LPC21xx/portmacro.h - MIT - - - SPDXRef-File-802 - - SHA1 - 9d06c3e1fe3679f6f02970b8b8762eea391cb7b9 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM7_LPC21xx/port.c - MIT - - - SPDXRef-File-803 - - SHA1 - acc4788a1361ed872d7b3d0a8ca5f67fba3eaeb5 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM7_LPC21xx/portASM.s - MIT - - - SPDXRef-File-804 - - SHA1 - 55dfb528135c5872c3a1b670d8c95b5ab2cb97ef - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c - MIT - - - SPDXRef-File-805 - - SHA1 - 4498c7ccd49000780b15e086aadbd61e0d020252 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CM4_MPU/portmacro.h - MIT - - - SPDXRef-File-806 - - SHA1 - a386255c433bca808cc3e4c01693852c516c5cce - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - ./portable/RVDS/ARM_CM4_MPU/port.c - MIT - - - SPDXRef-File-807 - - SHA1 - 75b4482af2bdec919efe29ba048c596c27a2ffa4 - - Copyright (C) 2021 Amazon.com, Inc. or its affiliates. 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relationshipType: CONTAINS - spdxElementId: SPDXRef-Package -spdxVersion: SPDX-2.3 diff --git a/README.md b/README.md index b4e87ce3b..fabe5220b 100644 --- a/README.md +++ b/README.md @@ -130,7 +130,7 @@ See the readme file in the ```./portable``` directory for more information. - The ```./include``` directory contains the real time kernel header files. -- The ```./template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project. +- The ```./examples/template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project. See the [FreeRTOSConfig.h](examples/template_configuration/FreeRTOSConfig.h) file for instructions. ### Code Formatting diff --git a/croutine.c b/croutine.c index 6ee7a131c..84e1b99bd 100644 --- a/croutine.c +++ b/croutine.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/event_groups.c b/event_groups.c index 7c43fa502..c69b96557 100644 --- a/event_groups.c +++ b/event_groups.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c index c62b26512..4b7ad5c5f 100644 --- a/examples/cmake_example/main.c +++ b/examples/cmake_example/main.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/examples/coverity/FreeRTOSConfig.h b/examples/coverity/FreeRTOSConfig.h index 0a6978989..5feaa40de 100644 --- a/examples/coverity/FreeRTOSConfig.h +++ b/examples/coverity/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h index 53262a830..7859a5c77 100644 --- a/examples/template_configuration/FreeRTOSConfig.h +++ b/examples/template_configuration/FreeRTOSConfig.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h index f31e72abb..63e2feb51 100644 --- a/include/FreeRTOS.h +++ b/include/FreeRTOS.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/StackMacros.h b/include/StackMacros.h index 07282a2c8..d0c624733 100644 --- a/include/StackMacros.h +++ b/include/StackMacros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/atomic.h b/include/atomic.h index 2fe6b4382..335a77fdf 100644 --- a/include/atomic.h +++ b/include/atomic.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/croutine.h b/include/croutine.h index 42e27b109..a5e2e4462 100644 --- a/include/croutine.h +++ b/include/croutine.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/deprecated_definitions.h b/include/deprecated_definitions.h index 60382309a..edc0f2246 100644 --- a/include/deprecated_definitions.h +++ b/include/deprecated_definitions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/event_groups.h b/include/event_groups.h index d705aa11f..d42c87b28 100644 --- a/include/event_groups.h +++ b/include/event_groups.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/list.h b/include/list.h index 2b9e2a27f..f9a8c00f6 100644 --- a/include/list.h +++ b/include/list.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -92,7 +92,7 @@ */ #ifndef configLIST_VOLATILE #define configLIST_VOLATILE -#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ +#endif /* configLIST_VOLATILE */ /* *INDENT-OFF* */ #ifdef __cplusplus @@ -191,7 +191,7 @@ typedef struct xLIST * Access macro to get the owner of a list item. The owner of a list item * is the object (usually a TCB) that contains the list item. * - * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \page listGET_LIST_ITEM_OWNER listGET_LIST_ITEM_OWNER * \ingroup LinkedList */ #define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) @@ -310,7 +310,7 @@ typedef struct xLIST * Remove an item from a list. The list item has a pointer to the list that * it is in, so only the list item need be passed into the function. * - * @param uxListRemove The item to be removed. The item will remove itself from + * @param pxItemToRemove The item to be removed. The item will remove itself from * the list pointed to by it's pxContainer parameter. * * @return The number of items that remain in the list after the list item has @@ -491,7 +491,7 @@ void vListInsertEnd( List_t * const pxList, * Remove an item from a list. The list item has a pointer to the list that * it is in, so only the list item need be passed into the function. * - * @param uxListRemove The item to be removed. The item will remove itself from + * @param pxItemToRemove The item to be removed. The item will remove itself from * the list pointed to by it's pxContainer parameter. * * @return The number of items that remain in the list after the list item has diff --git a/include/message_buffer.h b/include/message_buffer.h index afc337f76..cac6db3ba 100644 --- a/include/message_buffer.h +++ b/include/message_buffer.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -560,14 +560,14 @@ typedef StreamBufferHandle_t MessageBufferHandle_t; * * Example use: * @code{c} - * void vAFunction( MessageBuffer_t xMessageBuffer ) + * void vAFunction( MessageBufferHandle_t xMessageBuffer ) * { * uint8_t ucRxData[ 20 ]; * size_t xReceivedBytes; * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); * * // Receive the next message from the message buffer. Wait in the Blocked - * // state (so not using any CPU processing time) for a maximum of 100ms for + * // state (so not using any CPU processing time) for a maximum of 20ms for * // a message to become available. * xReceivedBytes = xMessageBufferReceive( xMessageBuffer, * ( void * ) ucRxData, @@ -655,7 +655,7 @@ typedef StreamBufferHandle_t MessageBufferHandle_t; * Example use: * @code{c} * // A message buffer that has already been created. - * MessageBuffer_t xMessageBuffer; + * MessageBufferHandle_t xMessageBuffer; * * void vAnInterruptServiceRoutine( void ) * { diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h index 7f1652d75..b4c0f4745 100644 --- a/include/mpu_prototypes.h +++ b/include/mpu_prototypes.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/mpu_syscall_numbers.h b/include/mpu_syscall_numbers.h index 50142e4a5..7c625a78d 100644 --- a/include/mpu_syscall_numbers.h +++ b/include/mpu_syscall_numbers.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h index 560d2aad9..3b4738e96 100644 --- a/include/mpu_wrappers.h +++ b/include/mpu_wrappers.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/newlib-freertos.h b/include/newlib-freertos.h index 531fec9b1..4414d24ad 100644 --- a/include/newlib-freertos.h +++ b/include/newlib-freertos.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/picolibc-freertos.h b/include/picolibc-freertos.h index 86ed9f803..5cf01afa8 100644 --- a/include/picolibc-freertos.h +++ b/include/picolibc-freertos.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/portable.h b/include/portable.h index 14277ab89..68e11e793 100644 --- a/include/portable.h +++ b/include/portable.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/projdefs.h b/include/projdefs.h index aff862dea..04ec47fae 100644 --- a/include/projdefs.h +++ b/include/projdefs.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/queue.h b/include/queue.h index b14f8536d..e3dbbefd2 100644 --- a/include/queue.h +++ b/include/queue.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/semphr.h b/include/semphr.h index c4b1a4364..7b44d78c0 100644 --- a/include/semphr.h +++ b/include/semphr.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/stack_macros.h b/include/stack_macros.h index 9b7dd7706..6d0117722 100644 --- a/include/stack_macros.h +++ b/include/stack_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/stdint.readme b/include/stdint.readme index d9e5aabbd..bfe3bb6f8 100644 --- a/include/stdint.readme +++ b/include/stdint.readme @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/include/stream_buffer.h b/include/stream_buffer.h index bec895dc6..577420c44 100644 --- a/include/stream_buffer.h +++ b/include/stream_buffer.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -760,7 +760,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, * * Example use: * @code{c} - * void vAFunction( StreamBuffer_t xStreamBuffer ) + * void vAFunction( StreamBufferHandle_t xStreamBuffer ) * { * uint8_t ucRxData[ 20 ]; * size_t xReceivedBytes; @@ -768,7 +768,7 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, * * // Receive up to another sizeof( ucRxData ) bytes from the stream buffer. * // Wait in the Blocked state (so not using any CPU processing time) for a - * // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be + * // maximum of 20ms for the full sizeof( ucRxData ) number of bytes to be * // available. * xReceivedBytes = xStreamBufferReceive( xStreamBuffer, * ( void * ) ucRxData, @@ -840,7 +840,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, * Example use: * @code{c} * // A stream buffer that has already been created. - * StreamBuffer_t xStreamBuffer; + * StreamBufferHandle_t xStreamBuffer; * * void vAnInterruptServiceRoutine( void ) * { @@ -1218,7 +1218,7 @@ UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t * stream_buffer.h * * @code{c} - * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBuffer_t xStreamBuffer, UBaseType_t uxNotificationIndex ); + * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxNotificationIndex ); * @endcode * * Set the task notification index used for the supplied stream buffer. diff --git a/include/task.h b/include/task.h index 81921320e..2a19fa73f 100644 --- a/include/task.h +++ b/include/task.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * @@ -54,9 +54,9 @@ * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD * values will reflect the last released version number. */ -#define tskKERNEL_VERSION_NUMBER "V11.3.0" +#define tskKERNEL_VERSION_NUMBER "V11.1.0+" #define tskKERNEL_VERSION_MAJOR 11 -#define tskKERNEL_VERSION_MINOR 3 +#define tskKERNEL_VERSION_MINOR 1 #define tskKERNEL_VERSION_BUILD 0 /* MPU region parameters passed in ulParameters diff --git a/include/timers.h b/include/timers.h index 480f31c44..7d99d3536 100644 --- a/include/timers.h +++ b/include/timers.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/list.c b/list.c index 5cdc86296..0c0f3676e 100644 --- a/list.c +++ b/list.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/manifest.yml b/manifest.yml index 60794d006..bd893f162 100644 --- a/manifest.yml +++ b/manifest.yml @@ -1,4 +1,4 @@ name : "FreeRTOS-Kernel" -version: "V11.3.0" +version: "V11.0.1+" description: "FreeRTOS Kernel." license: "MIT" diff --git a/portable/ARMv8M/copy_files.py b/portable/ARMv8M/copy_files.py index 94efa3dc1..ddeeb13ea 100644 --- a/portable/ARMv8M/copy_files.py +++ b/portable/ARMv8M/copy_files.py @@ -1,5 +1,5 @@ #/* -# * FreeRTOS Kernel V11.3.0 +# * FreeRTOS Kernel # * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. # * # * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/ReadMe.txt b/portable/ARMv8M/non_secure/ReadMe.txt index 5a8c28838..973c2cbbc 100644 --- a/portable/ARMv8M/non_secure/ReadMe.txt +++ b/portable/ARMv8M/non_secure/ReadMe.txt @@ -1,6 +1,6 @@ This directory tree contains the master copy of the FreeRTOS Armv8-M and Armv8.1-M ports. -Do not use the files located here! These file are copied into separate +Do not use the files located here! These files are copied into separate FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories prior to each FreeRTOS release. @@ -9,3 +9,54 @@ FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] dire If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories. + +Note: +The Armv8-M ports support SMP (multicore) systems when both MPU and TrustZone are disabled. +However, this has only been validated on Arm Cortex-M33 Non-TrustZone Non-MPU port. + +SMP Boot Sequence +--------------------------------------- + +Primary core flow: + +1. Perform core-specific and shared initialization (e.g., zero-initialize `.bss`). +2. Jump to `main()`, create user tasks, optionally pin tasks to specific cores. +3. Call `vTaskStartScheduler()` which invokes `xPortStartScheduler()`. +4. `xPortStartScheduler()` configures the primary core tick timer and signals secondary cores that shared init is complete using the `ucPrimaryCoreInitDoneFlag` variable. +5. Call the application-defined `configWAKE_SECONDARY_CORES` function. +6. Wait until all secondary cores report as brought up. +7. Once all cores are up, call `vStartFirstTask()` to schedule the first task on the primary core. + +Secondary core flow: + +1. Perform core-specific initialization. +2. Wait until the primary core signals that shared initialization has completed (that is, `ucPrimaryCoreInitDoneFlag` is set to 1). Once this occurs, +the application-defined `configWAKE_SECONDARY_CORES` function is invoked by the primary core to carry out the subsequent steps. +3. Program the inter-processor signaling mechanism (e.g., Arm Doorbell Mechanism) to be used by the kernel to interrupt that core and request that it perform a context switch. +4. Call `vPortConfigureInterruptPriorities` function to setup per core interrupt priorities. +5. If Pointer Authentication (PAC) or Branch Target Identification (BTI) is supported, call `vConfigurePACBTI` with `pdTRUE` as the input parameter to configure the per-core special-purpose CONTROL register +with the appropriate PACBTI settings. +6. Signal the primary that this secondary is online and ready by setting its flag in the `ucSecondaryCoresReadyFlags` array. +7. Issue an SVC with immediate value `102` (portSVC_START_SCHEDULER), which will call `vRestoreContextOfFirstTask()` to start scheduling on this core. + + +Inter-core notification +--------------------------------------- + +On SMP systems the application must provide an implementation of the `vInterruptCore( uint8_t ucCoreID )` function. The kernel calls this function +to interrupt another core and request that it perform a context switch (e.g., when a higher-priority task becomes ready on that core). + +Typical platform implementation: write a doorbell flag/bit or other inter-processor signaling register targeting `ucCoreID`. This should cause a +"doorbell" (or equivalent) IRQ on the secondary core. In the secondary core’s doorbell IRQ handler, check the reason for the interrupt and, if it is a +schedule request, trigger a context switch (i.e., by calling `portYIELD_FROM_ISR`). + +Notes: + +* `vInterruptCore` is declared weak in the port so that platforms can override it. If your hardware lacks a dedicated doorbell, use any available +inter-core interrupt/messaging mechanism to achieve the same effect. + +* The application must define `configCORE_ID_REGISTER`, usually in `FreeRTOSConfig.h` to the memory-mapped address of the platform register used +to read the current core ID. The port reads this register to determine the executing core and to index per-core scheduler state. + +* The application must define `configWAKE_SECONDARY_CORES`, usually in `FreeRTOSConfig.h`, to point to the application/platform-specific function +that wakes up and make the secondary cores ready after the primary core completes initialisation. diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c index 970ec0a65..7a62caff0 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c index b6e836f9c..978d35259 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h index 3385afd8a..f0d8b273d 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c index 970ec0a65..7a62caff0 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c index 3015b9ec5..d215f8f73 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h index 3385afd8a..f0d8b273d 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h index a78432994..02e5c92b0 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h index a78432994..9447e6558 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 1 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h index e974d3657..9c78947b0 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h index e85f7bbe0..a8f48a46a 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h index 8cb6e6556..814ec9c56 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h index ef5f73a9f..88615be17 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h index c79ab8589..2295105ee 100644 --- a/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S index 729dff1f3..9289bcbc2 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s index 2b93d5b60..6817abd7a 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h index c9215d885..46c2a2885 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S index 729dff1f3..9289bcbc2 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s index 336b16b09..bfe9eee4b 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h index c9215d885..46c2a2885 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h index 2dfa847aa..61da05503 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h index 2dfa847aa..b9612e487 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 1 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h index a03a81e51..9f7c97b90 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h index 13725fb54..d1e4d3a84 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h index bb91c012f..e58485e40 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h index 0b7c0ffa5..0268a9592 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h index 90aa59b0f..8ee96052d 100644 --- a/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/ARMv8M/non_secure/portasm.h b/portable/ARMv8M/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/ARMv8M/non_secure/portasm.h +++ b/portable/ARMv8M/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/ARMv8M/non_secure/portmacrocommon.h +++ b/portable/ARMv8M/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c index a55182f18..32559ad04 100644 --- a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c +++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c +++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s index a6f4cbe82..f70e89115 100644 --- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s +++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s +++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/context/secure_context.c b/portable/ARMv8M/secure/context/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/ARMv8M/secure/context/secure_context.c +++ b/portable/ARMv8M/secure/context/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/ARMv8M/secure/context/secure_context.h b/portable/ARMv8M/secure/context/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/ARMv8M/secure/context/secure_context.h +++ b/portable/ARMv8M/secure/context/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/ARMv8M/secure/heap/secure_heap.c +++ b/portable/ARMv8M/secure/heap/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/heap/secure_heap.h b/portable/ARMv8M/secure/heap/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/ARMv8M/secure/heap/secure_heap.h +++ b/portable/ARMv8M/secure/heap/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/init/secure_init.c b/portable/ARMv8M/secure/init/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/ARMv8M/secure/init/secure_init.c +++ b/portable/ARMv8M/secure/init/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/init/secure_init.h b/portable/ARMv8M/secure/init/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/ARMv8M/secure/init/secure_init.h +++ b/portable/ARMv8M/secure/init/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ARMv8M/secure/macros/secure_port_macros.h b/portable/ARMv8M/secure/macros/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/ARMv8M/secure/macros/secure_port_macros.h +++ b/portable/ARMv8M/secure/macros/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c index 500092638..14b1f6f5a 100644 --- a/portable/BCC/16BitDOS/Flsh186/port.c +++ b/portable/BCC/16BitDOS/Flsh186/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/portable/BCC/16BitDOS/Flsh186/prtmacro.h index 949b0bed6..b1b5c26eb 100644 --- a/portable/BCC/16BitDOS/Flsh186/prtmacro.h +++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c index 6c46a790a..0c1c0644e 100644 --- a/portable/BCC/16BitDOS/PC/port.c +++ b/portable/BCC/16BitDOS/PC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/BCC/16BitDOS/PC/prtmacro.h b/portable/BCC/16BitDOS/PC/prtmacro.h index 9f24b85a4..d24431806 100644 --- a/portable/BCC/16BitDOS/PC/prtmacro.h +++ b/portable/BCC/16BitDOS/PC/prtmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h index 38503295d..3e3acf0bd 100644 --- a/portable/BCC/16BitDOS/common/portasm.h +++ b/portable/BCC/16BitDOS/common/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/BCC/16BitDOS/common/portcomn.c b/portable/BCC/16BitDOS/common/portcomn.c index 3211fdc27..0e1bca1ab 100644 --- a/portable/BCC/16BitDOS/common/portcomn.c +++ b/portable/BCC/16BitDOS/common/portcomn.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCRH/F1Kx/port.c b/portable/CCRH/F1Kx/port.c index 4f2f78a0d..3a43ff418 100644 --- a/portable/CCRH/F1Kx/port.c +++ b/portable/CCRH/F1Kx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCRH/F1Kx/portasm.s b/portable/CCRH/F1Kx/portasm.s index 0cde23aef..ff8e7ee31 100644 --- a/portable/CCRH/F1Kx/portasm.s +++ b/portable/CCRH/F1Kx/portasm.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/CCRH/F1Kx/portmacro.h b/portable/CCRH/F1Kx/portmacro.h index 2dca19d99..a665ad23d 100644 --- a/portable/CCRH/F1Kx/portmacro.h +++ b/portable/CCRH/F1Kx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c index 1c1d1ab43..8373c14c0 100644 --- a/portable/CCS/ARM_CM3/port.c +++ b/portable/CCS/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_CM3/portasm.asm b/portable/CCS/ARM_CM3/portasm.asm index a1d7e4e26..483a66b49 100644 --- a/portable/CCS/ARM_CM3/portasm.asm +++ b/portable/CCS/ARM_CM3/portasm.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h index 6f5dd54e4..42498555f 100644 --- a/portable/CCS/ARM_CM3/portmacro.h +++ b/portable/CCS/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c index 6ba105863..1ad05077d 100644 --- a/portable/CCS/ARM_CM4F/port.c +++ b/portable/CCS/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_CM4F/portasm.asm b/portable/CCS/ARM_CM4F/portasm.asm index 68e53ee86..81d0a71c2 100644 --- a/portable/CCS/ARM_CM4F/portasm.asm +++ b/portable/CCS/ARM_CM4F/portasm.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h index 50336e9c8..faefd124c 100644 --- a/portable/CCS/ARM_CM4F/portmacro.h +++ b/portable/CCS/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c index 2b67ccdd8..853248f40 100644 --- a/portable/CCS/ARM_Cortex-R4/port.c +++ b/portable/CCS/ARM_Cortex-R4/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_Cortex-R4/portASM.asm b/portable/CCS/ARM_Cortex-R4/portASM.asm index 8773be49c..f20af2941 100644 --- a/portable/CCS/ARM_Cortex-R4/portASM.asm +++ b/portable/CCS/ARM_Cortex-R4/portASM.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/CCS/ARM_Cortex-R4/portmacro.h b/portable/CCS/ARM_Cortex-R4/portmacro.h index 21bb9e306..644f13a3c 100644 --- a/portable/CCS/ARM_Cortex-R4/portmacro.h +++ b/portable/CCS/ARM_Cortex-R4/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/MSP430X/data_model.h b/portable/CCS/MSP430X/data_model.h index e37126b00..b199175c0 100644 --- a/portable/CCS/MSP430X/data_model.h +++ b/portable/CCS/MSP430X/data_model.h @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c index cdc3e5a21..2097a2931 100644 --- a/portable/CCS/MSP430X/port.c +++ b/portable/CCS/MSP430X/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CCS/MSP430X/portext.asm b/portable/CCS/MSP430X/portext.asm index ddd216eda..dbbcec0aa 100644 --- a/portable/CCS/MSP430X/portext.asm +++ b/portable/CCS/MSP430X/portext.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h index 50f49ba76..c00c5a902 100644 --- a/portable/CCS/MSP430X/portmacro.h +++ b/portable/CCS/MSP430X/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/ColdFire_V1/port.c b/portable/CodeWarrior/ColdFire_V1/port.c index 15ff6ac5a..520c62ac5 100644 --- a/portable/CodeWarrior/ColdFire_V1/port.c +++ b/portable/CodeWarrior/ColdFire_V1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/ColdFire_V1/portasm.S b/portable/CodeWarrior/ColdFire_V1/portasm.S index 891af5ba0..1f00348af 100644 --- a/portable/CodeWarrior/ColdFire_V1/portasm.S +++ b/portable/CodeWarrior/ColdFire_V1/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h index 675a3b8eb..2f224d30b 100644 --- a/portable/CodeWarrior/ColdFire_V1/portmacro.h +++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/ColdFire_V2/port.c b/portable/CodeWarrior/ColdFire_V2/port.c index 1c905a918..64b2d078b 100644 --- a/portable/CodeWarrior/ColdFire_V2/port.c +++ b/portable/CodeWarrior/ColdFire_V2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/ColdFire_V2/portasm.S b/portable/CodeWarrior/ColdFire_V2/portasm.S index 0a99f1e1f..66f429259 100644 --- a/portable/CodeWarrior/ColdFire_V2/portasm.S +++ b/portable/CodeWarrior/ColdFire_V2/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h index 2a5bbeaa8..55b38ae3a 100644 --- a/portable/CodeWarrior/ColdFire_V2/portmacro.h +++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c index 31e10c196..2d564cd66 100644 --- a/portable/CodeWarrior/HCS12/port.c +++ b/portable/CodeWarrior/HCS12/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/CodeWarrior/HCS12/portmacro.h b/portable/CodeWarrior/HCS12/portmacro.h index b3b1ec161..8e6eb1057 100644 --- a/portable/CodeWarrior/HCS12/portmacro.h +++ b/portable/CodeWarrior/HCS12/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c index 79006450b..5bc4181e2 100644 --- a/portable/Common/mpu_wrappers.c +++ b/portable/Common/mpu_wrappers.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c index 50aaa9628..70082b829 100644 --- a/portable/Common/mpu_wrappers_v2.c +++ b/portable/Common/mpu_wrappers_v2.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_AT91FR40008/port.c b/portable/GCC/ARM7_AT91FR40008/port.c index 849b87b6d..30bbb9f48 100644 --- a/portable/GCC/ARM7_AT91FR40008/port.c +++ b/portable/GCC/ARM7_AT91FR40008/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_AT91FR40008/portISR.c b/portable/GCC/ARM7_AT91FR40008/portISR.c index 728f9919a..b4ddcc06d 100644 --- a/portable/GCC/ARM7_AT91FR40008/portISR.c +++ b/portable/GCC/ARM7_AT91FR40008/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h index d3aa336a2..4dbadab3f 100644 --- a/portable/GCC/ARM7_AT91FR40008/portmacro.h +++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_AT91SAM7S/port.c b/portable/GCC/ARM7_AT91SAM7S/port.c index 097e2952e..6750c45ee 100644 --- a/portable/GCC/ARM7_AT91SAM7S/port.c +++ b/portable/GCC/ARM7_AT91SAM7S/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c index 14d22d3f9..9e5ff6c98 100644 --- a/portable/GCC/ARM7_AT91SAM7S/portISR.c +++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h index be2688a59..3f2242fa9 100644 --- a/portable/GCC/ARM7_AT91SAM7S/portmacro.h +++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_LPC2000/port.c b/portable/GCC/ARM7_LPC2000/port.c index 3cd2c84cc..2c8268af5 100644 --- a/portable/GCC/ARM7_LPC2000/port.c +++ b/portable/GCC/ARM7_LPC2000/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_LPC2000/portISR.c b/portable/GCC/ARM7_LPC2000/portISR.c index d0f0836e9..4255df713 100644 --- a/portable/GCC/ARM7_LPC2000/portISR.c +++ b/portable/GCC/ARM7_LPC2000/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h index 08b274ca9..8e82cc08e 100644 --- a/portable/GCC/ARM7_LPC2000/portmacro.h +++ b/portable/GCC/ARM7_LPC2000/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_LPC23xx/port.c b/portable/GCC/ARM7_LPC23xx/port.c index 919a9a625..8ac1df709 100644 --- a/portable/GCC/ARM7_LPC23xx/port.c +++ b/portable/GCC/ARM7_LPC23xx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c index 1de68be5c..1cf7c7dae 100644 --- a/portable/GCC/ARM7_LPC23xx/portISR.c +++ b/portable/GCC/ARM7_LPC23xx/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h index be2688a59..3f2242fa9 100644 --- a/portable/GCC/ARM7_LPC23xx/portmacro.h +++ b/portable/GCC/ARM7_LPC23xx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c index f8d727666..7f080db74 100644 --- a/portable/GCC/ARM_AARCH64/port.c +++ b/portable/GCC/ARM_AARCH64/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_AARCH64/portASM.S b/portable/GCC/ARM_AARCH64/portASM.S index befe8b33a..e684755bf 100644 --- a/portable/GCC/ARM_AARCH64/portASM.S +++ b/portable/GCC/ARM_AARCH64/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_AARCH64/portmacro.h b/portable/GCC/ARM_AARCH64/portmacro.h index 2e8b511d3..0091357ee 100644 --- a/portable/GCC/ARM_AARCH64/portmacro.h +++ b/portable/GCC/ARM_AARCH64/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c index 405925a0c..ab9290d43 100644 --- a/portable/GCC/ARM_AARCH64_SRE/port.c +++ b/portable/GCC/ARM_AARCH64_SRE/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_AARCH64_SRE/portASM.S b/portable/GCC/ARM_AARCH64_SRE/portASM.S index ff8ce9401..f1f59cd33 100644 --- a/portable/GCC/ARM_AARCH64_SRE/portASM.S +++ b/portable/GCC/ARM_AARCH64_SRE/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_AARCH64_SRE/portmacro.h b/portable/GCC/ARM_AARCH64_SRE/portmacro.h index 7f4ee78b0..5810741d2 100644 --- a/portable/GCC/ARM_AARCH64_SRE/portmacro.h +++ b/portable/GCC/ARM_AARCH64_SRE/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c index 9b3c844eb..67bb0fc8c 100644 --- a/portable/GCC/ARM_CA9/port.c +++ b/portable/GCC/ARM_CA9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S index 9e8484187..5df123479 100644 --- a/portable/GCC/ARM_CA9/portASM.S +++ b/portable/GCC/ARM_CA9/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h index c3c19e3e2..1ded79c8c 100644 --- a/portable/GCC/ARM_CA9/portmacro.h +++ b/portable/GCC/ARM_CA9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c index 97af18b07..4f14482e2 100644 --- a/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c index 9c6279e49..fd3229a76 100644 --- a/portable/GCC/ARM_CM0/port.c +++ b/portable/GCC/ARM_CM0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM0/portasm.c b/portable/GCC/ARM_CM0/portasm.c index 48ef2f8d8..179a71546 100644 --- a/portable/GCC/ARM_CM0/portasm.c +++ b/portable/GCC/ARM_CM0/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM0/portasm.h b/portable/GCC/ARM_CM0/portasm.h index 109dac30d..346507531 100644 --- a/portable/GCC/ARM_CM0/portasm.h +++ b/portable/GCC/ARM_CM0/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h index fde921506..5acb2dcd2 100644 --- a/portable/GCC/ARM_CM0/portmacro.h +++ b/portable/GCC/ARM_CM0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c index 970ec0a65..7a62caff0 100644 --- a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c index b6e836f9c..978d35259 100644 --- a/portable/GCC/ARM_CM23/non_secure/portasm.c +++ b/portable/GCC/ARM_CM23/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.h b/portable/GCC/ARM_CM23/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM23/non_secure/portasm.h +++ b/portable/GCC/ARM_CM23/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h index 3385afd8a..f0d8b273d 100644 --- a/portable/GCC/ARM_CM23/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_CM23/secure/secure_context.c +++ b/portable/GCC/ARM_CM23/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_CM23/secure/secure_context.h b/portable/GCC/ARM_CM23/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_CM23/secure/secure_context.h +++ b/portable/GCC/ARM_CM23/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/secure/secure_context_port.c b/portable/GCC/ARM_CM23/secure/secure_context_port.c index a55182f18..32559ad04 100644 --- a/portable/GCC/ARM_CM23/secure/secure_context_port.c +++ b/portable/GCC/ARM_CM23/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_CM23/secure/secure_heap.c +++ b/portable/GCC/ARM_CM23/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.h b/portable/GCC/ARM_CM23/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_CM23/secure/secure_heap.h +++ b/portable/GCC/ARM_CM23/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/secure/secure_init.c b/portable/GCC/ARM_CM23/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_CM23/secure/secure_init.c +++ b/portable/GCC/ARM_CM23/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/secure/secure_init.h b/portable/GCC/ARM_CM23/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_CM23/secure/secure_init.h +++ b/portable/GCC/ARM_CM23/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/portable/GCC/ARM_CM23/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_CM23/secure/secure_port_macros.h +++ b/portable/GCC/ARM_CM23/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c index 970ec0a65..7a62caff0 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c index 3015b9ec5..d215f8f73 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h index 3385afd8a..f0d8b273d 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c index 9dad11bb9..f2a6a1e83 100644 --- a/portable/GCC/ARM_CM3/port.c +++ b/portable/GCC/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h index 960c2a88b..75dbcfa6c 100644 --- a/portable/GCC/ARM_CM3/portmacro.h +++ b/portable/GCC/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/GCC/ARM_CM33/non_secure/portasm.c +++ b/portable/GCC/ARM_CM33/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.h b/portable/GCC/ARM_CM33/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM33/non_secure/portasm.h +++ b/portable/GCC/ARM_CM33/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h index a78432994..02e5c92b0 100644 --- a/portable/GCC/ARM_CM33/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_CM33/secure/secure_context.c +++ b/portable/GCC/ARM_CM33/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_CM33/secure/secure_context.h b/portable/GCC/ARM_CM33/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_CM33/secure/secure_context.h +++ b/portable/GCC/ARM_CM33/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/secure/secure_context_port.c b/portable/GCC/ARM_CM33/secure/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/GCC/ARM_CM33/secure/secure_context_port.c +++ b/portable/GCC/ARM_CM33/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_CM33/secure/secure_heap.c +++ b/portable/GCC/ARM_CM33/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.h b/portable/GCC/ARM_CM33/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_CM33/secure/secure_heap.h +++ b/portable/GCC/ARM_CM33/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/secure/secure_init.c b/portable/GCC/ARM_CM33/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_CM33/secure/secure_init.c +++ b/portable/GCC/ARM_CM33/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/secure/secure_init.h b/portable/GCC/ARM_CM33/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_CM33/secure/secure_init.h +++ b/portable/GCC/ARM_CM33/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/portable/GCC/ARM_CM33/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_CM33/secure/secure_port_macros.h +++ b/portable/GCC/ARM_CM33/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h index a78432994..9447e6558 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 1 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM35P/non_secure/port.c +++ b/portable/GCC/ARM_CM35P/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portasm.c +++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.h b/portable/GCC/ARM_CM35P/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portasm.h +++ b/portable/GCC/ARM_CM35P/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h index e974d3657..9c78947b0 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.c b/portable/GCC/ARM_CM35P/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_context.c +++ b/portable/GCC/ARM_CM35P/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.h b/portable/GCC/ARM_CM35P/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_context.h +++ b/portable/GCC/ARM_CM35P/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/secure/secure_context_port.c b/portable/GCC/ARM_CM35P/secure/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_context_port.c +++ b/portable/GCC/ARM_CM35P/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_heap.c +++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.h b/portable/GCC/ARM_CM35P/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_heap.h +++ b/portable/GCC/ARM_CM35P/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.c b/portable/GCC/ARM_CM35P/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_init.c +++ b/portable/GCC/ARM_CM35P/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.h b/portable/GCC/ARM_CM35P/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_init.h +++ b/portable/GCC/ARM_CM35P/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P/secure/secure_port_macros.h b/portable/GCC/ARM_CM35P/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_CM35P/secure/secure_port_macros.h +++ b/portable/GCC/ARM_CM35P/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h index e974d3657..9c78947b0 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c index 56e7fbdfa..428e6e84a 100644 --- a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c index 68b0140c1..8c4dd7800 100644 --- a/portable/GCC/ARM_CM3_MPU/port.c +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h index f3f87f548..a2e6883c0 100644 --- a/portable/GCC/ARM_CM3_MPU/portmacro.h +++ b/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c index 3d82e198b..e6b481b1d 100644 --- a/portable/GCC/ARM_CM4F/port.c +++ b/portable/GCC/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h index d1f1a40a6..0a91d7c92 100644 --- a/portable/GCC/ARM_CM4F/portmacro.h +++ b/portable/GCC/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c index 56e7fbdfa..428e6e84a 100644 --- a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index 918a26d11..79f5e76d5 100644 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h index e4c325d3c..581b09d5c 100644 --- a/portable/GCC/ARM_CM4_MPU/portmacro.h +++ b/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/non_secure/port.c b/portable/GCC/ARM_CM52/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM52/non_secure/port.c +++ b/portable/GCC/ARM_CM52/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM52/non_secure/portasm.c b/portable/GCC/ARM_CM52/non_secure/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/GCC/ARM_CM52/non_secure/portasm.c +++ b/portable/GCC/ARM_CM52/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM52/non_secure/portasm.h b/portable/GCC/ARM_CM52/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM52/non_secure/portasm.h +++ b/portable/GCC/ARM_CM52/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/non_secure/portmacro.h b/portable/GCC/ARM_CM52/non_secure/portmacro.h index e85f7bbe0..a8f48a46a 100644 --- a/portable/GCC/ARM_CM52/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM52/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM52/secure/secure_context.c b/portable/GCC/ARM_CM52/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_CM52/secure/secure_context.c +++ b/portable/GCC/ARM_CM52/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_CM52/secure/secure_context.h b/portable/GCC/ARM_CM52/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_CM52/secure/secure_context.h +++ b/portable/GCC/ARM_CM52/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/secure/secure_context_port.c b/portable/GCC/ARM_CM52/secure/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/GCC/ARM_CM52/secure/secure_context_port.c +++ b/portable/GCC/ARM_CM52/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/secure/secure_heap.c b/portable/GCC/ARM_CM52/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_CM52/secure/secure_heap.c +++ b/portable/GCC/ARM_CM52/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/secure/secure_heap.h b/portable/GCC/ARM_CM52/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_CM52/secure/secure_heap.h +++ b/portable/GCC/ARM_CM52/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/secure/secure_init.c b/portable/GCC/ARM_CM52/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_CM52/secure/secure_init.c +++ b/portable/GCC/ARM_CM52/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/secure/secure_init.h b/portable/GCC/ARM_CM52/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_CM52/secure/secure_init.h +++ b/portable/GCC/ARM_CM52/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52/secure/secure_port_macros.h b/portable/GCC/ARM_CM52/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_CM52/secure/secure_port_macros.h +++ b/portable/GCC/ARM_CM52/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/port.c b/portable/GCC/ARM_CM52_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM52_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h index e85f7bbe0..a8f48a46a 100644 --- a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM55/non_secure/port.c +++ b/portable/GCC/ARM_CM55/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/GCC/ARM_CM55/non_secure/portasm.c +++ b/portable/GCC/ARM_CM55/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.h b/portable/GCC/ARM_CM55/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM55/non_secure/portasm.h +++ b/portable/GCC/ARM_CM55/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h index 8cb6e6556..814ec9c56 100644 --- a/portable/GCC/ARM_CM55/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM55/secure/secure_context.c b/portable/GCC/ARM_CM55/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_CM55/secure/secure_context.c +++ b/portable/GCC/ARM_CM55/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_CM55/secure/secure_context.h b/portable/GCC/ARM_CM55/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_CM55/secure/secure_context.h +++ b/portable/GCC/ARM_CM55/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/secure/secure_context_port.c b/portable/GCC/ARM_CM55/secure/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/GCC/ARM_CM55/secure/secure_context_port.c +++ b/portable/GCC/ARM_CM55/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_CM55/secure/secure_heap.c +++ b/portable/GCC/ARM_CM55/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.h b/portable/GCC/ARM_CM55/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_CM55/secure/secure_heap.h +++ b/portable/GCC/ARM_CM55/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/secure/secure_init.c b/portable/GCC/ARM_CM55/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_CM55/secure/secure_init.c +++ b/portable/GCC/ARM_CM55/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/secure/secure_init.h b/portable/GCC/ARM_CM55/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_CM55/secure/secure_init.h +++ b/portable/GCC/ARM_CM55/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55/secure/secure_port_macros.h b/portable/GCC/ARM_CM55/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_CM55/secure/secure_port_macros.h +++ b/portable/GCC/ARM_CM55/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h index 8cb6e6556..814ec9c56 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c index 2c9e1697e..6586980f4 100644 --- a/portable/GCC/ARM_CM7/r0p1/port.c +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h index d352f209a..4bc490b98 100644 --- a/portable/GCC/ARM_CM7/r0p1/portmacro.h +++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM85/non_secure/port.c +++ b/portable/GCC/ARM_CM85/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/GCC/ARM_CM85/non_secure/portasm.c +++ b/portable/GCC/ARM_CM85/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.h b/portable/GCC/ARM_CM85/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM85/non_secure/portasm.h +++ b/portable/GCC/ARM_CM85/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h index ef5f73a9f..88615be17 100644 --- a/portable/GCC/ARM_CM85/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_CM85/secure/secure_context.c +++ b/portable/GCC/ARM_CM85/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_CM85/secure/secure_context.h b/portable/GCC/ARM_CM85/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_CM85/secure/secure_context.h +++ b/portable/GCC/ARM_CM85/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/secure/secure_context_port.c b/portable/GCC/ARM_CM85/secure/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/GCC/ARM_CM85/secure/secure_context_port.c +++ b/portable/GCC/ARM_CM85/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_CM85/secure/secure_heap.c +++ b/portable/GCC/ARM_CM85/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.h b/portable/GCC/ARM_CM85/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_CM85/secure/secure_heap.h +++ b/portable/GCC/ARM_CM85/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/secure/secure_init.c b/portable/GCC/ARM_CM85/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_CM85/secure/secure_init.c +++ b/portable/GCC/ARM_CM85/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/secure/secure_init.h b/portable/GCC/ARM_CM85/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_CM85/secure/secure_init.h +++ b/portable/GCC/ARM_CM85/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/portable/GCC/ARM_CM85/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_CM85/secure/secure_port_macros.h +++ b/portable/GCC/ARM_CM85/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h index ef5f73a9f..88615be17 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c index 6902fb43c..72658e8d7 100644 --- a/portable/GCC/ARM_CR5/port.c +++ b/portable/GCC/ARM_CR5/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S index 1f9dbef14..3c39ef1b6 100644 --- a/portable/GCC/ARM_CR5/portASM.S +++ b/portable/GCC/ARM_CR5/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CR5/portmacro.h b/portable/GCC/ARM_CR5/portmacro.h index 31c3f1fad..35336e569 100644 --- a/portable/GCC/ARM_CR5/portmacro.h +++ b/portable/GCC/ARM_CR5/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c index f53266114..2d08949d2 100644 --- a/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CR82/port.c b/portable/GCC/ARM_CR82/port.c index 504ed5479..5030a528e 100644 --- a/portable/GCC/ARM_CR82/port.c +++ b/portable/GCC/ARM_CR82/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025-2026 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CR82/portASM.S b/portable/GCC/ARM_CR82/portASM.S index 4d952188a..12233481f 100644 --- a/portable/GCC/ARM_CR82/portASM.S +++ b/portable/GCC/ARM_CR82/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025-2026 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CR82/portmacro.h b/portable/GCC/ARM_CR82/portmacro.h index 86cbcbd4e..0df69921c 100644 --- a/portable/GCC/ARM_CR82/portmacro.h +++ b/portable/GCC/ARM_CR82/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025-2026 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S index 92c497598..caf31ff76 100644 --- a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S +++ b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_MPU/port.c b/portable/GCC/ARM_CRx_MPU/port.c index c4702d28c..56ff38384 100644 --- a/portable/GCC/ARM_CRx_MPU/port.c +++ b/portable/GCC/ARM_CRx_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_MPU/portASM.S b/portable/GCC/ARM_CRx_MPU/portASM.S index ee40f1434..2b6f22ef2 100644 --- a/portable/GCC/ARM_CRx_MPU/portASM.S +++ b/portable/GCC/ARM_CRx_MPU/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_MPU/portmacro.h b/portable/GCC/ARM_CRx_MPU/portmacro.h index 2e1bd1623..1eb8f0162 100644 --- a/portable/GCC/ARM_CRx_MPU/portmacro.h +++ b/portable/GCC/ARM_CRx_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h index f322468ac..c9573e419 100644 --- a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h +++ b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c index fc2a0dffa..81b16dcf6 100644 --- a/portable/GCC/ARM_CRx_No_GIC/port.c +++ b/portable/GCC/ARM_CRx_No_GIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S index fbf766d71..de9845e0f 100644 --- a/portable/GCC/ARM_CRx_No_GIC/portASM.S +++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h index 68d47104a..b29bd9be1 100644 --- a/portable/GCC/ARM_CRx_No_GIC/portmacro.h +++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c index d4ba99cde..33410a0c3 100644 --- a/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/port.c b/portable/GCC/ARM_STAR_MC3/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_STAR_MC3/non_secure/port.c +++ b/portable/GCC/ARM_STAR_MC3/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c index 15f9f47e1..0ebbe48a4 100644 --- a/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h b/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h index c79ab8589..2295105ee 100644 --- a/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h b/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_context.c b/portable/GCC/ARM_STAR_MC3/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_context.c +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_context.h b/portable/GCC/ARM_STAR_MC3/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_context.h +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c b/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c index 57c94b663..2d3d9439d 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_init.c b/portable/GCC/ARM_STAR_MC3/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_init.c +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_init.h b/portable/GCC/ARM_STAR_MC3/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_init.h +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h b/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c index 263cd04aa..4b984932d 100644 --- a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c index e7f656eaa..598e772fa 100644 --- a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -134,8 +133,21 @@ ( " .syntax unified \n" " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulFirstTaskLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -158,6 +170,14 @@ " mov r0, #0 \n" " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + #if ( configNUMBER_OF_CORES > 1 ) + " \n" + " .align 4 \n" + "ulFirstTaskLiteralPool: \n" + " .word %c0 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" (configCORE_ID_REGISTER) + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ ); } @@ -422,20 +442,43 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " clrm {r1-r4} \n" /* Clear r1-r4. */ #endif /* configENABLE_PAC */ " \n" + /* + * The SMP-specific logic below is derived from the Raspberry Pi + * implementation in the FreeRTOS-Kernel-Community-Supported-Ports project. + * Source: GCC/RP2350_ARM_NTZ/non_secure/portasm.c + * Upstream commit: 8b2955f6d97bf4cd582db9f5b62d9eb1587b76d7 + */ + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " str r0, [r1] \n" /* Save the new top of stack in TCB. */ " \n" " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ " dsb \n" " isb \n" + #if ( configNUMBER_OF_CORES > 1) + " mov r0, r2 \n" /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " bl vTaskSwitchContext \n" " mov r0, #0 \n" /* r0 = 0. */ " msr basepri, r0 \n" /* Enable interrupts. */ " \n" + #if ( configNUMBER_OF_CORES == 1) " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + #else /* if ( configNUMBER_OF_CORES == 1) */ + " ldr r1, =ulPendSVLiteralPool \n" /* Get the location of the current TCB and the Id of the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core Id */ + " ldr r1, [r3, r2, LSL #2] \n" /* r1 = pxCurrentTCBs[CORE_ID] */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ " \n" #if ( configENABLE_PAC == 1 ) @@ -458,7 +501,16 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ " msr psp, r0 \n" /* Remember the new top of stack for the task. */ " bx r3 \n" - ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #if ( configNUMBER_OF_CORES > 1 ) + " .align 4 \n" + " ulPendSVLiteralPool: \n" + " .word %c1 \n" /* CORE_ID_REGISTER */ + " .word pxCurrentTCBs \n" + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configCORE_ID_REGISTER ) + #else /* #if ( configNUMBER_OF_CORES > 1 ) */ + :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + ); } diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h index c79ab8589..2295105ee 100644 --- a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __attribute__( ( used ) ) +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c index aabb7bde5..ff80a8b81 100644 --- a/portable/GCC/ATMega323/port.c +++ b/portable/GCC/ATMega323/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ATMega323/portmacro.h b/portable/GCC/ATMega323/portmacro.h index f8870d481..6ed5e4295 100644 --- a/portable/GCC/ATMega323/portmacro.h +++ b/portable/GCC/ATMega323/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/AVR32_UC3/exception.S b/portable/GCC/AVR32_UC3/exception.S index 312916962..4e1b29703 100644 --- a/portable/GCC/AVR32_UC3/exception.S +++ b/portable/GCC/AVR32_UC3/exception.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c index 53664931b..984ef56a0 100644 --- a/portable/GCC/AVR32_UC3/port.c +++ b/portable/GCC/AVR32_UC3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h index 35760134a..d96a629b5 100644 --- a/portable/GCC/AVR32_UC3/portmacro.h +++ b/portable/GCC/AVR32_UC3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/GCC/CORTUS_APS3/port.c b/portable/GCC/CORTUS_APS3/port.c index db9e51dd5..8ea06df16 100644 --- a/portable/GCC/CORTUS_APS3/port.c +++ b/portable/GCC/CORTUS_APS3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/CORTUS_APS3/portmacro.h b/portable/GCC/CORTUS_APS3/portmacro.h index e41ff0198..a18af0f6f 100644 --- a/portable/GCC/CORTUS_APS3/portmacro.h +++ b/portable/GCC/CORTUS_APS3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ColdFire_V2/port.c b/portable/GCC/ColdFire_V2/port.c index 3673c10d1..e3bbb6b9e 100644 --- a/portable/GCC/ColdFire_V2/port.c +++ b/portable/GCC/ColdFire_V2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ColdFire_V2/portasm.S b/portable/GCC/ColdFire_V2/portasm.S index 98bb1b820..4b746ca22 100644 --- a/portable/GCC/ColdFire_V2/portasm.S +++ b/portable/GCC/ColdFire_V2/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h index ed23c2175..95381ab36 100644 --- a/portable/GCC/ColdFire_V2/portmacro.h +++ b/portable/GCC/ColdFire_V2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c index fbe1736fe..f8693b37b 100644 --- a/portable/GCC/H8S2329/port.c +++ b/portable/GCC/H8S2329/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/H8S2329/portmacro.h b/portable/GCC/H8S2329/portmacro.h index bcc8f0fe0..a954d4335 100644 --- a/portable/GCC/H8S2329/portmacro.h +++ b/portable/GCC/H8S2329/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c index a1a378545..4355a3f11 100644 --- a/portable/GCC/HCS12/port.c +++ b/portable/GCC/HCS12/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/HCS12/portmacro.h b/portable/GCC/HCS12/portmacro.h index 8dd6b459a..4d02ad54e 100644 --- a/portable/GCC/HCS12/portmacro.h +++ b/portable/GCC/HCS12/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h index 5f5aae6f7..18e10bf91 100644 --- a/portable/GCC/IA32_flat/ISR_Support.h +++ b/portable/GCC/IA32_flat/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c index ebe38d92d..682cce951 100644 --- a/portable/GCC/IA32_flat/port.c +++ b/portable/GCC/IA32_flat/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/IA32_flat/portASM.S b/portable/GCC/IA32_flat/portASM.S index 2f4a72ed3..c01b32bce 100644 --- a/portable/GCC/IA32_flat/portASM.S +++ b/portable/GCC/IA32_flat/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/IA32_flat/portmacro.h b/portable/GCC/IA32_flat/portmacro.h index 01b8d05d2..085250e04 100644 --- a/portable/GCC/IA32_flat/portmacro.h +++ b/portable/GCC/IA32_flat/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c index 13444bbcc..48a1a7921 100644 --- a/portable/GCC/MSP430F449/port.c +++ b/portable/GCC/MSP430F449/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h index f228c24ab..de2014683 100644 --- a/portable/GCC/MSP430F449/portmacro.h +++ b/portable/GCC/MSP430F449/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c index 24497d550..fb8b410be 100644 --- a/portable/GCC/MicroBlaze/port.c +++ b/portable/GCC/MicroBlaze/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlaze/portasm.s b/portable/GCC/MicroBlaze/portasm.s index c9ea905e7..b9c1dc8b3 100644 --- a/portable/GCC/MicroBlaze/portasm.s +++ b/portable/GCC/MicroBlaze/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h index 36bffb8a1..a81e07cde 100644 --- a/portable/GCC/MicroBlaze/portmacro.h +++ b/portable/GCC/MicroBlaze/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c index 60b13f6e3..1557af645 100644 --- a/portable/GCC/MicroBlazeV8/port.c +++ b/portable/GCC/MicroBlazeV8/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV8/port_exceptions.c b/portable/GCC/MicroBlazeV8/port_exceptions.c index e98550cbf..281a328b4 100644 --- a/portable/GCC/MicroBlazeV8/port_exceptions.c +++ b/portable/GCC/MicroBlazeV8/port_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV8/portasm.S b/portable/GCC/MicroBlazeV8/portasm.S index cd3a8ff25..36829767d 100644 --- a/portable/GCC/MicroBlazeV8/portasm.S +++ b/portable/GCC/MicroBlazeV8/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h index 641fa4387..d23214ea4 100644 --- a/portable/GCC/MicroBlazeV8/portmacro.h +++ b/portable/GCC/MicroBlazeV8/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c index d10bbc7bc..7a94ece00 100644 --- a/portable/GCC/MicroBlazeV9/port.c +++ b/portable/GCC/MicroBlazeV9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c index 0d126dbae..21dd28844 100644 --- a/portable/GCC/MicroBlazeV9/port_exceptions.c +++ b/portable/GCC/MicroBlazeV9/port_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV9/portasm.S b/portable/GCC/MicroBlazeV9/portasm.S index 269bf97ed..7480e76ed 100644 --- a/portable/GCC/MicroBlazeV9/portasm.S +++ b/portable/GCC/MicroBlazeV9/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h index a668d8968..1fb9c8259 100644 --- a/portable/GCC/MicroBlazeV9/portmacro.h +++ b/portable/GCC/MicroBlazeV9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/NiosII/port.c b/portable/GCC/NiosII/port.c index 37f0f5a71..974c7d121 100644 --- a/portable/GCC/NiosII/port.c +++ b/portable/GCC/NiosII/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/NiosII/port_asm.S b/portable/GCC/NiosII/port_asm.S index df6356a86..1485ab3fc 100644 --- a/portable/GCC/NiosII/port_asm.S +++ b/portable/GCC/NiosII/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h index 1515e8376..957f4db79 100644 --- a/portable/GCC/NiosII/portmacro.h +++ b/portable/GCC/NiosII/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/portable/GCC/PPC405_Xilinx/FPU_Macros.h index c2484a6d6..8446c9ae1 100644 --- a/portable/GCC/PPC405_Xilinx/FPU_Macros.h +++ b/portable/GCC/PPC405_Xilinx/FPU_Macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC405_Xilinx/port.c b/portable/GCC/PPC405_Xilinx/port.c index 1fe8f6e14..c815cf265 100644 --- a/portable/GCC/PPC405_Xilinx/port.c +++ b/portable/GCC/PPC405_Xilinx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC405_Xilinx/portasm.S b/portable/GCC/PPC405_Xilinx/portasm.S index 896fd2e32..db3e3b916 100644 --- a/portable/GCC/PPC405_Xilinx/portasm.S +++ b/portable/GCC/PPC405_Xilinx/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC405_Xilinx/portmacro.h b/portable/GCC/PPC405_Xilinx/portmacro.h index 7cc2adbcb..128d75c37 100644 --- a/portable/GCC/PPC405_Xilinx/portmacro.h +++ b/portable/GCC/PPC405_Xilinx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/portable/GCC/PPC440_Xilinx/FPU_Macros.h index c2484a6d6..8446c9ae1 100644 --- a/portable/GCC/PPC440_Xilinx/FPU_Macros.h +++ b/portable/GCC/PPC440_Xilinx/FPU_Macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC440_Xilinx/port.c b/portable/GCC/PPC440_Xilinx/port.c index 496771808..a17c25918 100644 --- a/portable/GCC/PPC440_Xilinx/port.c +++ b/portable/GCC/PPC440_Xilinx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC440_Xilinx/portasm.S b/portable/GCC/PPC440_Xilinx/portasm.S index 896fd2e32..db3e3b916 100644 --- a/portable/GCC/PPC440_Xilinx/portasm.S +++ b/portable/GCC/PPC440_Xilinx/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/PPC440_Xilinx/portmacro.h b/portable/GCC/PPC440_Xilinx/portmacro.h index 7cc2adbcb..128d75c37 100644 --- a/portable/GCC/PPC440_Xilinx/portmacro.h +++ b/portable/GCC/PPC440_Xilinx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h index f0e69b876..4d8a5fb53 100644 --- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h +++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h index 628ed8ad3..3be456cb4 100644 --- a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h index e660e1f9b..9f93824bd 100644 --- a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h index ce8ab7887..5b9ef4c06 100644 --- a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c index 3efa1c52a..32eaa335d 100644 --- a/portable/GCC/RISC-V/port.c +++ b/portable/GCC/RISC-V/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -90,7 +90,6 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) ); uint64_t ullNextTime = 0ULL; const uint64_t * pullNextTime = &ullNextTime; const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ -UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; volatile uint64_t * pullMachineTimerCompareRegister = NULL; /* Holds the critical nesting value - deliberately non-zero at start up to @@ -136,7 +135,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; __asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) ); - pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( configMTIMECMP_BASE_ADDRESS + ( ulHartId * sizeof( uint64_t ) ) ); do { @@ -154,7 +153,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; } -#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ +#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S index 949ace3bf..9d36d78f9 100644 --- a/portable/GCC/RISC-V/portASM.S +++ b/portable/GCC/RISC-V/portASM.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h index b211df4c5..0869a82b6 100644 --- a/portable/GCC/RISC-V/portContext.h +++ b/portable/GCC/RISC-V/portContext.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h index 5ba2f8ea2..a516a2467 100644 --- a/portable/GCC/RISC-V/portmacro.h +++ b/portable/GCC/RISC-V/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h index c4c8f868a..788718089 100644 --- a/portable/GCC/RL78/isr_support.h +++ b/portable/GCC/RL78/isr_support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c index 835ed620d..7dad2b12b 100644 --- a/portable/GCC/RL78/port.c +++ b/portable/GCC/RL78/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RL78/portasm.S b/portable/GCC/RL78/portasm.S index 75868e02f..2f24db972 100644 --- a/portable/GCC/RL78/portasm.S +++ b/portable/GCC/RL78/portasm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h index 0d228bbd2..730cf50a3 100644 --- a/portable/GCC/RL78/portmacro.h +++ b/portable/GCC/RL78/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c index 46c4a0c91..854587d44 100644 --- a/portable/GCC/RX100/port.c +++ b/portable/GCC/RX100/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h index 315b30985..052ee0be3 100644 --- a/portable/GCC/RX100/portmacro.h +++ b/portable/GCC/RX100/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX200/port.c b/portable/GCC/RX200/port.c index e1189810b..e58c96d13 100644 --- a/portable/GCC/RX200/port.c +++ b/portable/GCC/RX200/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h index 03b901a67..16e41bc61 100644 --- a/portable/GCC/RX200/portmacro.h +++ b/portable/GCC/RX200/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c index 37ff5cb32..9e6a7b443 100644 --- a/portable/GCC/RX600/port.c +++ b/portable/GCC/RX600/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h index e2fdaa6ea..187b2b5bd 100644 --- a/portable/GCC/RX600/portmacro.h +++ b/portable/GCC/RX600/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c index 292883d6b..c31d2c65c 100644 --- a/portable/GCC/RX600v2/port.c +++ b/portable/GCC/RX600v2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h index e2fdaa6ea..187b2b5bd 100644 --- a/portable/GCC/RX600v2/portmacro.h +++ b/portable/GCC/RX600v2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX700v3_DPFPU/port.c b/portable/GCC/RX700v3_DPFPU/port.c index fef69f0e0..8ed1bcfa4 100644 --- a/portable/GCC/RX700v3_DPFPU/port.c +++ b/portable/GCC/RX700v3_DPFPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h index 737fdb0ad..bbfd24f90 100644 --- a/portable/GCC/RX700v3_DPFPU/portmacro.h +++ b/portable/GCC/RX700v3_DPFPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/STR75x/port.c b/portable/GCC/STR75x/port.c index 5dbff430b..941b72b5f 100644 --- a/portable/GCC/STR75x/port.c +++ b/portable/GCC/STR75x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/STR75x/portISR.c b/portable/GCC/STR75x/portISR.c index 91ee65198..110c22a80 100644 --- a/portable/GCC/STR75x/portISR.c +++ b/portable/GCC/STR75x/portISR.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h index fc5c288ac..81a30dcb3 100644 --- a/portable/GCC/STR75x/portmacro.h +++ b/portable/GCC/STR75x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/TriCore_1782/port.c b/portable/GCC/TriCore_1782/port.c index 28946fe38..1579d8e72 100644 --- a/portable/GCC/TriCore_1782/port.c +++ b/portable/GCC/TriCore_1782/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h index 1822a8cc3..c1e0b14d5 100644 --- a/portable/GCC/TriCore_1782/portmacro.h +++ b/portable/GCC/TriCore_1782/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/GCC/TriCore_1782/porttrap.c b/portable/GCC/TriCore_1782/porttrap.c index 9253bf8e8..f0600d754 100644 --- a/portable/GCC/TriCore_1782/porttrap.c +++ b/portable/GCC/TriCore_1782/porttrap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/78K0R/ISR_Support.h b/portable/IAR/78K0R/ISR_Support.h index e451c9c29..b5a1f4d1d 100644 --- a/portable/IAR/78K0R/ISR_Support.h +++ b/portable/IAR/78K0R/ISR_Support.h @@ -1,5 +1,5 @@ ; /* - * ; * FreeRTOS Kernel V11.3.0 + * ; * FreeRTOS Kernel * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * ; * * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/78K0R/port.c b/portable/IAR/78K0R/port.c index d6fa14221..3183b89ab 100644 --- a/portable/IAR/78K0R/port.c +++ b/portable/IAR/78K0R/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/78K0R/portasm.s26 b/portable/IAR/78K0R/portasm.s26 index 4e204b87d..1cddc0caf 100644 --- a/portable/IAR/78K0R/portasm.s26 +++ b/portable/IAR/78K0R/portasm.s26 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/78K0R/portmacro.h b/portable/IAR/78K0R/portmacro.h index e01afa513..e0ac8fb02 100644 --- a/portable/IAR/78K0R/portmacro.h +++ b/portable/IAR/78K0R/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA5_No_GIC/port.c b/portable/IAR/ARM_CA5_No_GIC/port.c index 50bd6a9e2..31afbb567 100644 --- a/portable/IAR/ARM_CA5_No_GIC/port.c +++ b/portable/IAR/ARM_CA5_No_GIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.h b/portable/IAR/ARM_CA5_No_GIC/portASM.h index e0202f301..c3f9978d2 100644 --- a/portable/IAR/ARM_CA5_No_GIC/portASM.h +++ b/portable/IAR/ARM_CA5_No_GIC/portASM.h @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.s b/portable/IAR/ARM_CA5_No_GIC/portASM.s index ed7746d22..dcfaa6043 100644 --- a/portable/IAR/ARM_CA5_No_GIC/portASM.s +++ b/portable/IAR/ARM_CA5_No_GIC/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/portable/IAR/ARM_CA5_No_GIC/portmacro.h index 01662ea4b..8d5caeb8a 100644 --- a/portable/IAR/ARM_CA5_No_GIC/portmacro.h +++ b/portable/IAR/ARM_CA5_No_GIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c index 15e92512a..66852f9a7 100644 --- a/portable/IAR/ARM_CA9/port.c +++ b/portable/IAR/ARM_CA9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA9/portASM.h b/portable/IAR/ARM_CA9/portASM.h index e69e01671..181530b67 100644 --- a/portable/IAR/ARM_CA9/portASM.h +++ b/portable/IAR/ARM_CA9/portASM.h @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA9/portASM.s b/portable/IAR/ARM_CA9/portASM.s index a955031cf..d7d07995f 100644 --- a/portable/IAR/ARM_CA9/portASM.s +++ b/portable/IAR/ARM_CA9/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CA9/portmacro.h b/portable/IAR/ARM_CA9/portmacro.h index bff450d6a..f1cb124a2 100644 --- a/portable/IAR/ARM_CA9/portmacro.h +++ b/portable/IAR/ARM_CA9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c index ea936d382..6f5ec0ad5 100644 --- a/portable/IAR/ARM_CM0/port.c +++ b/portable/IAR/ARM_CM0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM0/portasm.s b/portable/IAR/ARM_CM0/portasm.s index a94c4cd2b..6c19a1749 100644 --- a/portable/IAR/ARM_CM0/portasm.s +++ b/portable/IAR/ARM_CM0/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM0/portmacro.h b/portable/IAR/ARM_CM0/portmacro.h index 52cc22e95..a097db9df 100644 --- a/portable/IAR/ARM_CM0/portmacro.h +++ b/portable/IAR/ARM_CM0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S index 729dff1f3..9289bcbc2 100644 --- a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.h b/portable/IAR/ARM_CM23/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM23/non_secure/portasm.h +++ b/portable/IAR/ARM_CM23/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.s b/portable/IAR/ARM_CM23/non_secure/portasm.s index 2b93d5b60..6817abd7a 100644 --- a/portable/IAR/ARM_CM23/non_secure/portasm.s +++ b/portable/IAR/ARM_CM23/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h index c9215d885..46c2a2885 100644 --- a/portable/IAR/ARM_CM23/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM23/secure/secure_context.c b/portable/IAR/ARM_CM23/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_CM23/secure/secure_context.c +++ b/portable/IAR/ARM_CM23/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_CM23/secure/secure_context.h b/portable/IAR/ARM_CM23/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_CM23/secure/secure_context.h +++ b/portable/IAR/ARM_CM23/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s index a6f4cbe82..f70e89115 100644 --- a/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_CM23/secure/secure_heap.c +++ b/portable/IAR/ARM_CM23/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.h b/portable/IAR/ARM_CM23/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_CM23/secure/secure_heap.h +++ b/portable/IAR/ARM_CM23/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/secure/secure_init.c b/portable/IAR/ARM_CM23/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_CM23/secure/secure_init.c +++ b/portable/IAR/ARM_CM23/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/secure/secure_init.h b/portable/IAR/ARM_CM23/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_CM23/secure/secure_init.h +++ b/portable/IAR/ARM_CM23/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/portable/IAR/ARM_CM23/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_CM23/secure/secure_port_macros.h +++ b/portable/IAR/ARM_CM23/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S index 729dff1f3..9289bcbc2 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s index 336b16b09..bfe9eee4b 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h index c9215d885..46c2a2885 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 0 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c index 780dcf814..ef590cf95 100644 --- a/portable/IAR/ARM_CM3/port.c +++ b/portable/IAR/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM3/portasm.s b/portable/IAR/ARM_CM3/portasm.s index 8d8a96ff8..7b2afde98 100644 --- a/portable/IAR/ARM_CM3/portasm.s +++ b/portable/IAR/ARM_CM3/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM3/portmacro.h b/portable/IAR/ARM_CM3/portmacro.h index 1065f9462..f49c618c4 100644 --- a/portable/IAR/ARM_CM3/portmacro.h +++ b/portable/IAR/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.h b/portable/IAR/ARM_CM33/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM33/non_secure/portasm.h +++ b/portable/IAR/ARM_CM33/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/IAR/ARM_CM33/non_secure/portasm.s +++ b/portable/IAR/ARM_CM33/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h index 2dfa847aa..61da05503 100644 --- a/portable/IAR/ARM_CM33/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM33/secure/secure_context.c b/portable/IAR/ARM_CM33/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_CM33/secure/secure_context.c +++ b/portable/IAR/ARM_CM33/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_CM33/secure/secure_context.h b/portable/IAR/ARM_CM33/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_CM33/secure/secure_context.h +++ b/portable/IAR/ARM_CM33/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_CM33/secure/secure_heap.c +++ b/portable/IAR/ARM_CM33/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.h b/portable/IAR/ARM_CM33/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_CM33/secure/secure_heap.h +++ b/portable/IAR/ARM_CM33/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/secure/secure_init.c b/portable/IAR/ARM_CM33/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_CM33/secure/secure_init.c +++ b/portable/IAR/ARM_CM33/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/secure/secure_init.h b/portable/IAR/ARM_CM33/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_CM33/secure/secure_init.h +++ b/portable/IAR/ARM_CM33/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/portable/IAR/ARM_CM33/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_CM33/secure/secure_port_macros.h +++ b/portable/IAR/ARM_CM33/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h index 2dfa847aa..b9612e487 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 1 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM35P/non_secure/port.c +++ b/portable/IAR/ARM_CM35P/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.h b/portable/IAR/ARM_CM35P/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portasm.h +++ b/portable/IAR/ARM_CM35P/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portasm.s +++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h index a03a81e51..9f7c97b90 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.c b/portable/IAR/ARM_CM35P/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_context.c +++ b/portable/IAR/ARM_CM35P/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.h b/portable/IAR/ARM_CM35P/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_context.h +++ b/portable/IAR/ARM_CM35P/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_heap.c +++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.h b/portable/IAR/ARM_CM35P/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_heap.h +++ b/portable/IAR/ARM_CM35P/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.c b/portable/IAR/ARM_CM35P/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_init.c +++ b/portable/IAR/ARM_CM35P/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.h b/portable/IAR/ARM_CM35P/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_init.h +++ b/portable/IAR/ARM_CM35P/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P/secure/secure_port_macros.h b/portable/IAR/ARM_CM35P/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_CM35P/secure/secure_port_macros.h +++ b/portable/IAR/ARM_CM35P/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h index a03a81e51..9f7c97b90 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -52,6 +53,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 0 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c index fe6a4c223..b96329a05 100644 --- a/portable/IAR/ARM_CM4F/port.c +++ b/portable/IAR/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM4F/portasm.s b/portable/IAR/ARM_CM4F/portasm.s index 131bf18ed..a2e8c3009 100644 --- a/portable/IAR/ARM_CM4F/portasm.s +++ b/portable/IAR/ARM_CM4F/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM4F/portmacro.h b/portable/IAR/ARM_CM4F/portmacro.h index ef3c89f33..f3d8ace9d 100644 --- a/portable/IAR/ARM_CM4F/portmacro.h +++ b/portable/IAR/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S index ee1e2d66f..f01c01d42 100644 --- a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c index 1dd492a1e..720138f08 100644 --- a/portable/IAR/ARM_CM4F_MPU/port.c +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_CM4F_MPU/portasm.s b/portable/IAR/ARM_CM4F_MPU/portasm.s index b0341e712..9ce0e14d8 100644 --- a/portable/IAR/ARM_CM4F_MPU/portasm.s +++ b/portable/IAR/ARM_CM4F_MPU/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h index 77e906874..6b7600c15 100644 --- a/portable/IAR/ARM_CM4F_MPU/portmacro.h +++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/non_secure/port.c b/portable/IAR/ARM_CM52/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM52/non_secure/port.c +++ b/portable/IAR/ARM_CM52/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM52/non_secure/portasm.h b/portable/IAR/ARM_CM52/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM52/non_secure/portasm.h +++ b/portable/IAR/ARM_CM52/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/non_secure/portasm.s b/portable/IAR/ARM_CM52/non_secure/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/IAR/ARM_CM52/non_secure/portasm.s +++ b/portable/IAR/ARM_CM52/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_CM52/non_secure/portmacro.h b/portable/IAR/ARM_CM52/non_secure/portmacro.h index 13725fb54..d1e4d3a84 100644 --- a/portable/IAR/ARM_CM52/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM52/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM52/secure/secure_context.c b/portable/IAR/ARM_CM52/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_CM52/secure/secure_context.c +++ b/portable/IAR/ARM_CM52/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_CM52/secure/secure_context.h b/portable/IAR/ARM_CM52/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_CM52/secure/secure_context.h +++ b/portable/IAR/ARM_CM52/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/secure/secure_heap.c b/portable/IAR/ARM_CM52/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_CM52/secure/secure_heap.c +++ b/portable/IAR/ARM_CM52/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/secure/secure_heap.h b/portable/IAR/ARM_CM52/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_CM52/secure/secure_heap.h +++ b/portable/IAR/ARM_CM52/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/secure/secure_init.c b/portable/IAR/ARM_CM52/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_CM52/secure/secure_init.c +++ b/portable/IAR/ARM_CM52/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/secure/secure_init.h b/portable/IAR/ARM_CM52/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_CM52/secure/secure_init.h +++ b/portable/IAR/ARM_CM52/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52/secure/secure_port_macros.h b/portable/IAR/ARM_CM52/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_CM52/secure/secure_port_macros.h +++ b/portable/IAR/ARM_CM52/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/port.c b/portable/IAR/ARM_CM52_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM52_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h index 13725fb54..d1e4d3a84 100644 --- a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM55/non_secure/port.c +++ b/portable/IAR/ARM_CM55/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.h b/portable/IAR/ARM_CM55/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM55/non_secure/portasm.h +++ b/portable/IAR/ARM_CM55/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/IAR/ARM_CM55/non_secure/portasm.s +++ b/portable/IAR/ARM_CM55/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h index bb91c012f..e58485e40 100644 --- a/portable/IAR/ARM_CM55/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM55/secure/secure_context.c b/portable/IAR/ARM_CM55/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_CM55/secure/secure_context.c +++ b/portable/IAR/ARM_CM55/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_CM55/secure/secure_context.h b/portable/IAR/ARM_CM55/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_CM55/secure/secure_context.h +++ b/portable/IAR/ARM_CM55/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_CM55/secure/secure_heap.c +++ b/portable/IAR/ARM_CM55/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.h b/portable/IAR/ARM_CM55/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_CM55/secure/secure_heap.h +++ b/portable/IAR/ARM_CM55/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/secure/secure_init.c b/portable/IAR/ARM_CM55/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_CM55/secure/secure_init.c +++ b/portable/IAR/ARM_CM55/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/secure/secure_init.h b/portable/IAR/ARM_CM55/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_CM55/secure/secure_init.h +++ b/portable/IAR/ARM_CM55/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/portable/IAR/ARM_CM55/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_CM55/secure/secure_port_macros.h +++ b/portable/IAR/ARM_CM55/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h index bb91c012f..e58485e40 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c index 5a8f6851c..723389633 100644 --- a/portable/IAR/ARM_CM7/r0p1/port.c +++ b/portable/IAR/ARM_CM7/r0p1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM7/r0p1/portasm.s b/portable/IAR/ARM_CM7/r0p1/portasm.s index 71594c90e..56d4b3e04 100644 --- a/portable/IAR/ARM_CM7/r0p1/portasm.s +++ b/portable/IAR/ARM_CM7/r0p1/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM7/r0p1/portmacro.h b/portable/IAR/ARM_CM7/r0p1/portmacro.h index c3b8fe9eb..7c66ed3f9 100644 --- a/portable/IAR/ARM_CM7/r0p1/portmacro.h +++ b/portable/IAR/ARM_CM7/r0p1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM85/non_secure/port.c +++ b/portable/IAR/ARM_CM85/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.h b/portable/IAR/ARM_CM85/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM85/non_secure/portasm.h +++ b/portable/IAR/ARM_CM85/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/IAR/ARM_CM85/non_secure/portasm.s +++ b/portable/IAR/ARM_CM85/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h index 0b7c0ffa5..0268a9592 100644 --- a/portable/IAR/ARM_CM85/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CM85/secure/secure_context.c b/portable/IAR/ARM_CM85/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_CM85/secure/secure_context.c +++ b/portable/IAR/ARM_CM85/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_CM85/secure/secure_context.h b/portable/IAR/ARM_CM85/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_CM85/secure/secure_context.h +++ b/portable/IAR/ARM_CM85/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_CM85/secure/secure_heap.c +++ b/portable/IAR/ARM_CM85/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.h b/portable/IAR/ARM_CM85/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_CM85/secure/secure_heap.h +++ b/portable/IAR/ARM_CM85/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/secure/secure_init.c b/portable/IAR/ARM_CM85/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_CM85/secure/secure_init.c +++ b/portable/IAR/ARM_CM85/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/secure/secure_init.h b/portable/IAR/ARM_CM85/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_CM85/secure/secure_init.h +++ b/portable/IAR/ARM_CM85/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/portable/IAR/ARM_CM85/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_CM85/secure/secure_port_macros.h +++ b/portable/IAR/ARM_CM85/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h index 0b7c0ffa5..0268a9592 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h @@ -1,6 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -57,6 +58,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_CRx_No_GIC/port.c b/portable/IAR/ARM_CRx_No_GIC/port.c index 5e2f60670..1b5c0fb8e 100644 --- a/portable/IAR/ARM_CRx_No_GIC/port.c +++ b/portable/IAR/ARM_CRx_No_GIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CRx_No_GIC/portASM.s b/portable/IAR/ARM_CRx_No_GIC/portASM.s index 6c5e81a35..f37ad570b 100644 --- a/portable/IAR/ARM_CRx_No_GIC/portASM.s +++ b/portable/IAR/ARM_CRx_No_GIC/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/portable/IAR/ARM_CRx_No_GIC/portmacro.h index d8498bcc1..7707fcf02 100644 --- a/portable/IAR/ARM_CRx_No_GIC/portmacro.h +++ b/portable/IAR/ARM_CRx_No_GIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/port.c b/portable/IAR/ARM_STAR_MC3/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_STAR_MC3/non_secure/port.c +++ b/portable/IAR/ARM_STAR_MC3/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s index 64e9704a7..8d5988819 100644 --- a/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2024 Arm Limited and/or its affiliates * diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h b/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h index 90aa59b0f..8ee96052d 100644 --- a/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h b/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_context.c b/portable/IAR/ARM_STAR_MC3/secure/secure_context.c index 7518a8d9e..a91e5e891 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_context.c +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_context.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -213,8 +213,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) /* Were we able to get a free context? */ if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) { - /* Allocate the stack space. */ - pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + /* Allocate the stack space if possible. */ + if( ulSecureStackSize > ( UINT32_MAX - securecontextSTACK_SEAL_SIZE ) ) + { + pucStackMemory = NULL; + } + else + { + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + } if( pucStackMemory != NULL ) { diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_context.h b/portable/IAR/ARM_STAR_MC3/secure/secure_context.h index 74fcca2fb..e36a8e430 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_context.h +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_context.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s b/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s index 3875f42d0..27a8f3933 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c index ceb2d2cb0..896b53e2d 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h index 00de7c3f4..0e84a9d9d 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_init.c b/portable/IAR/ARM_STAR_MC3/secure/secure_init.c index b930448c2..c50d37668 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_init.c +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_init.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_init.h b/portable/IAR/ARM_STAR_MC3/secure/secure_init.h index b44a7b36e..ebe04900f 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_init.h +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_init.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h b/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h index e43291f11..a70da2c65 100644 --- a/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4511a141b..d2cb78e92 100644 --- a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c index 09fb69124..44a06555f 100644 --- a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024-2025 Arm Limited and/or its affiliates - * + * Copyright 2024-2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -441,7 +440,11 @@ static void prvTaskExitError( void ); * * @return CONTROL register value according to the configured PACBTI option. */ - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -535,6 +538,18 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ + +#if ( configNUMBER_OF_CORES > 1 ) + + /** + * @brief Platform/Application-defined function that wakes up the secondary cores. + * + * @return pdTRUE if the secondary cores were successfully woken up. + * pdFALSE otherwise. + */ + extern BaseType_t configWAKE_SECONDARY_CORES( void ); + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -550,7 +565,15 @@ portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIV * @brief Each task maintains its own interrupt status in the critical nesting * variable. */ -PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0UL; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + /* Flag to indicate that the primary core has completed its initialisation. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ #if ( configENABLE_TRUSTZONE == 1 ) @@ -853,7 +876,11 @@ static void prvTaskExitError( void ) * should instead call vTaskDelete( NULL ). Artificially force an assert() * to be triggered if configASSERT() is defined, then stop here so * application writers can catch the error. */ - configASSERT( ulCriticalNesting == ~0UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == ~0UL ); + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == ~0UL ); + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) @@ -1017,28 +1044,29 @@ void vPortYield( void ) /* PRIVILEGED_FUNCTION */ } /*-----------------------------------------------------------*/ -void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - portDISABLE_INTERRUPTS(); - ulCriticalNesting++; - - /* Barriers are normally not required but do ensure the code is - * completely within the specified behaviour for the architecture. */ - __asm volatile ( "dsb" ::: "memory" ); - __asm volatile ( "isb" ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ -{ - configASSERT( ulCriticalNesting ); - ulCriticalNesting--; - - if( ulCriticalNesting == 0 ) +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ { - portENABLE_INTERRUPTS(); + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); } -} + /*-----------------------------------------------------------*/ + + void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* configNUMBER_OF_CORES == 1 */ /*-----------------------------------------------------------*/ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ @@ -1046,6 +1074,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + traceISR_ENTER(); { /* Increment the RTOS tick. */ @@ -1060,6 +1092,10 @@ void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ traceISR_EXIT(); } } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } /*-----------------------------------------------------------*/ @@ -1548,7 +1584,11 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO { /* Check PACBTI security feature configuration before pushing the * CONTROL register's value on task's TCB. */ - ulControl = prvConfigurePACBTI( pdFALSE ); + #if ( configNUMBER_OF_CORES == 1 ) + ulControl = prvConfigurePACBTI( pdFALSE ); + #else /* configNUMBER_OF_CORES > 1 */ + ulControl = vConfigurePACBTI( pdFALSE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1737,91 +1777,17 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configCHECK_HANDLER_INSTALLATION */ - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) - { - volatile uint32_t ulImplementedPrioBits = 0; - volatile uint8_t ucMaxPriorityValue; - - /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to - * ensure interrupt entry is as fast and simple as possible. - * - * First, determine the number of priority bits available. Write to all - * possible bits in the priority setting for SVCall. */ - portNVIC_SHPR2_REG = 0xFF000000; - - /* Read the value back to see how many bits stuck. */ - ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); - - /* Use the same mask on the maximum system call priority. */ - ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - - /* Check that the maximum system call priority is nonzero after - * accounting for the number of priority bits supported by the - * hardware. A priority of 0 is invalid because setting the BASEPRI - * register to 0 unmasks all interrupts, and interrupts with priority 0 - * cannot be masked using BASEPRI. - * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ucMaxSysCallPriority ); - - /* Check that the bits not implemented in hardware are zero in - * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); - - /* Calculate the maximum acceptable priority group value for the number - * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - { - ulImplementedPrioBits++; - ucMaxPriorityValue <<= ( uint8_t ) 0x01; - } - - if( ulImplementedPrioBits == 8 ) - { - /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); - ulMaxPRIGROUPValue = 0; - } - else - { - ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; - } - - /* Shift the priority group value back to its position within the AIRCR - * register. */ - ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - - /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall - * the highest priority. */ - portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; - portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; - portNVIC_SHPR2_REG = 0; + vPortConfigureInterruptPriorities(); #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) { /* Set the CONTROL register value based on PACBTI security feature * configuration before starting the first task. */ - ( void ) prvConfigurePACBTI( pdTRUE ); + #if ( configNUMBER_OF_CORES == 1 ) + ( void ) prvConfigurePACBTI( pdTRUE ); + #else /* configNUMBER_OF_CORES > 1 */ + ( void ) vConfigurePACBTI( pdTRUE ); + #endif /* configNUMBER_OF_CORES */ } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ @@ -1832,12 +1798,47 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ } #endif /* configENABLE_MPU */ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. */ - vPortSetupTimerInterrupt(); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count for all cores. */ + for ( uint8_t ucCoreID = 0; ucCoreID < configNUMBER_OF_CORES; ucCoreID++ ) + { + ulCriticalNestings[ ucCoreID ] = 0; + } + /* Signal that primary core has done all the necessary initialisations. */ + ucPrimaryCoreInitDoneFlag = 1; + /* Wake up secondary cores */ + BaseType_t xWakeResult = configWAKE_SECONDARY_CORES(); + configASSERT( xWakeResult == pdTRUE ); - /* Initialize the critical nesting count ready for the first task. */ - ulCriticalNesting = 0; + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + vPortSetupTimerInterrupt(); + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { @@ -1854,7 +1855,11 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimization does not remove the * symbol. */ - vTaskSwitchContext(); + #if ( configNUMBER_OF_CORES > 1 ) + vTaskSwitchContext( portGET_CORE_ID() ); + #else + vTaskSwitchContext(); + #endif prvTaskExitError(); /* Should not get here. */ @@ -1866,7 +1871,11 @@ void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ { /* Not implemented in ports where there is nothing to return to. * Artificially force an assert. */ - configASSERT( ulCriticalNesting == 1000UL ); + #if ( configNUMBER_OF_CORES == 1 ) + configASSERT( ulCriticalNesting == 1000UL ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + configASSERT( ulCriticalNestings[ portGET_CORE_ID() ] == 1000UL ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ } /*-----------------------------------------------------------*/ @@ -2149,6 +2158,90 @@ BaseType_t xPortIsInsideInterrupt( void ) #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ +void vPortConfigureInterruptPriorities( void ) /* PRIVILEGED_FUNCTION */ +{ + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; +} +/*-----------------------------------------------------------*/ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, @@ -2245,36 +2338,214 @@ BaseType_t xPortIsInsideInterrupt( void ) /*-----------------------------------------------------------*/ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) - - static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) - { - uint32_t ulControl = 0x0; - - /* Ensure that PACBTI is implemented. */ - configASSERT( portID_ISAR5_REG != 0x0 ); - - /* Enable UsageFault exception. */ - portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - - #if ( configENABLE_PAC == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + #else /* configNUMBER_OF_CORES > 1 */ + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ) + #endif /* configNUMBER_OF_CORES */ { - ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); - } - #endif + uint32_t ulControl = 0x0; - #if ( configENABLE_BTI == 1 ) - { - ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); - } - #endif + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); - if( xWriteControlRegister == pdTRUE ) - { - __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); - } + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; - return ulControl; - } + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? */ + PRIVILEGED_DATA volatile uint32_t ulOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint32_t ulRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA volatile uint32_t ulGateWord[ eLockCount ]; + + __attribute__((weak)) void vInterruptCore( uint8_t ucCoreID ) + { + /* Default weak stub - platform specific implementation may override. */ + ( void ) ucCoreID; + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( volatile uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov r1, #0 \n" + "str r1, [%0] \n" + "sev \n" + "dsb \n" + "isb \n" + : + : "r" ( ulLock ) + : "memory", "r1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( volatile uint32_t * ulLock ) + { + /* + * Conservative ldrex/strex trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry strex only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + uint32_t ulVal; + uint32_t ulStatus; + + __asm volatile ( + " ldrex %0, [%1] \n" + : "=r" ( ulVal ) + : "r" ( ulLock ) + : "memory" + ); + + if( ulVal != 0U ) + { + __asm volatile ("clrex" ::: "memory"); + return 1U; + } + + __asm volatile ( + " strex %0, %2, [%1] \n" + : "=&r" ( ulStatus ) + : "r" ( ulLock ), "r" (1U) + : "memory" + ); + + if( ulStatus != 0U ) + { + return 1U; + } + __asm volatile ( "dmb" ::: "memory" ); + return 0U; + } + + +/*-----------------------------------------------------------*/ + + /* Read 32b value shared between cores. */ + static inline uint32_t prvGet32( volatile uint32_t * x ) + { + __asm( "dsb" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 32b value shared between cores. */ + static inline void prvSet32( volatile uint32_t * x, + uint32_t value ) + { + *x = value; + __asm( "dsb" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. */ + /* If spinlock is not available check if the core owns the lock. */ + /* If the core owns the lock wait increment the lock count by the core. */ + /* If core does not own the lock wait for the spinlock. */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != portUINT32_MAX ); + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + __asm volatile ( "wfe" ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], 1 ); + /* Set ulOwnedByCore. */ + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ulRecursionCountByLock by 1. */ + prvSet32( &ulRecursionCountByLock[ eLockNum ], ( prvGet32( &ulRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet32( &ulRecursionCountByLock[ eLockNum ] ) ) + { + prvSet32( &ulOwnedByCore[ ucCoreID ], ( prvGet32( &ulOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm volatile( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + return *(volatile uint8_t *)(configCORE_ID_REGISTER); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h index 4df2f4e06..b7021b024 100644 --- a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s index 2a530b622..2051f0112 100644 --- a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -41,7 +40,15 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#if ( configNUMBER_OF_CORES == 1) EXTERN pxCurrentTCB +#else /* if ( configNUMBER_OF_CORES == 1) */ + EXTERN pxCurrentTCBs +#endif EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) @@ -169,8 +176,15 @@ vRestoreContextOfFirstTask: #else /* configENABLE_MPU */ vRestoreContextOfFirstTask: +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulFirstTaskLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -193,6 +207,13 @@ vRestoreContextOfFirstTask: mov r0, #0 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ bx r2 /* Finally, branch to EXC_RETURN. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulFirstTaskLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ @@ -377,20 +398,37 @@ PendSV_Handler: clrm {r1-r4} /* Clear r1-r4. */ #endif /* configENABLE_PAC */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb + #if ( configNUMBER_OF_CORES > 1) + mov r0, r2 /* r0 = ucPortGetCoreID() */ + #endif /* if ( configNUMBER_OF_CORES == 1) */ bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ +#if ( configNUMBER_OF_CORES == 1) ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ +#else /* if ( configNUMBER_OF_CORES == 1) */ + ldr r1, =ulPendSVLiteralPool /* Get the location of the current TCB and the Id of the current core. */ + ldmia r1!, {r2, r3} + ldr r2, [r2] /* r2 = Core Id */ + ldr r1, [r3, r2, LSL #2] /* r1 = pxCurrentTCBs[CORE_ID] */ +#endif /* if ( configNUMBER_OF_CORES == 1) */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ #if ( configENABLE_PAC == 1 ) @@ -413,6 +451,13 @@ PendSV_Handler: msr psplim, r2 /* Restore the PSPLIM register value for the task. */ msr psp, r0 /* Remember the new top of stack for the task. */ bx r3 +#if ( configNUMBER_OF_CORES > 1 ) + /* Align to 4 bytes in ROM/code area (2^2 alignment, 0 fill). */ + ALIGNROM 2, 0 + ulPendSVLiteralPool: + DC32 configCORE_ID_REGISTER /* CORE_ID_REGISTER */ + DC32 pxCurrentTCBs +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h index 90aa59b0f..8ee96052d 100644 --- a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h @@ -1,7 +1,8 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -58,6 +59,7 @@ #define portHAS_ARMV8M_MAIN_EXTENSION 1 #define portARMV8M_MINOR_VERSION 1 #define portDONT_DISCARD __root +#define portVALIDATED_FOR_SMP 0 /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h index 237676dbd..8e602a1d0 100644 --- a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h @@ -1,8 +1,7 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * Copyright 2024 Arm Limited and/or its affiliates - * + * Copyright 2024, 2026 Arm Limited and/or its affiliates * * SPDX-License-Identifier: MIT * @@ -31,6 +30,8 @@ #ifndef PORTMACROCOMMON_H #define PORTMACROCOMMON_H +#include "mpu_wrappers.h" + /* *INDENT-OFF* */ #ifdef __cplusplus extern "C" { @@ -59,6 +60,19 @@ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. #endif /* configENABLE_TRUSTZONE */ +#if ( configNUMBER_OF_CORES > 1 ) + #if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) + #error "Multi-core SMP is currently only validated for Cortex-M33 non-TrustZone non-MPU port." + #endif /* if ( portVALIDATED_FOR_SMP != 1 ) || ( configENABLE_MPU == 1 ) || ( configENABLE_TRUSTZONE == 1 ) ) */ + + #ifndef configCORE_ID_REGISTER + #error "configCORE_ID_REGISTER must be defined to the address of the register used to identify the core executing the code." + #endif /* ifndef configCORE_ID_REGISTER */ + + #ifndef configWAKE_SECONDARY_CORES + #error "configWAKE_SECONDARY_CORES must be defined to a function that wakes the secondary cores." + #endif /* ifndef configWAKE_SECONDARY_CORES */ +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ /*-----------------------------------------------------------*/ /** @@ -139,6 +153,11 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); #endif /* configENABLE_PAC */ + +/** + * @brief Configures interrupt priorities. + */ +void vPortConfigureInterruptPriorities( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /** @@ -428,10 +447,26 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /** * @brief Critical section management. */ + +#define portSET_INTERRUPT_MASK() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK( x ) vClearInterruptMask( x ) #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() + +#if ( configNUMBER_OF_CORES == 1 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else /* ( configNUMBER_OF_CORES == 1 ) */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES != 1 ) */ /*-----------------------------------------------------------*/ /** @@ -526,7 +561,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P /* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION * based on whether or not Mainline extension is implemented. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #else #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 @@ -573,6 +608,44 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint32_t ulCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern void vInterruptCore( uint8_t ucCoreID ); + + #define portGET_CORE_ID() ucPortGetCoreID() + + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ulCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + + #define portMAX_CORE_COUNT ( configNUMBER_OF_CORES ) + + #define portYIELD_CORE( xCoreID ) vInterruptCore( xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + uint32_t vConfigurePACBTI( BaseType_t xWriteControlRegister ); + #endif /* ( configENABLE_PAC == 1 || configENABLE_BTI == 1 ) */ +#endif + /* *INDENT-OFF* */ #ifdef __cplusplus } diff --git a/portable/IAR/ATMega323/port.c b/portable/IAR/ATMega323/port.c index 5132fcdaa..980787990 100644 --- a/portable/IAR/ATMega323/port.c +++ b/portable/IAR/ATMega323/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ATMega323/portmacro.h b/portable/IAR/ATMega323/portmacro.h index de4a5e718..e50d9f3d7 100644 --- a/portable/IAR/ATMega323/portmacro.h +++ b/portable/IAR/ATMega323/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/ATMega323/portmacro.s90 b/portable/IAR/ATMega323/portmacro.s90 index e269ed86c..029d0dbb6 100644 --- a/portable/IAR/ATMega323/portmacro.s90 +++ b/portable/IAR/ATMega323/portmacro.s90 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR32_UC3/exception.s82 b/portable/IAR/AVR32_UC3/exception.s82 index 0200f2b22..653600995 100644 --- a/portable/IAR/AVR32_UC3/exception.s82 +++ b/portable/IAR/AVR32_UC3/exception.s82 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c index ab61209d4..dbe121cca 100644 --- a/portable/IAR/AVR32_UC3/port.c +++ b/portable/IAR/AVR32_UC3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/IAR/AVR32_UC3/portmacro.h b/portable/IAR/AVR32_UC3/portmacro.h index 51fdbffda..036833f8f 100644 --- a/portable/IAR/AVR32_UC3/portmacro.h +++ b/portable/IAR/AVR32_UC3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/IAR/AVR32_UC3/read.c b/portable/IAR/AVR32_UC3/read.c index 922a027ec..639d1f8f8 100644 --- a/portable/IAR/AVR32_UC3/read.c +++ b/portable/IAR/AVR32_UC3/read.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/IAR/AVR32_UC3/write.c b/portable/IAR/AVR32_UC3/write.c index 1142aa689..5ac796332 100644 --- a/portable/IAR/AVR32_UC3/write.c +++ b/portable/IAR/AVR32_UC3/write.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT AND BSD-3-Clause diff --git a/portable/IAR/AVR_AVRDx/port.c b/portable/IAR/AVR_AVRDx/port.c index 3b03326ed..07269f0f6 100644 --- a/portable/IAR/AVR_AVRDx/port.c +++ b/portable/IAR/AVR_AVRDx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_AVRDx/porthardware.h b/portable/IAR/AVR_AVRDx/porthardware.h index e56aaffca..f9176f96b 100644 --- a/portable/IAR/AVR_AVRDx/porthardware.h +++ b/portable/IAR/AVR_AVRDx/porthardware.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_AVRDx/portmacro.h b/portable/IAR/AVR_AVRDx/portmacro.h index 743d8487b..829958dc0 100644 --- a/portable/IAR/AVR_AVRDx/portmacro.h +++ b/portable/IAR/AVR_AVRDx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_AVRDx/portmacro.s90 b/portable/IAR/AVR_AVRDx/portmacro.s90 index df21d09c6..c518d3af9 100644 --- a/portable/IAR/AVR_AVRDx/portmacro.s90 +++ b/portable/IAR/AVR_AVRDx/portmacro.s90 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_Mega0/port.c b/portable/IAR/AVR_Mega0/port.c index dfb6dbff0..7d1d2f6e8 100644 --- a/portable/IAR/AVR_Mega0/port.c +++ b/portable/IAR/AVR_Mega0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_Mega0/porthardware.h b/portable/IAR/AVR_Mega0/porthardware.h index a53f3d67c..d834a8e82 100644 --- a/portable/IAR/AVR_Mega0/porthardware.h +++ b/portable/IAR/AVR_Mega0/porthardware.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_Mega0/portmacro.h b/portable/IAR/AVR_Mega0/portmacro.h index 743d8487b..829958dc0 100644 --- a/portable/IAR/AVR_Mega0/portmacro.h +++ b/portable/IAR/AVR_Mega0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AVR_Mega0/portmacro.s90 b/portable/IAR/AVR_Mega0/portmacro.s90 index d04a3f6fe..c2789d48e 100644 --- a/portable/IAR/AVR_Mega0/portmacro.s90 +++ b/portable/IAR/AVR_Mega0/portmacro.s90 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM7S64/ISR_Support.h b/portable/IAR/AtmelSAM7S64/ISR_Support.h index a16353650..273e95141 100644 --- a/portable/IAR/AtmelSAM7S64/ISR_Support.h +++ b/portable/IAR/AtmelSAM7S64/ISR_Support.h @@ -1,5 +1,5 @@ ; /* - * ; * FreeRTOS Kernel V11.3.0 + * ; * FreeRTOS Kernel * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * ; * * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM7S64/port.c b/portable/IAR/AtmelSAM7S64/port.c index 269241509..5f5f7625f 100644 --- a/portable/IAR/AtmelSAM7S64/port.c +++ b/portable/IAR/AtmelSAM7S64/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM7S64/portasm.s79 b/portable/IAR/AtmelSAM7S64/portasm.s79 index 0f31ee63f..4f5f5c083 100644 --- a/portable/IAR/AtmelSAM7S64/portasm.s79 +++ b/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM7S64/portmacro.h b/portable/IAR/AtmelSAM7S64/portmacro.h index 79aa9a96e..75588d526 100644 --- a/portable/IAR/AtmelSAM7S64/portmacro.h +++ b/portable/IAR/AtmelSAM7S64/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM9XE/ISR_Support.h b/portable/IAR/AtmelSAM9XE/ISR_Support.h index ad97bbb4b..ac73c7816 100644 --- a/portable/IAR/AtmelSAM9XE/ISR_Support.h +++ b/portable/IAR/AtmelSAM9XE/ISR_Support.h @@ -1,5 +1,5 @@ ; /* - * ; * FreeRTOS Kernel V11.3.0 + * ; * FreeRTOS Kernel * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * ; * * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM9XE/port.c b/portable/IAR/AtmelSAM9XE/port.c index a3fe22256..f2bd893fc 100644 --- a/portable/IAR/AtmelSAM9XE/port.c +++ b/portable/IAR/AtmelSAM9XE/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM9XE/portasm.s79 b/portable/IAR/AtmelSAM9XE/portasm.s79 index 76801ca01..37241da9c 100644 --- a/portable/IAR/AtmelSAM9XE/portasm.s79 +++ b/portable/IAR/AtmelSAM9XE/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/AtmelSAM9XE/portmacro.h b/portable/IAR/AtmelSAM9XE/portmacro.h index 78963b1b6..68e54c8d3 100644 --- a/portable/IAR/AtmelSAM9XE/portmacro.h +++ b/portable/IAR/AtmelSAM9XE/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/LPC2000/ISR_Support.h b/portable/IAR/LPC2000/ISR_Support.h index a16353650..273e95141 100644 --- a/portable/IAR/LPC2000/ISR_Support.h +++ b/portable/IAR/LPC2000/ISR_Support.h @@ -1,5 +1,5 @@ ; /* - * ; * FreeRTOS Kernel V11.3.0 + * ; * FreeRTOS Kernel * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * ; * * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/LPC2000/port.c b/portable/IAR/LPC2000/port.c index 3fa3f03c2..69d711d3b 100644 --- a/portable/IAR/LPC2000/port.c +++ b/portable/IAR/LPC2000/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/LPC2000/portasm.s79 b/portable/IAR/LPC2000/portasm.s79 index 3ffdb7ad9..2bd1ccc06 100644 --- a/portable/IAR/LPC2000/portasm.s79 +++ b/portable/IAR/LPC2000/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/LPC2000/portmacro.h b/portable/IAR/LPC2000/portmacro.h index 2780d6543..b44d307f3 100644 --- a/portable/IAR/LPC2000/portmacro.h +++ b/portable/IAR/LPC2000/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430/port.c b/portable/IAR/MSP430/port.c index 47893d27b..070f64bf0 100644 --- a/portable/IAR/MSP430/port.c +++ b/portable/IAR/MSP430/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430/portasm.h b/portable/IAR/MSP430/portasm.h index 600aee832..0d8115034 100644 --- a/portable/IAR/MSP430/portasm.h +++ b/portable/IAR/MSP430/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430/portext.s43 b/portable/IAR/MSP430/portext.s43 index 97baf9914..bfe6a190f 100644 --- a/portable/IAR/MSP430/portext.s43 +++ b/portable/IAR/MSP430/portext.s43 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430/portmacro.h b/portable/IAR/MSP430/portmacro.h index 3d60eeadb..f87bfe589 100644 --- a/portable/IAR/MSP430/portmacro.h +++ b/portable/IAR/MSP430/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430X/data_model.h b/portable/IAR/MSP430X/data_model.h index f1a45e645..0d5dcbdd4 100644 --- a/portable/IAR/MSP430X/data_model.h +++ b/portable/IAR/MSP430X/data_model.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c index a8fb23ff3..6c5b21c3a 100644 --- a/portable/IAR/MSP430X/port.c +++ b/portable/IAR/MSP430X/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430X/portext.s43 b/portable/IAR/MSP430X/portext.s43 index 9db96fe69..ccfd084c2 100644 --- a/portable/IAR/MSP430X/portext.s43 +++ b/portable/IAR/MSP430X/portext.s43 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/MSP430X/portmacro.h b/portable/IAR/MSP430X/portmacro.h index 863d021fa..b428f8d40 100644 --- a/portable/IAR/MSP430X/portmacro.h +++ b/portable/IAR/MSP430X/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h index 6dcbd5c4f..364fd5773 100644 --- a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h +++ b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c index 307a1a5ba..0a2864b6d 100644 --- a/portable/IAR/RISC-V/port.c +++ b/portable/IAR/RISC-V/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -98,7 +98,6 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) ); uint64_t ullNextTime = 0ULL; const uint64_t * pullNextTime = &ullNextTime; const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ -UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; volatile uint64_t * pullMachineTimerCompareRegister = NULL; /* Holds the critical nesting value - deliberately non-zero at start up to @@ -169,7 +168,7 @@ static void prvTaskExitError( void ) __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is HART ID. */ - pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( configMTIMECMP_BASE_ADDRESS + ( ulHartId * sizeof( uint64_t ) ) ); do { @@ -187,7 +186,7 @@ static void prvTaskExitError( void ) ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; } -#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ +#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) diff --git a/portable/IAR/RISC-V/portASM.s b/portable/IAR/RISC-V/portASM.s index 1edcce7c3..12a2a6154 100644 --- a/portable/IAR/RISC-V/portASM.s +++ b/portable/IAR/RISC-V/portASM.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RISC-V/portContext.h b/portable/IAR/RISC-V/portContext.h index c0e72421e..7b3244e7b 100644 --- a/portable/IAR/RISC-V/portContext.h +++ b/portable/IAR/RISC-V/portContext.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h index 335b53856..c7237b363 100644 --- a/portable/IAR/RISC-V/portmacro.h +++ b/portable/IAR/RISC-V/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RL78/port.c b/portable/IAR/RL78/port.c index 20359780a..656efeb2d 100644 --- a/portable/IAR/RL78/port.c +++ b/portable/IAR/RL78/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RL78/portasm.s b/portable/IAR/RL78/portasm.s index 238b07490..7067cb1e4 100644 --- a/portable/IAR/RL78/portasm.s +++ b/portable/IAR/RL78/portasm.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h index dab63add8..36697a620 100644 --- a/portable/IAR/RL78/portmacro.h +++ b/portable/IAR/RL78/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX100/port.c b/portable/IAR/RX100/port.c index 824122655..b63b23b48 100644 --- a/portable/IAR/RX100/port.c +++ b/portable/IAR/RX100/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX100/port_asm.s b/portable/IAR/RX100/port_asm.s index 79b82d36b..5eb90f7d1 100644 --- a/portable/IAR/RX100/port_asm.s +++ b/portable/IAR/RX100/port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX100/portmacro.h b/portable/IAR/RX100/portmacro.h index 766545537..ab5eae69f 100644 --- a/portable/IAR/RX100/portmacro.h +++ b/portable/IAR/RX100/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX600/port.c b/portable/IAR/RX600/port.c index a577c6222..73ff96cff 100644 --- a/portable/IAR/RX600/port.c +++ b/portable/IAR/RX600/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX600/port_asm.s b/portable/IAR/RX600/port_asm.s index 8f3621587..29698534d 100644 --- a/portable/IAR/RX600/port_asm.s +++ b/portable/IAR/RX600/port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX600/portmacro.h b/portable/IAR/RX600/portmacro.h index a08e5df5e..87faf8639 100644 --- a/portable/IAR/RX600/portmacro.h +++ b/portable/IAR/RX600/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX700v3_DPFPU/port.c b/portable/IAR/RX700v3_DPFPU/port.c index 3eb302730..d05835975 100644 --- a/portable/IAR/RX700v3_DPFPU/port.c +++ b/portable/IAR/RX700v3_DPFPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RX700v3_DPFPU/portmacro.h b/portable/IAR/RX700v3_DPFPU/portmacro.h index a555977ef..e24cbfe53 100644 --- a/portable/IAR/RX700v3_DPFPU/portmacro.h +++ b/portable/IAR/RX700v3_DPFPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RXv2/port.c b/portable/IAR/RXv2/port.c index 0afb4eb9b..af21ae57a 100644 --- a/portable/IAR/RXv2/port.c +++ b/portable/IAR/RXv2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RXv2/port_asm.s b/portable/IAR/RXv2/port_asm.s index b24917384..122f8a4f4 100644 --- a/portable/IAR/RXv2/port_asm.s +++ b/portable/IAR/RXv2/port_asm.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/RXv2/portmacro.h b/portable/IAR/RXv2/portmacro.h index 26e95d9a9..792beb9df 100644 --- a/portable/IAR/RXv2/portmacro.h +++ b/portable/IAR/RXv2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR71x/ISR_Support.h b/portable/IAR/STR71x/ISR_Support.h index a16353650..273e95141 100644 --- a/portable/IAR/STR71x/ISR_Support.h +++ b/portable/IAR/STR71x/ISR_Support.h @@ -1,5 +1,5 @@ ; /* - * ; * FreeRTOS Kernel V11.3.0 + * ; * FreeRTOS Kernel * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * ; * * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR71x/port.c b/portable/IAR/STR71x/port.c index 679136efb..8f0e78c0d 100644 --- a/portable/IAR/STR71x/port.c +++ b/portable/IAR/STR71x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR71x/portasm.s79 b/portable/IAR/STR71x/portasm.s79 index ffbb59c40..87166f691 100644 --- a/portable/IAR/STR71x/portasm.s79 +++ b/portable/IAR/STR71x/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR71x/portmacro.h b/portable/IAR/STR71x/portmacro.h index 5cfd0f7a6..e05c380ab 100644 --- a/portable/IAR/STR71x/portmacro.h +++ b/portable/IAR/STR71x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR75x/ISR_Support.h b/portable/IAR/STR75x/ISR_Support.h index a16353650..273e95141 100644 --- a/portable/IAR/STR75x/ISR_Support.h +++ b/portable/IAR/STR75x/ISR_Support.h @@ -1,5 +1,5 @@ ; /* - * ; * FreeRTOS Kernel V11.3.0 + * ; * FreeRTOS Kernel * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * ; * * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR75x/port.c b/portable/IAR/STR75x/port.c index 7e464dd89..b4ec381a5 100644 --- a/portable/IAR/STR75x/port.c +++ b/portable/IAR/STR75x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR75x/portasm.s79 b/portable/IAR/STR75x/portasm.s79 index 5694d26bf..ad2aa1b5e 100644 --- a/portable/IAR/STR75x/portasm.s79 +++ b/portable/IAR/STR75x/portasm.s79 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR75x/portmacro.h b/portable/IAR/STR75x/portmacro.h index 10105f422..1d5cdabbe 100644 --- a/portable/IAR/STR75x/portmacro.h +++ b/portable/IAR/STR75x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR91x/ISR_Support.h b/portable/IAR/STR91x/ISR_Support.h index ccfd5cb21..2e6973757 100644 --- a/portable/IAR/STR91x/ISR_Support.h +++ b/portable/IAR/STR91x/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR91x/port.c b/portable/IAR/STR91x/port.c index 90420447f..f706c946e 100644 --- a/portable/IAR/STR91x/port.c +++ b/portable/IAR/STR91x/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR91x/portasm.s79 b/portable/IAR/STR91x/portasm.s79 index 83c28fb21..9b91475c7 100644 --- a/portable/IAR/STR91x/portasm.s79 +++ b/portable/IAR/STR91x/portasm.s79 @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/STR91x/portmacro.h b/portable/IAR/STR91x/portmacro.h index 856464e11..fde5b6dcb 100644 --- a/portable/IAR/STR91x/portmacro.h +++ b/portable/IAR/STR91x/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/V850ES/ISR_Support.h b/portable/IAR/V850ES/ISR_Support.h index 1b8968c62..b99126d0f 100644 --- a/portable/IAR/V850ES/ISR_Support.h +++ b/portable/IAR/V850ES/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/V850ES/port.c b/portable/IAR/V850ES/port.c index ea66bf214..d1d9d6a7d 100644 --- a/portable/IAR/V850ES/port.c +++ b/portable/IAR/V850ES/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/IAR/V850ES/portasm.s85 b/portable/IAR/V850ES/portasm.s85 index e166cc146..b01753667 100644 --- a/portable/IAR/V850ES/portasm.s85 +++ b/portable/IAR/V850ES/portasm.s85 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/V850ES/portasm_Fx3.s85 b/portable/IAR/V850ES/portasm_Fx3.s85 index f915b2861..12262b3af 100644 --- a/portable/IAR/V850ES/portasm_Fx3.s85 +++ b/portable/IAR/V850ES/portasm_Fx3.s85 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/V850ES/portasm_Hx2.s85 b/portable/IAR/V850ES/portasm_Hx2.s85 index 014e1c1bd..03c2e38ae 100644 --- a/portable/IAR/V850ES/portasm_Hx2.s85 +++ b/portable/IAR/V850ES/portasm_Hx2.s85 @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/IAR/V850ES/portmacro.h b/portable/IAR/V850ES/portmacro.h index d55f4dfb9..0f066a0fc 100644 --- a/portable/IAR/V850ES/portmacro.h +++ b/portable/IAR/V850ES/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c index 29032a942..bb8451581 100644 --- a/portable/MPLAB/PIC18F/port.c +++ b/portable/MPLAB/PIC18F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC18F/portmacro.h b/portable/MPLAB/PIC18F/portmacro.h index 92a2ab2ef..a0bfb44b5 100644 --- a/portable/MPLAB/PIC18F/portmacro.h +++ b/portable/MPLAB/PIC18F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c index 0dbb93495..f309128e5 100644 --- a/portable/MPLAB/PIC24_dsPIC/port.c +++ b/portable/MPLAB/PIC24_dsPIC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S index 3bc11dec0..e2a7d6267 100644 --- a/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S +++ b/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S index 4b4e76e43..ec1f070a4 100644 --- a/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S +++ b/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC24_dsPIC/portmacro.h b/portable/MPLAB/PIC24_dsPIC/portmacro.h index cdb441773..fbac471d5 100644 --- a/portable/MPLAB/PIC24_dsPIC/portmacro.h +++ b/portable/MPLAB/PIC24_dsPIC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h index 1bdee17ce..ce7c4ad63 100644 --- a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h +++ b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c index 2d8bd3e93..1f0d9cc03 100644 --- a/portable/MPLAB/PIC32MEC14xx/port.c +++ b/portable/MPLAB/PIC32MEC14xx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MEC14xx/port_asm.S b/portable/MPLAB/PIC32MEC14xx/port_asm.S index 4dc181e5e..b2c37f2db 100644 --- a/portable/MPLAB/PIC32MEC14xx/port_asm.S +++ b/portable/MPLAB/PIC32MEC14xx/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h index 9fc689cab..f431ae324 100644 --- a/portable/MPLAB/PIC32MEC14xx/portmacro.h +++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MX/ISR_Support.h b/portable/MPLAB/PIC32MX/ISR_Support.h index 6cdfa4380..0bff08fe1 100644 --- a/portable/MPLAB/PIC32MX/ISR_Support.h +++ b/portable/MPLAB/PIC32MX/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c index 823c77f54..582a600a3 100644 --- a/portable/MPLAB/PIC32MX/port.c +++ b/portable/MPLAB/PIC32MX/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MX/port_asm.S b/portable/MPLAB/PIC32MX/port_asm.S index 0b4853e2d..4e00324eb 100644 --- a/portable/MPLAB/PIC32MX/port_asm.S +++ b/portable/MPLAB/PIC32MX/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h index 99479b15a..7868dcb8c 100644 --- a/portable/MPLAB/PIC32MX/portmacro.h +++ b/portable/MPLAB/PIC32MX/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h index ecec01e3c..292877f42 100644 --- a/portable/MPLAB/PIC32MZ/ISR_Support.h +++ b/portable/MPLAB/PIC32MZ/ISR_Support.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c index f629066f4..4af1fb832 100644 --- a/portable/MPLAB/PIC32MZ/port.c +++ b/portable/MPLAB/PIC32MZ/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MZ/port_asm.S b/portable/MPLAB/PIC32MZ/port_asm.S index c4c545906..78cb14165 100644 --- a/portable/MPLAB/PIC32MZ/port_asm.S +++ b/portable/MPLAB/PIC32MZ/port_asm.S @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h index 951823803..8b0497086 100644 --- a/portable/MPLAB/PIC32MZ/portmacro.h +++ b/portable/MPLAB/PIC32MZ/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c index f37ef1bbe..40458682b 100644 --- a/portable/MSVC-MingW/port.c +++ b/portable/MSVC-MingW/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT @@ -408,7 +408,7 @@ static void prvProcessSimulatedInterrupts( void ) /* Create a pending tick to ensure the first task is started as soon as * this thread pends. */ - ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK ); + ulPendingInterrupts |= ( 1UL << portINTERRUPT_TICK ); SetEvent( pvInterruptEvent ); while( xPortRunning == pdTRUE ) @@ -447,7 +447,7 @@ static void prvProcessSimulatedInterrupts( void ) if( ulIsrHandler[ i ]() != pdFALSE ) { /* A bit mask is used purely to help debugging. */ - ulSwitchRequired |= ( 1 << i ); + ulSwitchRequired |= ( 1UL << i ); } } @@ -580,7 +580,7 @@ void vPortCloseRunningThread( void * pvTaskToDelete, if( pvInterruptEventMutex != NULL ) { WaitForSingleObject( pvInterruptEventMutex, INFINITE ); - ulPendingInterrupts |= ( 1 << portINTERRUPT_YIELD ); + ulPendingInterrupts |= ( 1UL << portINTERRUPT_YIELD ); ReleaseMutex( pvInterruptEventMutex ); } @@ -604,7 +604,7 @@ void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ) if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) ) { WaitForSingleObject( pvInterruptEventMutex, INFINITE ); - ulPendingInterrupts |= ( 1 << ulInterruptNumber ); + ulPendingInterrupts |= ( 1UL << ulInterruptNumber ); /* The simulated interrupt is now held pending, but don't actually * process it yet if this call is within a critical section. It is @@ -645,7 +645,7 @@ void vPortGenerateSimulatedInterruptFromWindowsThread( uint32_t ulInterruptNumbe /* Pending a user defined interrupt to be handled in simulated interrupt * handler thread. */ - ulPendingInterrupts |= ( 1 << ulInterruptNumber ); + ulPendingInterrupts |= ( 1UL << ulInterruptNumber ); /* The interrupt is now pending - notify the simulated interrupt * handler thread. Must be outside of a critical section to get here so diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h index 532f2456b..37bfb2586 100644 --- a/portable/MSVC-MingW/portmacro.h +++ b/portable/MSVC-MingW/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c index 5829ff671..f697c907c 100644 --- a/portable/MemMang/heap_1.c +++ b/portable/MemMang/heap_1.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c index 005dc0764..fa6ea9d9b 100644 --- a/portable/MemMang/heap_2.c +++ b/portable/MemMang/heap_2.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MemMang/heap_3.c b/portable/MemMang/heap_3.c index 35dceffef..5094390b5 100644 --- a/portable/MemMang/heap_3.c +++ b/portable/MemMang/heap_3.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c index a2b93aff1..50af15dfb 100644 --- a/portable/MemMang/heap_4.c +++ b/portable/MemMang/heap_4.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c index c6680bc74..bf321304f 100644 --- a/portable/MemMang/heap_5.c +++ b/portable/MemMang/heap_5.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index e1811bc2f..a167f8588 100644 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h index 7abc06d2c..d6cd752e4 100644 --- a/portable/MikroC/ARM_CM4F/portmacro.h +++ b/portable/MikroC/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c index 61ba56f63..443104885 100644 --- a/portable/Paradigm/Tern_EE/large_untested/port.c +++ b/portable/Paradigm/Tern_EE/large_untested/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h index d7fc0df84..cf9e711c8 100644 --- a/portable/Paradigm/Tern_EE/large_untested/portasm.h +++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/portable/Paradigm/Tern_EE/large_untested/portmacro.h index 951813945..1ea0c3176 100644 --- a/portable/Paradigm/Tern_EE/large_untested/portmacro.h +++ b/portable/Paradigm/Tern_EE/large_untested/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c index 98aa771db..75273f225 100644 --- a/portable/Paradigm/Tern_EE/small/port.c +++ b/portable/Paradigm/Tern_EE/small/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Paradigm/Tern_EE/small/portasm.h b/portable/Paradigm/Tern_EE/small/portasm.h index 0edb0c4cc..88ef3ba99 100644 --- a/portable/Paradigm/Tern_EE/small/portasm.h +++ b/portable/Paradigm/Tern_EE/small/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Paradigm/Tern_EE/small/portmacro.h b/portable/Paradigm/Tern_EE/small/portmacro.h index 5ecc0cde7..0ab083838 100644 --- a/portable/Paradigm/Tern_EE/small/portmacro.h +++ b/portable/Paradigm/Tern_EE/small/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM7_LPC21xx/port.c b/portable/RVDS/ARM7_LPC21xx/port.c index 9e86e7a29..5476af8c9 100644 --- a/portable/RVDS/ARM7_LPC21xx/port.c +++ b/portable/RVDS/ARM7_LPC21xx/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM7_LPC21xx/portASM.s b/portable/RVDS/ARM7_LPC21xx/portASM.s index f1cd6dcdc..c47a9a641 100644 --- a/portable/RVDS/ARM7_LPC21xx/portASM.s +++ b/portable/RVDS/ARM7_LPC21xx/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.h b/portable/RVDS/ARM7_LPC21xx/portmacro.h index 3404f67ab..5535dcfef 100644 --- a/portable/RVDS/ARM7_LPC21xx/portmacro.h +++ b/portable/RVDS/ARM7_LPC21xx/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/portable/RVDS/ARM7_LPC21xx/portmacro.inc index 28da6d414..ef84d1adf 100644 --- a/portable/RVDS/ARM7_LPC21xx/portmacro.inc +++ b/portable/RVDS/ARM7_LPC21xx/portmacro.inc @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c index 47ff49bcf..7ef38f399 100644 --- a/portable/RVDS/ARM_CA9/port.c +++ b/portable/RVDS/ARM_CA9/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CA9/portASM.s b/portable/RVDS/ARM_CA9/portASM.s index 296aa4e6e..771b140da 100644 --- a/portable/RVDS/ARM_CA9/portASM.s +++ b/portable/RVDS/ARM_CA9/portASM.s @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CA9/portmacro.h b/portable/RVDS/ARM_CA9/portmacro.h index 2710c282a..2218a6379 100644 --- a/portable/RVDS/ARM_CA9/portmacro.h +++ b/portable/RVDS/ARM_CA9/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CA9/portmacro.inc b/portable/RVDS/ARM_CA9/portmacro.inc index a34c125db..68a73945f 100644 --- a/portable/RVDS/ARM_CA9/portmacro.inc +++ b/portable/RVDS/ARM_CA9/portmacro.inc @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c index e6e2fb639..ececb715a 100644 --- a/portable/RVDS/ARM_CM0/port.c +++ b/portable/RVDS/ARM_CM0/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM0/portmacro.h b/portable/RVDS/ARM_CM0/portmacro.h index 920f34be0..785138722 100644 --- a/portable/RVDS/ARM_CM0/portmacro.h +++ b/portable/RVDS/ARM_CM0/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index d0136b5c4..725127193 100644 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h index 591a79292..0436525fd 100644 --- a/portable/RVDS/ARM_CM3/portmacro.h +++ b/portable/RVDS/ARM_CM3/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c index 498ec047b..8d21daffb 100644 --- a/portable/RVDS/ARM_CM4F/port.c +++ b/portable/RVDS/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h index 02f84f618..063b148f4 100644 --- a/portable/RVDS/ARM_CM4F/portmacro.h +++ b/portable/RVDS/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c index d6c51002d..950788e09 100644 --- a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c +++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index 7d83d4c7a..450b86211 100644 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2025 Arm Limited and/or its affiliates * diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h index 8d73af2d8..8e682ba74 100644 --- a/portable/RVDS/ARM_CM4_MPU/portmacro.h +++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c index f3626fe62..33fa80266 100644 --- a/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h index 3f44c3904..b36b427d9 100644 --- a/portable/RVDS/ARM_CM7/r0p1/portmacro.h +++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c index 8f962bb1d..a22da66cf 100644 --- a/portable/Renesas/RX100/port.c +++ b/portable/Renesas/RX100/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX100/port_asm.src b/portable/Renesas/RX100/port_asm.src index 69042d22e..afe0aba5b 100644 --- a/portable/Renesas/RX100/port_asm.src +++ b/portable/Renesas/RX100/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h index fcb6ecef6..5ae7d05aa 100644 --- a/portable/Renesas/RX100/portmacro.h +++ b/portable/Renesas/RX100/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c index 5eddd5117..fe05cf750 100644 --- a/portable/Renesas/RX200/port.c +++ b/portable/Renesas/RX200/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX200/port_asm.src b/portable/Renesas/RX200/port_asm.src index 69042d22e..afe0aba5b 100644 --- a/portable/Renesas/RX200/port_asm.src +++ b/portable/Renesas/RX200/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h index a17387c6d..bf11b2e93 100644 --- a/portable/Renesas/RX200/portmacro.h +++ b/portable/Renesas/RX200/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c index 481b4a243..95431adce 100644 --- a/portable/Renesas/RX600/port.c +++ b/portable/Renesas/RX600/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX600/port_asm.src b/portable/Renesas/RX600/port_asm.src index 69042d22e..afe0aba5b 100644 --- a/portable/Renesas/RX600/port_asm.src +++ b/portable/Renesas/RX600/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h index 6a7279129..53f45dec7 100644 --- a/portable/Renesas/RX600/portmacro.h +++ b/portable/Renesas/RX600/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c index b931d796a..bae8fd623 100644 --- a/portable/Renesas/RX600v2/port.c +++ b/portable/Renesas/RX600v2/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX600v2/port_asm.src b/portable/Renesas/RX600v2/port_asm.src index 9d2415969..8d5200b6c 100644 --- a/portable/Renesas/RX600v2/port_asm.src +++ b/portable/Renesas/RX600v2/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h index bbfa1ebae..0442b05a1 100644 --- a/portable/Renesas/RX600v2/portmacro.h +++ b/portable/Renesas/RX600v2/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX700v3_DPFPU/port.c b/portable/Renesas/RX700v3_DPFPU/port.c index 6300e62cc..6fec50425 100644 --- a/portable/Renesas/RX700v3_DPFPU/port.c +++ b/portable/Renesas/RX700v3_DPFPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX700v3_DPFPU/port_asm.src b/portable/Renesas/RX700v3_DPFPU/port_asm.src index 9d2415969..8d5200b6c 100644 --- a/portable/Renesas/RX700v3_DPFPU/port_asm.src +++ b/portable/Renesas/RX700v3_DPFPU/port_asm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h index 7e29f141e..e0c6b1df1 100644 --- a/portable/Renesas/RX700v3_DPFPU/portmacro.h +++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/SH2A_FPU/ISR_Support.inc b/portable/Renesas/SH2A_FPU/ISR_Support.inc index 194f8b27e..33ad2de68 100644 --- a/portable/Renesas/SH2A_FPU/ISR_Support.inc +++ b/portable/Renesas/SH2A_FPU/ISR_Support.inc @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/SH2A_FPU/port.c b/portable/Renesas/SH2A_FPU/port.c index 48656712d..c14a0a851 100644 --- a/portable/Renesas/SH2A_FPU/port.c +++ b/portable/Renesas/SH2A_FPU/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/SH2A_FPU/portasm.src b/portable/Renesas/SH2A_FPU/portasm.src index 7ee325138..4cf7225aa 100644 --- a/portable/Renesas/SH2A_FPU/portasm.src +++ b/portable/Renesas/SH2A_FPU/portasm.src @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Renesas/SH2A_FPU/portmacro.h b/portable/Renesas/SH2A_FPU/portmacro.h index 7386885cc..2229fd3f6 100644 --- a/portable/Renesas/SH2A_FPU/portmacro.h +++ b/portable/Renesas/SH2A_FPU/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Rowley/MSP430F449/port.c b/portable/Rowley/MSP430F449/port.c index 00f878546..392dadbdd 100644 --- a/portable/Rowley/MSP430F449/port.c +++ b/portable/Rowley/MSP430F449/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Rowley/MSP430F449/portasm.h b/portable/Rowley/MSP430F449/portasm.h index 0c0c5ff26..18361cce3 100644 --- a/portable/Rowley/MSP430F449/portasm.h +++ b/portable/Rowley/MSP430F449/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Rowley/MSP430F449/portext.asm b/portable/Rowley/MSP430F449/portext.asm index f55d04adf..80cdcef81 100644 --- a/portable/Rowley/MSP430F449/portext.asm +++ b/portable/Rowley/MSP430F449/portext.asm @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Rowley/MSP430F449/portmacro.h b/portable/Rowley/MSP430F449/portmacro.h index 81a8c0aa5..38304fb03 100644 --- a/portable/Rowley/MSP430F449/portmacro.h +++ b/portable/Rowley/MSP430F449/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c index 1357dcb7c..418a50430 100644 --- a/portable/SDCC/Cygnal/port.c +++ b/portable/SDCC/Cygnal/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/SDCC/Cygnal/portmacro.h b/portable/SDCC/Cygnal/portmacro.h index e4539d17c..fe0340757 100644 --- a/portable/SDCC/Cygnal/portmacro.h +++ b/portable/SDCC/Cygnal/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Softune/MB91460/__STD_LIB_sbrk.c b/portable/Softune/MB91460/__STD_LIB_sbrk.c index f9c1dd132..4f986e804 100644 --- a/portable/Softune/MB91460/__STD_LIB_sbrk.c +++ b/portable/Softune/MB91460/__STD_LIB_sbrk.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c index cf1c1a9f1..4b87ba402 100644 --- a/portable/Softune/MB91460/port.c +++ b/portable/Softune/MB91460/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Softune/MB91460/portmacro.h b/portable/Softune/MB91460/portmacro.h index 6dc3d4b7b..182a3057e 100644 --- a/portable/Softune/MB91460/portmacro.h +++ b/portable/Softune/MB91460/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Softune/MB96340/__STD_LIB_sbrk.c b/portable/Softune/MB96340/__STD_LIB_sbrk.c index f9c1dd132..4f986e804 100644 --- a/portable/Softune/MB96340/__STD_LIB_sbrk.c +++ b/portable/Softune/MB96340/__STD_LIB_sbrk.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c index 5836112a9..ec0d977bc 100644 --- a/portable/Softune/MB96340/port.c +++ b/portable/Softune/MB96340/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Softune/MB96340/portmacro.h b/portable/Softune/MB96340/portmacro.h index 69b192c80..ef4a1eb5a 100644 --- a/portable/Softune/MB96340/portmacro.h +++ b/portable/Softune/MB96340/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c index 9eb56881e..43a892f1e 100644 --- a/portable/Tasking/ARM_CM4F/port.c +++ b/portable/Tasking/ARM_CM4F/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/Tasking/ARM_CM4F/port_asm.asm b/portable/Tasking/ARM_CM4F/port_asm.asm index 22f5c88e8..8b6784e70 100644 --- a/portable/Tasking/ARM_CM4F/port_asm.asm +++ b/portable/Tasking/ARM_CM4F/port_asm.asm @@ -1,5 +1,5 @@ ;/* -; * FreeRTOS Kernel V11.3.0 +; * FreeRTOS Kernel ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT diff --git a/portable/Tasking/ARM_CM4F/portmacro.h b/portable/Tasking/ARM_CM4F/portmacro.h index d694bfe37..3d16cd6da 100644 --- a/portable/Tasking/ARM_CM4F/portmacro.h +++ b/portable/Tasking/ARM_CM4F/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c index 1b8b9730c..3b5b085a2 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h index 1f1381588..35a5abafb 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h +++ b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s b/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s index 635c67966..14174a376 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s +++ b/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c index 7c8ef2f08..7d74f319e 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c index e205ff442..7837f8f73 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/port.c +++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h index 49567dda1..e5004146b 100644 --- a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h +++ b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c index 1b8b9730c..3b5b085a2 100644 --- a/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c +++ b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h index 1f1381588..35a5abafb 100644 --- a/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h +++ b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_v1/arc_support.s b/portable/ThirdParty/GCC/ARC_v1/arc_support.s index 64208676a..df2ec408c 100644 --- a/portable/ThirdParty/GCC/ARC_v1/arc_support.s +++ b/portable/ThirdParty/GCC/ARC_v1/arc_support.s @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_v1/port.c b/portable/ThirdParty/GCC/ARC_v1/port.c index a4c0a4e6e..39e8b771b 100644 --- a/portable/ThirdParty/GCC/ARC_v1/port.c +++ b/portable/ThirdParty/GCC/ARC_v1/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ARC_v1/portmacro.h b/portable/ThirdParty/GCC/ARC_v1/portmacro.h index af707e47c..cc67ad613 100644 --- a/portable/ThirdParty/GCC/ARC_v1/portmacro.h +++ b/portable/ThirdParty/GCC/ARC_v1/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c index f069b8946..168bcdd94 100644 --- a/portable/ThirdParty/GCC/ATmega/port.c +++ b/portable/ThirdParty/GCC/ATmega/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h index 0c2ba820f..0cc583479 100644 --- a/portable/ThirdParty/GCC/ATmega/portmacro.h +++ b/portable/ThirdParty/GCC/ATmega/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c index 677675236..a1b1ca8c7 100644 --- a/portable/ThirdParty/GCC/Posix/port.c +++ b/portable/ThirdParty/GCC/Posix/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Cambridge Consultants Ltd. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h index d3a5ea446..e117749fe 100644 --- a/portable/ThirdParty/GCC/Posix/portmacro.h +++ b/portable/ThirdParty/GCC/Posix/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright 2020 Cambridge Consultants Ltd. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c index 0f8070d51..55fd7bbfc 100644 --- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c +++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h index 6de521596..533db04f1 100644 --- a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h +++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h index 829edf0e4..71ca3277e 100644 --- a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h +++ b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h index 8ebcb8c4b..d8173716e 100644 --- a/portable/ThirdParty/GCC/RP2040/include/portmacro.h +++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * diff --git a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h index d83f4c9d2..b2159a94e 100644 --- a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h +++ b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c index 262d19afa..66d633720 100644 --- a/portable/ThirdParty/GCC/RP2040/port.c +++ b/portable/ThirdParty/GCC/RP2040/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h index 5a81c0e75..57f7b0156 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h @@ -7,7 +7,7 @@ */ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h index 42c7368aa..2f3fe55e0 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h @@ -8,7 +8,7 @@ */ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c index b76060d71..a89868baa 100644 --- a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c @@ -8,7 +8,7 @@ */ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c index f2ec3ad9f..53c2dbcc7 100644 --- a/portable/WizC/PIC18/Drivers/Tick/Tick.c +++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/portable/WizC/PIC18/Drivers/Tick/isrTick.c index b6f2f8b7b..d68f8431f 100644 --- a/portable/WizC/PIC18/Drivers/Tick/isrTick.c +++ b/portable/WizC/PIC18/Drivers/Tick/isrTick.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/WizC/PIC18/addFreeRTOS.h b/portable/WizC/PIC18/addFreeRTOS.h index d465f75a2..386ae9f7e 100644 --- a/portable/WizC/PIC18/addFreeRTOS.h +++ b/portable/WizC/PIC18/addFreeRTOS.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/WizC/PIC18/port.c b/portable/WizC/PIC18/port.c index ca6f4f7c8..6941ece4f 100644 --- a/portable/WizC/PIC18/port.c +++ b/portable/WizC/PIC18/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h index 22e32df65..abeb955d0 100644 --- a/portable/WizC/PIC18/portmacro.h +++ b/portable/WizC/PIC18/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c index 5d6873ad2..4b900b6a8 100644 --- a/portable/oWatcom/16BitDOS/Flsh186/port.c +++ b/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h index 58ca57ef2..efa43611b 100644 --- a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h +++ b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c index 32871c6a9..bbee5ec68 100644 --- a/portable/oWatcom/16BitDOS/PC/port.c +++ b/portable/oWatcom/16BitDOS/PC/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/oWatcom/16BitDOS/PC/portmacro.h b/portable/oWatcom/16BitDOS/PC/portmacro.h index cc8d98a83..99b29dbc7 100644 --- a/portable/oWatcom/16BitDOS/PC/portmacro.h +++ b/portable/oWatcom/16BitDOS/PC/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h index be1b079d0..b9cb0e697 100644 --- a/portable/oWatcom/16BitDOS/common/portasm.h +++ b/portable/oWatcom/16BitDOS/common/portasm.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/oWatcom/16BitDOS/common/portcomn.c b/portable/oWatcom/16BitDOS/common/portcomn.c index 3dff17bba..d05b1fd1f 100644 --- a/portable/oWatcom/16BitDOS/common/portcomn.c +++ b/portable/oWatcom/16BitDOS/common/portcomn.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/portable/template/port.c b/portable/template/port.c index 570af8464..7cac1c991 100644 --- a/portable/template/port.c +++ b/portable/template/port.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * license and copyright intentionally withheld to promote copying into user code. */ diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h index 10b9a05cb..a426f0003 100644 --- a/portable/template/portmacro.h +++ b/portable/template/portmacro.h @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * license and copyright intentionally withheld to promote copying into user code. */ diff --git a/queue.c b/queue.c index 905dbd942..25613bf3f 100644 --- a/queue.c +++ b/queue.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/stream_buffer.c b/stream_buffer.c index 079347229..287bd0736 100644 --- a/stream_buffer.c +++ b/stream_buffer.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT diff --git a/tasks.c b/tasks.c index 2b7d31198..c596c475f 100644 --- a/tasks.c +++ b/tasks.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * Copyright 2026 Arm Limited and/or its affiliates * diff --git a/timers.c b/timers.c index c3e26216d..1bc40bc46 100644 --- a/timers.c +++ b/timers.c @@ -1,5 +1,5 @@ /* - * FreeRTOS Kernel V11.3.0 + * FreeRTOS Kernel * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT