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@ -76,15 +76,15 @@
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||||||
* Macros to mark the start and end of a critical code region.
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* Macros to mark the start and end of a critical code region.
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*/
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*/
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#define event_groupsENTER_CRITICAL( pxEventBits ) taskDATA_GROUP_ENTER_CRITICAL( &pxEventBits->xTaskSpinlock, &pxEventBits->xISRSpinlock )
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#define event_groupsENTER_CRITICAL( pxEventBits ) taskDATA_GROUP_ENTER_CRITICAL( pxEventBits )
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#define event_groupsENTER_CRITICAL_FROM_ISR( pxEventBits, puxSavedInterruptStatus ) taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( &pxEventBits->xISRSpinlock, puxSavedInterruptStatus )
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#define event_groupsENTER_CRITICAL_FROM_ISR( pxEventBits ) taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( pxEventBits )
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#define event_groupsEXIT_CRITICAL( pxEventBits ) taskDATA_GROUP_EXIT_CRITICAL( &pxEventBits->xTaskSpinlock, &pxEventBits->xISRSpinlock )
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#define event_groupsEXIT_CRITICAL( pxEventBits ) taskDATA_GROUP_EXIT_CRITICAL( pxEventBits )
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#define event_groupsEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxEventBits ) taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, &pxEventBits->xISRSpinlock )
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#define event_groupsEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxEventBits ) taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxEventBits )
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#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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#define event_groupsENTER_CRITICAL( pxEventBits ) taskENTER_CRITICAL();
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#define event_groupsENTER_CRITICAL( pxEventBits ) taskENTER_CRITICAL();
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#define event_groupsENTER_CRITICAL_FROM_ISR( pxEventBits, puxSavedInterruptStatus ) do { *( puxSavedInterruptStatus ) = taskENTER_CRITICAL_FROM_ISR(); } while( 0 )
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#define event_groupsENTER_CRITICAL_FROM_ISR( pxEventBits ) taskENTER_CRITICAL_FROM_ISR();
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#define event_groupsEXIT_CRITICAL( pxEventBits ) taskEXIT_CRITICAL();
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#define event_groupsEXIT_CRITICAL( pxEventBits ) taskEXIT_CRITICAL();
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#define event_groupsEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxEventBits ) taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
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#define event_groupsEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxEventBits ) taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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/*
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/*
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@ -603,7 +603,7 @@
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* MISRA Ref 4.7.1 [Return value shall be checked] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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/* coverity[misra_c_2012_directive_4_7_violation] */
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event_groupsENTER_CRITICAL_FROM_ISR( pxEventBits, &uxSavedInterruptStatus );
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uxSavedInterruptStatus = event_groupsENTER_CRITICAL_FROM_ISR( pxEventBits );
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{
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{
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uxReturn = pxEventBits->uxEventBits;
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uxReturn = pxEventBits->uxEventBits;
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}
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}
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128
include/task.h
128
include/task.h
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@ -292,27 +292,27 @@ typedef enum
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* \ingroup GranularLocks
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* \ingroup GranularLocks
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*/
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*/
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#define taskDATA_GROUP_ENTER_CRITICAL( pxTaskSpinlock, pxISRSpinlock ) \
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#define taskDATA_GROUP_ENTER_CRITICAL( pxDataGroup ) \
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do { \
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do { \
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/* Disable preemption to avoid task state changes during the critical section. */ \
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/* Disable preemption to avoid task state changes during the critical section. */ \
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vTaskPreemptionDisable( NULL ); \
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vTaskPreemptionDisable( NULL ); \
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{ \
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{ \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) { \
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if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) { \
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/* Task spinlock is always taken first */ \
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/* Task spinlock is always taken first */ \
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portGET_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) pxTaskSpinlock ); \
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portGET_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) &( ( pxDataGroup )->xTaskSpinlock ) ); \
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/* Disable interrupts */ \
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/* Disable interrupts */ \
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portDISABLE_INTERRUPTS(); \
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portDISABLE_INTERRUPTS(); \
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/* Take the ISR spinlock next */ \
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/* Take the ISR spinlock next */ \
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portGET_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) pxISRSpinlock ); \
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portGET_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) &( ( pxDataGroup )->xISRSpinlock ) ); \
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} \
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} \
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else \
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else \
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{ \
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{ \
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mtCOVERAGE_TEST_MARKER(); \
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mtCOVERAGE_TEST_MARKER(); \
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} \
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} \
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/* Increment the critical nesting count */ \
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/* Increment the critical nesting count */ \
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portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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} \
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} \
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} while( 0 )
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} while( 0 )
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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|
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@ -325,15 +325,17 @@ typedef enum
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* \ingroup GranularLocks
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* \ingroup GranularLocks
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*/
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*/
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#define taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( pxISRSpinlock, puxSavedInterruptStatus ) \
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#define taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( pxDataGroup ) \
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do { \
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( { \
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*( puxSavedInterruptStatus ) = portSET_INTERRUPT_MASK_FROM_ISR(); \
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UBaseType_t uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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/* Take the ISR spinlock */ \
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/* Take the ISR spinlock */ \
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portGET_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) pxISRSpinlock ); \
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portGET_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) &( ( pxDataGroup )->xISRSpinlock ) ); \
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/* Increment the critical nesting count */ \
|
/* Increment the critical nesting count */ \
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portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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} while( 0 )
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/* Return the previous interrupt status */ \
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uxSavedInterruptStatus; \
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|
} )
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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||||||
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||||||
/**
|
/**
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@ -345,27 +347,27 @@ typedef enum
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||||||
* \ingroup GranularLocks
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* \ingroup GranularLocks
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||||||
*/
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*/
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#if ( portUSING_GRANULAR_LOCKS == 1 )
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#define taskDATA_GROUP_EXIT_CRITICAL( pxTaskSpinlock, pxISRSpinlock ) \
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#define taskDATA_GROUP_EXIT_CRITICAL( pxDataGroup ) \
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do { \
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do { \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ); \
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configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ); \
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/* Decrement the critical nesting count */ \
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/* Decrement the critical nesting count */ \
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portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 ) \
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if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 ) \
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{ \
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{ \
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/* Release the ISR spinlock */ \
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/* Release the ISR spinlock */ \
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portRELEASE_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) pxISRSpinlock ); \
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portRELEASE_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) &( ( pxDataGroup )->xISRSpinlock ) ); \
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/* Enable interrupts */ \
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/* Enable interrupts */ \
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portENABLE_INTERRUPTS(); \
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portENABLE_INTERRUPTS(); \
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/* Release the task spinlock */ \
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/* Release the task spinlock */ \
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portRELEASE_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) pxTaskSpinlock ); \
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portRELEASE_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) &( ( pxDataGroup )->xTaskSpinlock ) ); \
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} \
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} \
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else \
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else \
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||||||
{ \
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{ \
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||||||
mtCOVERAGE_TEST_MARKER(); \
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mtCOVERAGE_TEST_MARKER(); \
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||||||
} \
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} \
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||||||
/* Re-enable preemption */ \
|
/* Re-enable preemption */ \
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||||||
vTaskPreemptionEnable( NULL ); \
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vTaskPreemptionEnable( NULL ); \
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} while( 0 )
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} while( 0 )
|
||||||
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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||||||
|
|
||||||
|
@ -378,18 +380,18 @@ typedef enum
|
||||||
* \ingroup GranularLocks
|
* \ingroup GranularLocks
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||||||
*/
|
*/
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||||||
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
#if ( portUSING_GRANULAR_LOCKS == 1 )
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||||||
#define taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxISRSpinlock ) \
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#define taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( xSavedInterruptStatus, pxDataGroup ) \
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||||||
do { \
|
do { \
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||||||
const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); \
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configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ); \
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configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ); \
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||||||
/* Decrement the critical nesting count */ \
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/* Decrement the critical nesting count */ \
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||||||
portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ); \
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||||||
/* Release the ISR spinlock */ \
|
/* Release the ISR spinlock */ \
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portRELEASE_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) pxISRSpinlock ); \
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portRELEASE_SPINLOCK( xCoreID, ( portSPINLOCK_TYPE * ) &( pxDataGroup->xISRSpinlock ) ); \
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if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 ) \
|
if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 ) \
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||||||
{ \
|
{ \
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||||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
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portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus ); \
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} \
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} \
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||||||
} while( 0 )
|
} while( 0 )
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||||||
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
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||||||
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||||||
|
|
24
queue.c
24
queue.c
|
@ -260,15 +260,15 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
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||||||
* Macros to mark the start and end of a critical code region.
|
* Macros to mark the start and end of a critical code region.
|
||||||
*/
|
*/
|
||||||
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
||||||
#define queueENTER_CRITICAL( pxQueue ) taskDATA_GROUP_ENTER_CRITICAL( &pxQueue->xTaskSpinlock, &pxQueue->xISRSpinlock )
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#define queueENTER_CRITICAL( pxQueue ) taskDATA_GROUP_ENTER_CRITICAL( pxQueue )
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||||||
#define queueENTER_CRITICAL_FROM_ISR( pxQueue, puxSavedInterruptStatus ) taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( &pxQueue->xISRSpinlock, puxSavedInterruptStatus )
|
#define queueENTER_CRITICAL_FROM_ISR( pxQueue ) taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( pxQueue )
|
||||||
#define queueEXIT_CRITICAL( pxQueue ) taskDATA_GROUP_EXIT_CRITICAL( &pxQueue->xTaskSpinlock, &pxQueue->xISRSpinlock )
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#define queueEXIT_CRITICAL( pxQueue ) taskDATA_GROUP_EXIT_CRITICAL( pxQueue )
|
||||||
#define queueEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxQueue ) taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, &pxQueue->xISRSpinlock )
|
#define queueEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxQueue ) taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxQueue )
|
||||||
#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
||||||
#define queueENTER_CRITICAL( pxQueue ) taskENTER_CRITICAL();
|
#define queueENTER_CRITICAL( pxQueue ) taskENTER_CRITICAL();
|
||||||
#define queueENTER_CRITICAL_FROM_ISR( pxQueue, puxSavedInterruptStatus ) do { *( puxSavedInterruptStatus ) = taskENTER_CRITICAL_FROM_ISR(); } while( 0 )
|
#define queueENTER_CRITICAL_FROM_ISR( pxQueue ) taskENTER_CRITICAL_FROM_ISR();
|
||||||
#define queueEXIT_CRITICAL( pxQueue ) taskEXIT_CRITICAL();
|
#define queueEXIT_CRITICAL( pxQueue ) taskEXIT_CRITICAL();
|
||||||
#define queueEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxQueue ) taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
|
#define queueEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxQueue ) taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
|
||||||
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1266,7 +1266,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
|
||||||
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
/* coverity[misra_c_2012_directive_4_7_violation] */
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
queueENTER_CRITICAL_FROM_ISR( pxQueue, &uxSavedInterruptStatus );
|
uxSavedInterruptStatus = ( UBaseType_t ) queueENTER_CRITICAL_FROM_ISR( pxQueue );
|
||||||
{
|
{
|
||||||
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
||||||
{
|
{
|
||||||
|
@ -1444,7 +1444,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
|
||||||
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
/* coverity[misra_c_2012_directive_4_7_violation] */
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
queueENTER_CRITICAL_FROM_ISR( pxQueue, &uxSavedInterruptStatus );
|
uxSavedInterruptStatus = ( UBaseType_t ) queueENTER_CRITICAL_FROM_ISR( pxQueue );
|
||||||
{
|
{
|
||||||
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
||||||
|
|
||||||
|
@ -2097,7 +2097,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
|
||||||
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
/* coverity[misra_c_2012_directive_4_7_violation] */
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
queueENTER_CRITICAL_FROM_ISR( pxQueue, &uxSavedInterruptStatus );
|
uxSavedInterruptStatus = ( UBaseType_t ) queueENTER_CRITICAL_FROM_ISR( pxQueue );
|
||||||
{
|
{
|
||||||
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
||||||
|
|
||||||
|
@ -2198,7 +2198,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
|
||||||
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
/* coverity[misra_c_2012_directive_4_7_violation] */
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
queueENTER_CRITICAL_FROM_ISR( pxQueue, &uxSavedInterruptStatus );
|
uxSavedInterruptStatus = ( UBaseType_t ) queueENTER_CRITICAL_FROM_ISR( pxQueue );
|
||||||
{
|
{
|
||||||
/* Cannot block in an ISR, so check there is data available. */
|
/* Cannot block in an ISR, so check there is data available. */
|
||||||
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
|
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
|
||||||
|
|
|
@ -63,15 +63,15 @@
|
||||||
* Macros to mark the start and end of a critical code region.
|
* Macros to mark the start and end of a critical code region.
|
||||||
*/
|
*/
|
||||||
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
||||||
#define sbENTER_CRITICAL( pxStreamBuffer ) taskDATA_GROUP_ENTER_CRITICAL( &pxStreamBuffer->xTaskSpinlock, &pxStreamBuffer->xISRSpinlock )
|
#define sbENTER_CRITICAL( pxStreamBuffer ) taskDATA_GROUP_ENTER_CRITICAL( pxStreamBuffer )
|
||||||
#define sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer, puxSavedInterruptStatus ) taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( &pxStreamBuffer->xISRSpinlock, puxSavedInterruptStatus )
|
#define sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer ) taskDATA_GROUP_ENTER_CRITICAL_FROM_ISR( pxStreamBuffer )
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||||||
#define sbEXIT_CRITICAL( pxStreamBuffer ) taskDATA_GROUP_EXIT_CRITICAL( &pxStreamBuffer->xTaskSpinlock, &pxStreamBuffer->xISRSpinlock )
|
#define sbEXIT_CRITICAL( pxStreamBuffer ) taskDATA_GROUP_EXIT_CRITICAL( pxStreamBuffer )
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||||||
#define sbEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxStreamBuffer ) taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, &pxStreamBuffer->xISRSpinlock )
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#define sbEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxStreamBuffer ) taskDATA_GROUP_EXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxStreamBuffer )
|
||||||
#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
||||||
#define sbENTER_CRITICAL( pxStreamBuffer ) taskENTER_CRITICAL();
|
#define sbENTER_CRITICAL( pxEventBits ) taskENTER_CRITICAL();
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||||||
#define sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer, puxSavedInterruptStatus ) do { *( puxSavedInterruptStatus ) = taskENTER_CRITICAL_FROM_ISR(); } while( 0 )
|
#define sbENTER_CRITICAL_FROM_ISR( pxEventBits ) taskENTER_CRITICAL_FROM_ISR();
|
||||||
#define sbEXIT_CRITICAL( pxStreamBuffer ) taskEXIT_CRITICAL();
|
#define sbEXIT_CRITICAL( pxEventBits ) taskEXIT_CRITICAL();
|
||||||
#define sbEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxStreamBuffer ) taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
|
#define sbEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus, pxStreamBuffer ) taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
|
||||||
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
#endif /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -138,7 +138,7 @@
|
||||||
do { \
|
do { \
|
||||||
UBaseType_t uxSavedInterruptStatus; \
|
UBaseType_t uxSavedInterruptStatus; \
|
||||||
\
|
\
|
||||||
sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer, &uxSavedInterruptStatus ); \
|
uxSavedInterruptStatus = sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer ); \
|
||||||
{ \
|
{ \
|
||||||
if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
|
if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
|
||||||
{ \
|
{ \
|
||||||
|
@ -217,7 +217,7 @@
|
||||||
do { \
|
do { \
|
||||||
UBaseType_t uxSavedInterruptStatus; \
|
UBaseType_t uxSavedInterruptStatus; \
|
||||||
\
|
\
|
||||||
sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer, &uxSavedInterruptStatus ); \
|
uxSavedInterruptStatus = sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer ); \
|
||||||
{ \
|
{ \
|
||||||
if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
|
if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
|
||||||
{ \
|
{ \
|
||||||
|
@ -1504,7 +1504,7 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
|
||||||
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
/* coverity[misra_c_2012_directive_4_7_violation] */
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer, &uxSavedInterruptStatus );
|
uxSavedInterruptStatus = sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer );
|
||||||
{
|
{
|
||||||
if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
|
if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
|
||||||
{
|
{
|
||||||
|
@ -1543,7 +1543,7 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
|
||||||
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
/* MISRA Ref 4.7.1 [Return value shall be checked] */
|
||||||
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
|
||||||
/* coverity[misra_c_2012_directive_4_7_violation] */
|
/* coverity[misra_c_2012_directive_4_7_violation] */
|
||||||
sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer, &uxSavedInterruptStatus );
|
uxSavedInterruptStatus = sbENTER_CRITICAL_FROM_ISR( pxStreamBuffer );
|
||||||
{
|
{
|
||||||
if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
|
if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
|
||||||
{
|
{
|
||||||
|
|
16
timers.c
16
timers.c
|
@ -83,8 +83,8 @@
|
||||||
* Macros to mark the start and end of a critical code region.
|
* Macros to mark the start and end of a critical code region.
|
||||||
*/
|
*/
|
||||||
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
#if ( portUSING_GRANULAR_LOCKS == 1 )
|
||||||
#define tmrENTER_CRITICAL() taskDATA_GROUP_ENTER_CRITICAL( &xTaskSpinlock, &xISRSpinlock )
|
#define tmrENTER_CRITICAL() taskDATA_GROUP_ENTER_CRITICAL( &xTimerDataGroupLocks )
|
||||||
#define tmrEXIT_CRITICAL() taskDATA_GROUP_EXIT_CRITICAL( &xTaskSpinlock, &xISRSpinlock )
|
#define tmrEXIT_CRITICAL() taskDATA_GROUP_EXIT_CRITICAL( &xTimerDataGroupLocks )
|
||||||
#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
#else /* #if ( portUSING_GRANULAR_LOCKS == 1 ) */
|
||||||
#define tmrENTER_CRITICAL() taskENTER_CRITICAL()
|
#define tmrENTER_CRITICAL() taskENTER_CRITICAL()
|
||||||
#define tmrEXIT_CRITICAL() taskEXIT_CRITICAL()
|
#define tmrEXIT_CRITICAL() taskEXIT_CRITICAL()
|
||||||
|
@ -161,8 +161,16 @@
|
||||||
PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
|
PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
|
||||||
|
|
||||||
#if ( ( portUSING_GRANULAR_LOCKS == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
|
#if ( ( portUSING_GRANULAR_LOCKS == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
|
||||||
PRIVILEGED_DATA static portSPINLOCK_TYPE xTaskSpinlock = portINIT_SPINLOCK_STATIC;
|
PRIVILEGED_DATA static struct
|
||||||
PRIVILEGED_DATA static portSPINLOCK_TYPE xISRSpinlock = portINIT_SPINLOCK_STATIC;
|
{
|
||||||
|
portSPINLOCK_TYPE xTaskSpinlock;
|
||||||
|
portSPINLOCK_TYPE xISRSpinlock;
|
||||||
|
}
|
||||||
|
xTimerDataGroupLocks =
|
||||||
|
{
|
||||||
|
.xTaskSpinlock = portINIT_SPINLOCK_STATIC,
|
||||||
|
.xISRSpinlock = portINIT_SPINLOCK_STATIC
|
||||||
|
};
|
||||||
#endif /* #if ( ( portUSING_GRANULAR_LOCKS == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
|
#endif /* #if ( ( portUSING_GRANULAR_LOCKS == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
|
||||||
|
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
Loading…
Reference in a new issue