This commit updates the __stack_size definition in the
linker flags, changing its value from 350 to 352. This
change ensures that the stack size is a multiple of 16,
aligning the stack pointer (sp) to a 16-byte boundary
as required by the system architecture.
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Increase the memory for RVA23 compilation
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Update the regtest to include fpu registers
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Fix small issues for 64-bit configs
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Enable FPU unit
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Enable compilation for RVA23 platforms
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Fix copyright related CI issues
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Update submodule manifest
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Update a few typos and left overs
* Demo: RISC-V_RV32_QEMU_VIRT_GCC: Apply @aggarg's sugestions
* Update pointer to Freertos-Kernel
* Refactor the trap handler macro
Since `portasmHANDLE_INTERRUPT` is removed at FreeRTOS-kernel, Riscv re-factoring (#444) (commit: 9efca75d1e)
We don't need this definition anymore
We also remove the unused function definition
* Styling the file header to pass the checker
Remove an extra space
Co-authored-by: ztex <ztex030640417@gmail.com>
1. miss debug info in assembly code
RISC-V-spike-htif_GCC
LDFLAGS add arch and abi info for linker
for riscv64-unknown-elf multilib, if there is no arch and abi
info, will link to default lib and have below error
target emulation `elf32-littleriscv' does not match `elf64-littleriscv'
use CFLAGS to replace ASFLAGS when compile assembly code
because DEBUG flag is added in CFLAGS, if we use ASFLAGS to compile
assembly code, there is no debug info in assembly code objfile
2. binutils 2.39 ld warn 'has a LOAD segment with RWX permissions'
RISC-V-Qemu-virt_GCC
RISC-V-spike-htif_GCC
RISC-V_RV32_QEMU_VIRT_GCC
3. fix build fail
RISC-V_RV32_QEMU_VIRT_GCC
Signed-off-by: Eric Chan <e14002270@gmail.com>
When built with PICOLIBC=1, selects picolibc as the C library, uses
semihosting to display messages and uses picolibc stdio for output.
Signed-off-by: Keith Packard <keithpac@amazon.com>
Allocate ROM for initialized thread local storage variables. Allocate
TLS offsets for all thread local storage variables.
Signed-off-by: Keith Packard <keithpac@amazon.com>
Need to add _zicsr for more recent Risc-V toolchains which don't add
this extension to the default set anymore.
Signed-off-by: Keith Packard <keithpac@amazon.com>
* Expand RV32E demo support, prevent 'ebreak' looping
The RegTest tests are modified in the Qemu and HiFive demos
to support RV32E and its limited set of registers.
'ebreak' call looping is removed in RegTest. This produces
a lot of noise when debugging.
* Correct whitespace
* Remove 'ebreak' instruction calls
The ebreak instruction sets and exception
which leads to jumping around the binary. This
can make debugging difficult.
* Fix whitespace formatting
* Simple blinky demo working. Not tried full demo yet.
* Get the full demo running.
* Add Eclipse project to build the RISC-V_RV32_QEMU_VIRT_GCC gcc makefile.
* Add regtest tasks to the RISC-V_RV32_QEMU_VIRT_GCC demo.
* Update priority of the timer task.
* Adjust timer frequency and optimisation level before committing prior to rearranging the Eclipse project.
* Reorganise Eclipse project slightly.
* Add note to the RISC-V-Qemu-virt_GCC readme file about the updated version in RISC-V_RV32_QEMU_VIRT_GCC.
* Update headers in newly added source files so they pass the automated header check.
* Update lexicon to pass automated spell check.
Co-authored-by: none <>
