3 commits

Author	SHA1	Message	Date
Skptak	def7d2df2b	[AUTO][RELEASE]: Bump file header version to "10.5.1"	2022-11-15 20:10:13 +00:00
Jakub Lužný	d91cd6fd05	RISC-V: Add support for RV32E extension in GCC port (#543) ... Co-authored-by: Joseph Julicher <jjulicher@mac.com>	2022-08-30 16:49:37 -07:00
Gaurav-Aggarwal-AWS	9efca75d1e	Riscv re-factoring (#444) ... * Refactor RISCV port Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Changes to make re-factoring work on ESP32-C3 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Remove alignment and place handlers in separate sections Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Correct section names This is needed so that the assemblers correctly recognizes functions. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move mtvec programming to the application Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Refactor mtimer udpate code Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move critical nesting to port layer Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Respect configTASK_RETURN_ADDRESS Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Formatting changes Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	2022-01-26 17:55:01 -08:00