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4 commits

Author SHA1 Message Date
Richard Barry b2b1b09ea5 Fix bug in core_cm3.c atomic macros. 
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
 2019-02-16 01:08:38 +00:00
Richard Barry d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. 
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
 2018-12-28 00:44:18 +00:00
Richard Barry e5daf23d75 Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested. 2018-12-27 04:34:08 +00:00
Richard Barry f7102f2342 Add a starting point for a Freedom Studio Risc V project. 2018-11-24 03:48:55 +00:00