9 commits

Author	SHA1	Message	Date
Richard Barry	b2b1b09ea5	Fix bug in core_cm3.c atomic macros. ... Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.	2019-02-16 01:08:38 +00:00
Richard Barry	11d9c440b8	Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). ... Add a project for the Vega board's RI5CY core.	2018-12-31 18:19:52 +00:00
Richard Barry	e2af102c80	Re-org of RISC-V file structure and naming step 2.	2018-12-30 23:53:47 +00:00
Richard Barry	d369110167	Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. ... Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.	2018-12-28 00:44:18 +00:00
Richard Barry	e5daf23d75	Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested.	2018-12-27 04:34:08 +00:00
Richard Barry	4b9dd38d1c	Backup checking of the Freedom Studio RISC-V project - still a work in progress.	2018-12-04 01:25:53 +00:00
Richard Barry	dc99300fa9	First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.	2018-11-24 20:59:07 +00:00
Richard Barry	d0ef322b13	Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo.	2018-11-24 04:42:20 +00:00
Richard Barry	f7102f2342	Add a starting point for a Freedom Studio Risc V project.	2018-11-24 03:48:55 +00:00