Richard Barry
b51529a284
Update version number ready for next release.
2019-05-11 01:47:37 +00:00
Richard Barry
58ba10eee8
Update version number in readiness for V10.2.0 release.
2019-02-17 22:36:16 +00:00
Richard Barry
92ae8e7aff
Update version numbers ready for release.
2018-09-07 18:13:20 +00:00
Richard Barry
3a1631fda3
Update copyright date ready for tagging V10.1.0.
2018-08-22 23:23:03 +00:00
Richard Barry
fb9de58f56
Update version numbers in preparation for a new release.
2018-08-21 19:50:48 +00:00
Richard Barry
10eea4aded
Remove period from the URL that links to the web page that describes the FreeRTOSConfig.h parameters.
2018-06-15 00:03:20 +00:00
Richard Barry
d30249789b
Previously the MPSoC Cortex-A53 demo was updated to the latest Xilinx SDK tools to the point where it was building, but not tested. This check in modifies the project files slightly following testing.
2018-05-04 15:06:50 +00:00
Richard Barry
26d8c76996
Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED.
2018-05-02 04:04:54 +00:00
Richard Barry
13651934be
Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release.
2017-12-18 22:54:18 +00:00
Richard Barry
cfc268814a
Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt
2017-11-29 16:53:26 +00:00
Richard Barry
8d041c8e21
Update version number in preparation for maintenance release.
2017-01-22 05:28:13 +00:00
Richard Barry
ff55eb920c
Update Zynq MPSoC hardware definition and BSP files to be those shipped with the 2016.4 SDK.
2017-01-19 16:33:13 +00:00
Richard Barry
992a3c8c71
Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
...
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
2017-01-19 04:11:21 +00:00
Richard Barry
2bd7884ace
Prepare for V9.0.0 release:
...
+ Change version number from V9.0.0rc2 to V9.0.0.
2016-05-20 18:05:46 +00:00
Richard Barry
324127837c
Update some more standard demos for use on 64-bit architectures.
...
Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK.
2016-05-06 12:40:27 +00:00
Richard Barry
0cb71ee9ce
Update the Xilinx UltraScale+ demo project to use the BSP and hardware platform generated by the 2016.1 version of the SDK.
2016-04-28 12:49:19 +00:00
Richard Barry
11fe9de0f0
Update the Xilinx UltraScale+ 64-bit demo to use the hardware definition and BSP from version 2016.1 of the SDK.
2016-04-28 12:23:52 +00:00
Richard Barry
4b9c4aa757
Correct comment error that was replicated on many different main_full.c files.
2016-04-04 14:53:04 +00:00
Richard Barry
07ac1399ee
Update version number to 9.0.0rc2.
2016-03-30 12:20:36 +00:00
Richard Barry
d3ba0aa98d
Update version number ready for version 9 release candidate 1.
2016-02-18 17:11:14 +00:00
Richard Barry
f81575dcee
Correct a comment that had been cut and paste into multiple main.c files.
2016-01-12 10:38:16 +00:00
Richard Barry
5690221c5c
Add in the CORTEX_A53_64-bit_UltraScale_MPSoC demo application (a demo has been included in the Xilinx SDK download for some time already).
...
Update a few demo application files to work with 64-bit data types.
2015-12-22 13:56:20 +00:00
