Gaurav Aggarwal
66ce9f7d72
Move warning suppression for IAR compiler to portmacro.h for v8M ports
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IAR produces some warnings which can not be fixed in the source code because
then other compilers start generating warnings. We suppressed those warnings
in the project file before. This change moves the warning suppression from
project files to portmacro.h.
2019-12-07 01:23:17 +00:00
Richard Barry
46e5937529
Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports.
2019-11-21 22:35:21 +00:00
Richard Barry
07622ed3ee
Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.
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Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
2019-11-18 17:23:14 +00:00
Richard Barry
16639d2d63
Update to the latest atomic.h.
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Improve commenting in RISC-V GCC port.
Fix IAR RISC-V port so the first task starts with interrupts enabled.
Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced.
Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section.
Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.
2019-11-18 16:28:03 +00:00
Richard Barry
61a003088d
Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time.
2019-10-21 04:16:32 +00:00
Yuhui.Zheng
0fe36e497d
Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.
2019-09-24 22:26:36 +00:00
Yuhui.Zheng
35bc9d7938
Revert 2728. Not because the files are still needed, but because we want to test out submodule.
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Before further updating project files in GitHub, keeping an additional copy.
2019-09-24 22:19:54 +00:00
Yuhui.Zheng
f001126ea8
Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.
2019-09-24 20:56:55 +00:00
Yuhui.Zheng
9052882500
Adding tickless hooks to GCC/ARM_CRx_No_GIC port.
2019-09-24 20:07:40 +00:00
Richard Barry
80c1cb5de1
Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR.
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Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
2019-09-24 16:06:21 +00:00
Yuhui.Zheng
6f958bbf80
sync from github to svn: Xtensa GCC as-is.
2019-09-20 22:09:21 +00:00
Yuhui.Zheng
1c5fcc7f05
sync from github to svn: Wiced_CY for AFR Cypress ports.
2019-09-20 20:52:30 +00:00
Yuhui.Zheng
74df636c78
sync from github to svn: documentation for RISC-V. This may be a temporary parking location.
2019-09-20 20:47:29 +00:00
Yuhui.Zheng
cc0aee651e
sync from github to svn: Renasas/RX100 #pragma _VECT()
2019-09-20 20:41:32 +00:00
Richard Barry
da3d370ff7
RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
2019-09-04 15:46:45 +00:00
Richard Barry
96bad0f6c3
Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL.
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Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks.
2019-09-04 00:13:17 +00:00
Richard Barry
ab41d89285
Add IAR RISC-V port to SVN - a work in progress.
2019-09-03 01:39:29 +00:00
Richard Barry
973a4f9869
Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
2019-08-27 15:57:45 +00:00
Richard Barry
7d285f3dcb
+ Moved the History.txt file from the website git repo into the source code SVN repo.
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+ Added xTaskCatchUpTicks() which corrects the tick count value after the application code has held interrupts disabled for an extended period.
+ Updated the xTaskResumeAll() implementation so it uses the new xTaskCatchUpTicks() function mentioned above to unwind ticks that were pended while the scheduler was suspended.
+ Various maintenance on the message buffer, stream buffer and abort delay demos.
+ Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it has same type as variables it is compared to, and therefore also rename the variable xPendingTicks.
+ Correct spelling mistake within a comment that was common to all the ARMv7-M ports.
2019-08-25 19:35:59 +00:00
Richard Barry
5352cb4f45
Tidy up Win32 port layer - include addition of new variable that prevents recursive attempts to obtain a mutex when the trace recorder is used inside an interrupt.
2019-08-04 01:14:43 +00:00
Richard Barry
fe4511b35e
Continued to work on the MQTT demo project.
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A few review comments added into the MQTT implementation.
2019-07-24 00:27:14 +00:00
Richard Barry
8bd1813446
Only partially implemented and may get reverted - updates to the Win32 port that uses a per-task event to prevent the task proceeding past its yield point if the SuspendThread() call used to stop the task does not take effect immediately. This is intended to fix issues reported by users, although we have been unable to replicate them ourselves.
2019-07-12 01:52:22 +00:00
Richard Barry
246bb6e806
Add vPortGetHeapStats() function to query heap statistics.
2019-07-04 19:34:48 +00:00
Richard Barry
fb3eaeac40
Added additional xMessageBufferSpacesAvailable() (plural) to existing xMessageBufferSpaceAvailable() (singular) macro as the documentation muddled both.
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Added #define portPOINTER_SIZE_TYPE uint64_t to the 64-bit RISC-V port layer.
2019-05-13 03:14:05 +00:00
Richard Barry
b51529a284
Update version number ready for next release.
2019-05-11 01:47:37 +00:00
Gaurav Aggarwal
aa9c8d2697
Delete the not needed file missed in last commit
2019-05-09 22:09:12 +00:00
Gaurav Aggarwal
b9e379951a
Do not strip required symbols when LTO is on
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Link time optimization was stripping off some symbols which were
accessed from assembly code.
2019-05-09 22:04:29 +00:00
Gaurav Aggarwal
ae448fc952
Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351.
2019-05-02 21:08:28 +00:00
Richard Barry
079d081346
Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit.
2019-04-29 00:57:14 +00:00
Richard Barry
27ca5c8341
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM Cortex-M33 ports to assist with link time optimisation.
2019-04-25 19:49:50 +00:00
Richard Barry
84377442fc
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.
2019-04-21 20:15:34 +00:00
Richard Barry
606845492b
Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence.
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Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.
2019-04-17 17:16:04 +00:00
Gaurav Aggarwal
dd9a9710c6
Export port architecture name for COrtex-M33. This can be used by debuggers to find the port in-use to be able to correctly decode the context stored on the stack.
2019-03-28 00:00:46 +00:00
Gaurav Aggarwal
ba39a958b5
Fix spelling of priority in comments.
2019-03-18 23:28:03 +00:00
Richard Barry
2265d70499
Correcting spelling mistakes in comments only.
2019-03-08 17:30:49 +00:00
Richard Barry
06596c3192
Prepare the RISC-V port layer for addition of 64-bit port.
2019-03-08 17:03:43 +00:00
Gaurav Aggarwal
5fe8465a35
Change type of usStackDepth to configSTACK_DEPTH_TYPE.
2019-02-21 03:25:30 +00:00
Gaurav Aggarwal
5623c69748
Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files.
2019-02-20 20:27:07 +00:00
Richard Barry
8b6ab5f197
Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file.
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Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
2019-02-20 17:55:59 +00:00
Gaurav Aggarwal
5849459c65
Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
2019-02-20 00:25:45 +00:00
Richard Barry
c3c9c12ce2
Update the common demo death.c to use the updated macro name to give it a secure context.
2019-02-19 02:57:44 +00:00
Gaurav Aggarwal
ce576f3683
First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees.
2019-02-19 02:30:32 +00:00
Richard Barry
58ba10eee8
Update version number in readiness for V10.2.0 release.
2019-02-17 22:36:16 +00:00
Gaurav Aggarwal
55ad3861c5
Sync the Renesas port to AFR Git Repo
2019-02-17 01:27:16 +00:00
Richard Barry
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
2019-02-16 01:15:33 +00:00
Richard Barry
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00
Richard Barry
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
2019-02-08 01:18:08 +00:00
Richard Barry
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
2019-01-21 23:39:48 +00:00
Gaurav Aggarwal
817783d75c
Copyright updates from Cadence.
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e1df894752
2019-01-16 19:01:25 +00:00
Richard Barry
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
2018-12-31 18:19:52 +00:00
