According to the RISC-V Privileged Architecture Specification (20211203),
writing Initial or Clean to the FS field of mstatus may result in the FS
value getting set to Dirty in some implementations. This means we cannot
rely on reading back the same FS value after writing to mstatus.
Previously, the context restore code would:
1. Write an FS value to mstatus
2. Read mstatus again at a later point
3. Use the read FS value to determine FPU status
This change updates the context restore code to use the mstatus value
from the saved context instead of re-reading mstatus after writing to
it. This required chaning the location of the mstatus slot in the
context.
Fixes: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1327
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
RISC-V: refine fpu reg context offset
pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).
Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
* port: riscv: Split the number of registers and the size of the context
* port: riscv: Create some macros for the FPU context
* port: riscv: Add a couple of macros that store fpu context
* port: riscv: Update the stack init function to include the fpu context size
* port: riscv: Add a chip_specific_extensions file that includes the F extension
* Update dictionary to include some risc-v instructions
* port: riscv: Fix a few typos
* port: riscv: Apply @aggarg's sugestions
* Use new version of CI-CD Actions
* Use cSpell spell check, and use ubuntu-20.04 for formatting check
* Format and spell check all files in the portable directory
* Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /*
* Use checkout@v3 instead of checkout@v2 on all jobs
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