12 commits

Author	SHA1	Message	Date
Richard Barry	05adf564f6	Add readme into the third party RISC-V port that points to the directories that contains the official ports.	2019-12-24 17:24:23 +00:00
Yuhui.Zheng	0fe36e497d	Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.	2019-09-24 22:26:36 +00:00
Yuhui.Zheng	35bc9d7938	Revert 2728. Not because the files are still needed, but because we want to test out submodule. ... Before further updating project files in GitHub, keeping an additional copy.	2019-09-24 22:19:54 +00:00
Yuhui.Zheng	f001126ea8	Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.	2019-09-24 20:56:55 +00:00
Yuhui.Zheng	6f958bbf80	sync from github to svn: Xtensa GCC as-is.	2019-09-20 22:09:21 +00:00
Yuhui.Zheng	1c5fcc7f05	sync from github to svn: Wiced_CY for AFR Cypress ports.	2019-09-20 20:52:30 +00:00
Gaurav Aggarwal	817783d75c	Copyright updates from Cadence. ... e1df894752	2019-01-16 19:01:25 +00:00
Richard Barry	c6de0001fa	Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. ... Allows the task name parameter passed into xTaskCreate() to be NULL.	2018-09-30 21:50:05 +00:00
Gaurav Aggarwal	56dc0dd9b4	Merge bug fixes from Cadence	2018-08-07 07:21:07 +00:00
Richard Barry	483f4a8c4b	Small change to the directory name in which the RISC-V port is stored.	2018-06-20 21:15:04 +00:00
Richard Barry	3d8d2f3cc8	Add RISCV port layer.	2018-06-20 19:21:18 +00:00
Gaurav Aggarwal	c4b1afc4ef	Add Xtensa port ... The project file is for Xtensa Xplorer simulator. Also add tests for one size stream buffer.	2018-06-14 19:43:17 +00:00