4 commits

Author	SHA1	Message	Date
Richard Barry	bdbf347c22	Remove clrex instruction from Cortex-M ports again as it is implicit in interrupt entry.	2016-06-28 10:39:25 +00:00
Richard Barry	c296e2cff8	Improvements to the Cortex-M ports: ... - Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler). - Ensure atomic operations are thread safe by executing clrex in the context switch.	2016-06-27 13:13:05 +00:00
Richard Barry	2bd7884ace	Prepare for V9.0.0 release: ... + Change version number from V9.0.0rc2 to V9.0.0.	2016-05-20 18:05:46 +00:00
Richard Barry	ee9cd40b6d	Add GCC ARM Cortex-M4F MPU port. ... Add RVDS ARM Cortex-M4F MPU port. Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining. Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.	2016-05-18 10:41:28 +00:00