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Author SHA1 Message Date
Richard Barry d269f2027a Demo project only: Cyclone V SoC now running from external RAM. 2014-10-01 09:30:35 +00:00
Richard Barry e2f2cfa816 Added project for Altera Cyclone V SoC, currently running from internal RAM. 2014-09-30 15:32:19 +00:00
Richard Barry 3b0854bf96 Core kernel code: 
+ Introduce xSemaphoreGenericGiveFromISR() as an optimisation when giving semaphores and mutexes from an interrupt.

Demo applications:
+ Update IntSemTest.c to provide more code coverage in xSemaphoreGenericGiveFromISR().
+ Ensure the MMU is turned on in the RZ IAR demo.  It was already on in the RZ ARM demo.
 2014-09-16 14:54:32 +00:00
Richard Barry b3c040fc27 SAM4L tickless implementation: Bug fix and update the demo project to exercise the fix. 2014-09-16 12:24:14 +00:00
Richard Barry 4f03f7d1bb Demo project only: 
Add the new IntSem test/demo code into the MSVC demo project.
 2014-09-12 11:32:47 +00:00
Richard Barry b6e4854f26 Demo tasks only, with the aim of improving test coverage: 
+ Split out the code that uses a mutex from an interrupt from GenQTest.c and add to new common demo task IntSemTest.c.
 2014-09-11 12:06:27 +00:00
Richard Barry d55e7e77a2 Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into individual port layers so it does not affect ports that do not support the definition. 2014-09-02 22:39:54 +00:00
Richard Barry 33cc3a292b Demo code only: 
Add the IntQ standard test to the SAM4S project.
 2014-09-02 16:06:57 +00:00
Richard Barry 99229b597b Correct potential compiler warning when configUSE_MUTEXES is set to 0. 
Add comments.
 2014-08-30 20:18:18 +00:00
Richard Barry a60ce58731 Update version number to 8.1.1 for patch release that re-enables mutexes to be given from an interrupt. 2014-08-29 19:14:23 +00:00
Richard Barry ff5d3512b3 Core kernel code: 
- Re-introduce the ability to give a mutex from an ISR.

Common demo code:
- Add additional tests into the GenQTest files for priority inheritance and using a mutex from an ISR.
 2014-08-29 13:53:58 +00:00
Richard Barry 6507701fdf Lower the minimum stack size used by the ATSAMA5 demo. 2014-08-26 16:53:40 +00:00
Richard Barry 7d49c2190c Minor edits prior to tagging V8.1.0. 2014-08-26 16:23:09 +00:00
Richard Barry d33a14b5fb ***IMMINENT RELEASE NOTICE*** 
Update version numbers ready for FreeRTOS V8.1.0 release in about 10 days.
 2014-08-16 20:19:40 +00:00
Richard Barry 52e687086c Demo application related: 
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.

Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.

Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.
 2014-08-16 14:29:39 +00:00
Richard Barry 162448f06b General maintenance - changing comments and correcting spellings only. 2014-08-04 07:57:18 +00:00
Richard Barry 60538c7480 Common demo tasks: 
- Add additional tests to GenQTest.c to test the updated priority inheritance mechanism.
- Slightly increase some delays in recmutex.c to prevent it reporting false errors in high load test cases.

SAMA5D3 Xplained IAR demo:
- Remove space being allocated for stacks that are not used.
- Remove explicit enabling of interrupts in ISR handers as this is now done from the central ISR callback before the individual handers are invoked.
- Reduce both the allocated heap size and the stack allocated to each task.
- Enable I cache.
 2014-08-04 07:53:20 +00:00
Richard Barry 47f895cb34 Cortex-A5 IAR port: 
- Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.
 2014-08-03 19:15:30 +00:00
Richard Barry b2e739495a Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.: 
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
 2014-08-03 18:37:58 +00:00
Richard Barry 3a3d061cc5 Continue working on the GIC-less Cortex-A5 port for IAR: 
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
 2014-07-29 21:31:04 +00:00
Richard Barry e9b5deb34a Carry on working on SAMA5D3 demo: 
- Add full interrupt nesting tests.
- Add additional critical section/context switching tests.
- Set interrupt priorities so everything can run at once without any software watchdog errors.
- Re-enable interrupts in each IRQ handler.
- Add in run-time stats.
 2014-07-29 21:28:22 +00:00
Richard Barry 146b46df87 SAMA5D3 demo: Add CDC driver code and use CDC to create a simple command console. 2014-07-23 21:07:03 +00:00
Richard Barry 5fcd270398 Re-test Zynq demo now it is using the latest tools. 2014-07-14 14:01:07 +00:00
Richard Barry bd9d37924d Add back Zynq demo - this time using SDK V14.2. 2014-07-14 13:00:18 +00:00
Richard Barry 96ceb9f537 Remove Zynq demo project ready to recreate the project using the 14.2 version of Xilinx's SDK. 2014-07-14 11:46:34 +00:00
Richard Barry 5b96cf6eea Add 'full' demo to the SAMA5 Xplained demo - but so far without interrupt nesting tests or CLI. 2014-07-12 20:40:33 +00:00
Richard Barry 8ad9b75810 Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit. 2014-07-12 20:39:22 +00:00
Richard Barry 29336e35b5 SAMA5D3 Xplained demo blinky running. 2014-07-12 19:25:18 +00:00
Richard Barry f4a1a7d577 Add new port layer for Cortex-A devices without the means to mask interrupt priorities. 2014-07-12 19:21:04 +00:00
Richard Barry 5b96c12e92 Start of SAMA5D3 XPlained demo. 2014-07-09 21:19:01 +00:00
Richard Barry 8aa5fa3459 Make the parameters to vPortDefineHeapRegions() const. 
Add additional asserts to the Keil CM3 and CM4F ports (other CM3/4 ports already updated).
Add the additional yield necessitated by the mutex held count to the case when configUSE_QUEUE_SETS is 0.
 2014-07-04 13:17:21 +00:00
Richard Barry 4fe2abc792 Update the MSVC simulator demo to demonstrate heap_5 allocator and pdTICKS_TO_MS macro being used. 2014-07-03 16:49:29 +00:00
Richard Barry d96dc2adb0 Simply some of the alignment calculations in heap_4.c to match those used in heap_5.c. 
Remove some apparently obsolete code from xTaskPriorityDisinherit() (a task cannot be both blocked and giving bac a mutex at the same time].
Update the new "mutex held count" increment and decrement functions to allow mutexes to be created before the scheduler is started.
 2014-07-03 14:44:37 +00:00
Richard Barry b0ba273489 Check in the portable.h version required to use heap_5.c. 2014-07-02 10:20:35 +00:00
Richard Barry 4b26dc0614 Check in the new memory allocator that allows the heap to span multiple blocks. 2014-07-02 10:19:49 +00:00
Richard Barry 4ce4de750a Update timer demo in PIC32MZ demo to remove multiple extern definition created by adding in the macro that checks non ISR safe functions are not called from ISRs. 2014-06-16 13:07:01 +00:00
Richard Barry 42b1688a30 Implementation of mutex held counting in tasks.c - needs optimisation before release. 2014-06-16 12:55:50 +00:00
Richard Barry 583b144bc3 Default the definition of portASSERT_IF_IN_ISR() to nothing if it is not defined. 
Helper updates to allow a count of the number of mutexes held to be added.
Updates to the CCS Cortex-R4 implementation necessitated by a change in compiler semantics.
Update PIC32MX and MZ ports to assert if a non ISR safe function is called from an ISR.
 2014-06-16 12:51:35 +00:00
Richard Barry b4659d8872 Add code to assert() if non ISR safe API function is called from ISR in Tasking CM4F ports - plus fix bug where the max syscall interrupt priority was used incorrectly in the Tasking CM4F port. 2014-06-15 09:24:08 +00:00
Richard Barry 113220628f Add code to assert() if non ISR safe API function is called from ISR in IAR and GCC CM3 and CM4F ports - Keil and tasking to follow. 2014-06-14 13:56:25 +00:00
Richard Barry 4723209074 Simplify the assert that checks if a non-ISR safe function is called from an ISR in the GCC Cortex-A9 port. 2014-06-13 14:08:28 +00:00
Richard Barry d45f18cc8d Add additional comments to the Zynq lwIP demo. 2014-06-13 14:06:43 +00:00
Richard Barry 8426eba8e7 Added portASSERT_IF_IN_INTERRUPT() macro to the GCC Cortex A9 port layer. 2014-06-12 16:28:56 +00:00
Richard Barry de7df3cfda Zynq demo: Fix Xilinx network driver by deferring the function that allocated memory from the interrupt into a task. Add DHCP option. 2014-06-12 16:27:35 +00:00
Richard Barry f1a0534a56 Remove some of the lwip asserts to allow use with 64-bit alignment. 2014-06-10 16:29:32 +00:00
Richard Barry 7fa64efeeb Switch to using the private watchdog as the run time stats timer in the Zynq demo. 2014-06-10 16:25:46 +00:00
Richard Barry 2f6cb8a86c Reorganise Zynq project after spitting lwIP example into a separate configuration. 2014-06-09 20:20:23 +00:00
Richard Barry e92795bcc8 Move the Zynq's lwIP example from the Full demo into its own configuration as having the lwIP tasks at a high priority made the self checking test tasks report failures, while having the lwIP tasks at a low priority slugged the throughput. 2014-06-09 19:35:08 +00:00
Richard Barry be8b0ed21d Update lwIP byte alignment to make Zynq pings more reliable. 2014-06-09 12:43:18 +00:00
Richard Barry 16ff69e873 Update RL78 GCC demo application after testing with fixed compiler. 2014-06-05 12:44:38 +00:00
Richard Barry 9efb5c8b2f Check in RL78 GCC port layer now it has been verified with the fixed compiler. 2014-06-05 12:42:49 +00:00
Richard Barry 5cbab67186 Complete RX64M GCC demo. 2014-06-04 09:19:16 +00:00
Richard Barry 1130a53ec8 Reverse order of projdefs.h and FreeRTOSConfig.h includes in FreeRTOS.h to allow addition of pdMS_TO_TICKS() macro. 
Update RXv2 GCC port to match RXv2 Renesas port.
 2014-06-04 09:17:14 +00:00
Richard Barry 5cd0b1e5ef Add -nomessage command line option to RX64M demo to suppress warning about the yield function being defined when it is not called directly. 2014-05-29 13:56:16 +00:00
Richard Barry f46070dc79 Ensure demo app files are using FreeRTOS V8 names - a few were missed previously. 2014-05-29 13:54:15 +00:00
Richard Barry ef254df85f A few additional casts to keep the Renesas RX compiler happy. 2014-05-29 13:39:48 +00:00
Richard Barry 74ffdb0b89 Add lwIP driver into Zynq demo - not yet fully functional. 2014-05-23 16:38:18 +00:00
Richard Barry 09a89763ee Add brackets in lwIP assert statement to prevent compiler warnings. 2014-05-23 16:36:49 +00:00
Richard Barry b215310e63 Add some missing volatiles to __asm statements in the CA9 GCC port. 2014-05-19 13:14:02 +00:00
Richard Barry 0bb794301a Update version number ready for release. 2014-04-24 14:26:36 +00:00
Richard Barry 911e82a909 Add xQueueGetMutexHolder() to MPU functions. 2014-04-24 12:29:40 +00:00
Richard Barry f25503977e Event Groups: Convert the 'clear bits from ISR' function into a pended function to fix reentrancy issue. 
Event Groups: Ensure the 'wait bits' and 'sync' functions don't return values that still contain some internal control bits.
 2014-04-23 15:23:54 +00:00
Richard Barry fa7222ab4a Update demos that use FreeRTOS+FAT SL to have correct version numbers after the update of FreeRTOS+FAT SL itself. 2014-04-23 14:34:49 +00:00
Richard Barry 03c95b5950 Update IAR XMC4200 project to fix link error that resulted from updating the IAR version to 7.x. 2014-04-23 13:59:56 +00:00
Richard Barry 6af9b013eb Ensure xNewLib_reent is reclaimed when a task is deleted. 2014-04-09 09:07:19 +00:00
Richard Barry 82207ebffa Add test and correct code for the unusual case of a task using an event group to synchronise only with itself. 
Add critical sections around call to prvResetNextTaskUnblockTime() that can occur from within a task.
 2014-03-31 02:12:17 +00:00
Richard Barry ef7f3c5320 Add the pcTimerGetTimerName() API function. 2014-03-28 14:41:15 +00:00
Richard Barry 887fcd04f4 Add interrupt nesting test code into RX64M demo. 2014-03-28 13:05:29 +00:00
Richard Barry 42cbd6a778 Add RSK definition and LED flash tasks into RX64M demo. 2014-03-28 11:47:40 +00:00
Richard Barry 29a08b5e24 Update Cortex-A port layers to ensure the ICCRPR and ICCPMR registers are always accessed as 32-bit values. 2014-03-25 17:12:31 +00:00
Richard Barry d59bf60ff9 Started to create RX64M GCC project - building but not yet converted to new core. 2014-03-20 12:04:49 +00:00
Richard Barry 6fe7e7ef67 Delete old RL78 launch configurations. 2014-03-19 16:45:53 +00:00
Richard Barry 7f7ad3d081 Add RL78/L1C configuration into e2studio demo. 2014-03-19 16:44:58 +00:00
Richard Barry 2283bfb0ae RL78/L1C configuration added to the IAR RL78 demo projects. 2014-03-19 13:29:11 +00:00
Richard Barry a5f00caf16 Working but incomplete RXv2 demo. 2014-03-07 17:13:05 +00:00
Richard Barry 05a0e4379e First pass at RXv2 port layer. 2014-03-07 17:12:06 +00:00
Richard Barry 3788026636 RXv1 tests running before updating to RXv2. 2014-03-06 12:46:16 +00:00
Richard Barry b17ab311af Start to create an RX64M demo. 2014-03-03 16:39:41 +00:00
Richard Barry 9bd5e5cf03 Cast away a few unused return types to ensure lint/compilers don't generate warnings when the warning level is high. 2014-02-23 20:01:07 +00:00
Richard Barry c8953a68cd Add extra #error message as a configuration sanity check. 2014-02-19 13:08:34 +00:00
Richard Barry ba6d285ea8 Minor updates to ensure all kernel aware debuggers are happy with V8. 2014-02-19 11:58:52 +00:00
Richard Barry e101e7e437 Update version number to V8.0.0 (without the release candidate number). 2014-02-18 14:01:57 +00:00
Richard Barry 38ae9b76bc Add logic to determine the tick timer source and vector installation into the PIC32MZ port assembly file to allow more efficient interrupt entry. 2014-02-18 10:10:32 +00:00
Richard Barry c3dd6f6593 Add event group code to the PIC32MZ demo. 2014-02-18 10:08:33 +00:00
Richard Barry 0f6b699eef Linting. 2014-02-17 19:41:29 +00:00
Richard Barry a2089bbcf6 Add #define INCLUDE_eTaskGetState 1 to the demos that use the int queue test. 2014-02-17 19:32:20 +00:00
Richard Barry d6da7b1231 Remove test of trace functions from the Win32/GCC build as it messes up the trace recorder. 2014-02-17 12:56:05 +00:00
Richard Barry 0ccfdd1021 Remove test of trace functions from the Win32 build as it messes up the trace recorder. 2014-02-17 12:48:18 +00:00
Richard Barry 853696a991 Add event groups demo to SAM4E demo. 2014-02-16 22:03:39 +00:00
Richard Barry b7eb76904a Add event group tests to IAR LM3S demo. 2014-02-16 21:47:07 +00:00
Richard Barry e4dbc6b770 Make xEventGroupSetBitsFromISR() a function when configUSE_TRACE_FACILITY is enabled to allow the inclusion of a trace macro. 2014-02-14 11:07:25 +00:00
Richard Barry b96016e234 Follow instructions on http://blogs.msdn.com/b/vsproject/archive/2009/07/21/enable-c-project-system-logging.aspx to manually prevent MSVC from incorrectly reporting the MSVC demo project as being out of date. 2014-02-11 15:15:36 +00:00
Richard Barry 5a2a8fc319 Update the demo directory to use the version 8 type naming conventions. 2014-02-11 12:04:59 +00:00
Richard Barry c6d8892b0d Replace xTaskIsTaskSuspended() call with eTaskGetState() call in IntQueue.c as the former is now a private function. 2014-02-11 11:38:33 +00:00
Richard Barry 4f01401c00 Add a small amount of randomisation into the Zynq demo. 2014-02-11 11:37:42 +00:00
Richard Barry 0cc51d99a7 Add event groups demo to Zynq demo. 
Add C implementations of some standard library functions to the Zynq demo to prevent the GCC libraries (which use floating point registers as scratch registers) being linked in.
 2014-02-11 09:24:33 +00:00
Richard Barry 3eb212f454 Update IAR RL78 demo regtest tasks to make use of SKZ instructions as the latest IAR linker didn't seem to like the previous version. 2014-02-10 19:13:49 +00:00
Richard Barry 84f4ae9aa0 Make xTaskIsTaskSuspended() a private function as it should only be called from within critical sections. 
Fix issue in and simplify the xTaskRemoveFromUnorderedEventList() function.  The function is new to the V8 release candidates so does not effect official released code.
 2014-02-10 17:02:37 +00:00
Richard Barry eea669240b Remove inclusion of now removed header file from the RZ/IAR LowLevelInitialise.c file. 2014-02-10 14:22:19 +00:00
Richard Barry d4ca65f22f Third attempt: Improve how TimerDemo.c manages differences between the tick count and its own internal tick count, which can temporarily differ when the tick hook is called while the scheduler is suspended. 2014-02-10 14:21:17 +00:00