8 commits

Author	SHA1	Message	Date
Richard Barry	079d081346	Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit.	2019-04-29 00:57:14 +00:00
Richard Barry	84377442fc	Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.	2019-04-21 20:15:34 +00:00
Richard Barry	606845492b	Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence. ... Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.	2019-04-17 17:16:04 +00:00
Richard Barry	2265d70499	Correcting spelling mistakes in comments only.	2019-03-08 17:30:49 +00:00
Richard Barry	06596c3192	Prepare the RISC-V port layer for addition of 64-bit port.	2019-03-08 17:03:43 +00:00
Richard Barry	58ba10eee8	Update version number in readiness for V10.2.0 release.	2019-02-17 22:36:16 +00:00
Richard Barry	6844bef74f	Replace the pdf RISC-V documentation with links to the documentation web pages.	2019-02-16 01:15:33 +00:00
Richard Barry	b2b1b09ea5	Fix bug in core_cm3.c atomic macros. ... Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.	2019-02-16 01:08:38 +00:00