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Author SHA1 Message Date
Kody Stribrny
1d59f65007
Add IAR RISC-V 32 Embedded Extension Support (#588) 
Adds RV32E support to the IAR port. This is done by
reducing our register usage to the first 16 registers
only.

Influenced by changes in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/543

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
 2022-11-29 14:55:18 -08:00
Ming Yue
f789a0e790
Update RISC-V IAR port to support vector mode. (#458) 
* Update RISC-V IAR port to support vector mode.

* uncrustify

Co-authored-by: David Chalco <david@chalco.io>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>
 2022-09-20 15:32:41 -07:00