Richard Barry
c861e3883d
Add coverage test markers.
2013-12-23 18:11:15 +00:00
Richard Barry
64ad1c00b5
In process of module testing event_groups.c.
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Introduce xPortRunning variable into Win32 simulator port layer.
Add port optimised task selection macro for the GCC Win32 port layer (the MSVC version has had one for a while).
Ensure the event list item value does not get modified by code in tasks.c (priority inheritance, or priority change) when it is in use by the event group implementation.
2013-12-23 16:02:03 +00:00
Richard Barry
4b2f9dad42
Force the SysTick clock bit to be set in Cortex-M3 and Cortex-M4F bits if configSYSTICK_CLOCK_HZ is not defined, otherwise leave the bit as it is found as the SysTick may use a divided clock.
2013-12-15 10:27:37 +00:00
Richard Barry
a320d6dffd
Update the ucQueueNumber member of the queue structure (used with FreeRTOS+Trace to be an unsigned portBASE_TYPE instead of an unsigned char.
2013-12-14 13:16:05 +00:00
Richard Barry
acad916453
Change the way one thread deletes another in the Windows simulator port (the way one thread deleted itself was already changed in a previous check-in).
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Reset the expected block time variable when a task is suspended or deleted in case the value held in the variables was associated with the task just suspended or deleted.
2013-12-12 16:07:24 +00:00
Richard Barry
0d1e12522b
Update Cortex-M3 and Cortex-M4F ports to allow the SysTick to be clocked at a different speed than the system clock (as is done in the recent STM32L demo. ).
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Add additional asserts and isb instructions into the Cortex-M3 and Cortex-M4F ports.
2013-12-12 14:07:20 +00:00
Richard Barry
6b3393b4b6
Add trace macros into the event groups implementation.
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Add a task pre-delete hook to allow the insertion of any port specific clean up when a task is deleted.
Increase use of 'const' qualifiers.
Add vPortCloseRunningThread() into the Win32 port layer to attempt to allow Windows threads to be closed more gracefully when a task deletes itself.
2013-12-12 10:19:07 +00:00
Richard Barry
00ad1a0200
Multiple tidy up, documentation corrections and typo corrections highlighted by Tamas Kleiber's diligent review.
2013-11-28 10:48:33 +00:00
Richard Barry
f54f21b8f6
Add event_groups.c and associated functions in other core files.
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Added xTimerPendCallbackFromISR() to provide a centralised deferred interrupt handling mechanism.
Add xPortGetLowestEverFreeHeapSize() to heap_4.c.
2013-11-21 21:46:08 +00:00
Richard Barry
fa002f7fdd
Final tidy up before V7.6.0 zip file creation.
2013-11-17 15:46:08 +00:00
Richard Barry
0cd79ad81d
Change version numbers in preparation for V7.6.0 release.
2013-11-08 11:47:35 +00:00
Richard Barry
b181a3af99
Ensure the definition of prvTaskExitError()does not result in a compiler warning in ports where its use can be overridden (GCC Cortex-M ports).
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Remove duplicate save/restore of r14 in Cortex-M4F ports.
2013-11-07 16:43:54 +00:00
Richard Barry
30bc6c01a9
Add ehb instructions back into PIC32 port layer (upon advice).
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Add configCLEAR_TICK_TIMER_INTERRUPT into PIC32 port layer to allow the timer configuration to be changed without any edits to the port layer being required.
Add prvTaskExitError() into the PIC32 port layer to trap tasks that attempt to exit from their implementing function.
Provide the ability to trap interrupt stack overflows in the PIC32 port.
Radically improve the timing in the Win32 simulator port layer.
2013-11-07 14:16:32 +00:00
Richard Barry
dcd261bb8b
Update the Keil and IAR CM0 port layers to match the changes made to the GCC version.
2013-10-22 11:26:16 +00:00
Richard Barry
41fe693968
Improve how the scheduler is started in the GCC Cortex-M0 port.
2013-10-22 09:50:20 +00:00
Richard Barry
a12ea2d212
Update FreeRTOS version number to V7.5.3
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Update FreeRTOS+CLI version number to V1.0.2
Update FreeRTOS+UDP version number to V1.0.1
2013-10-14 19:56:47 +00:00
Richard Barry
94607d83f9
Add workaround to XMC4000 silicon bug to Tasking Cortex-M4F port layer.
2013-10-14 14:03:05 +00:00
Richard Barry
0c56f5018d
Add some defensive programming in the default tickless mode in case the application supplied post tick hook takes a long time to complete.
2013-10-08 12:33:46 +00:00
Richard Barry
aedf7824cb
Introduce the prvTaskExitError() function for all ARM_CMn ports.
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Introduce the configTASK_RETURN_ADDRESS macro for the GCC ARM_CMn ports.
Improve time slippage penalty when entering tickless mode is abandoned.
2013-10-08 11:30:40 +00:00
Richard Barry
eaacbb099a
Clear up a few compiler warnings.
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Correct header comments in the UARTCommandConsole.c file used in the SmartFusion2 demo.
Exercise the new xQueueSpacesAvailable() function in the MSVC demo.
Add defaults for the new traceMALLOC and traceFREE trace macros.
Catch tasks trying to exit their functions in the Cortex-M0 ports.
Add additional comments to timers.c in response to a support forum question.
Initialise _impure_ptr prior to the first task being started.
Prior to V7.5.0 a yield pended in the tick hook would have occurred during the same tick interrupt. Return pdTRUE from xTaskIncrementTick() if a yield is pending to revert to that behaviour.
2013-10-07 12:06:17 +00:00
Richard Barry
7ec4773131
Add traceMALLOC() and traceFREE() macros.
2013-10-04 20:56:45 +00:00
Richard Barry
73606369c4
Make Cortex-M0 set/clear interrupt flag from ISR functions nestable.
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Don't reset the stack location when starting the scheduler in Cortex-M0 ports as the vector offset register is not implemented and XMC1000 devices have their application vector address somewhere other than 0x00.
2013-09-01 19:53:24 +00:00
Richard Barry
574f5044a6
Starting point for Keil Cortex-M0 port.
2013-08-25 01:01:18 +00:00
Richard Barry
c40370e96a
Fix a few typos and remove the "register" keyword.
2013-08-16 13:31:54 +00:00
Richard Barry
2f754d9b0c
Add additional critical section to the default tickless implementations.
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Update version number for maintenance release.
2013-07-24 09:45:17 +00:00
Richard Barry
3cbe0a724d
Update version number.
2013-07-23 10:51:45 +00:00
Richard Barry
bb2093cf5d
Update the header file included in the PIC32 port_asm.S file to use the header for the latest compiler version.
2013-07-23 09:50:06 +00:00
Richard Barry
679a3c670c
Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library.
2013-07-23 09:44:00 +00:00
Richard Barry
203ae64600
Rename xTaskGetSystemState() uxTaskGetSystemState().
2013-07-18 14:41:15 +00:00
Richard Barry
7d6758ee1a
Minor updates and change version number for V7.5.0 release.
2013-07-17 18:32:57 +00:00
Richard Barry
7d1292ced2
Linting and MISRA checking
2013-07-15 14:27:15 +00:00
Richard Barry
ce9c3b7413
Variable name change in the PIC32 port layer only.
2013-07-14 13:06:17 +00:00
Richard Barry
da0fff63c9
Update Cortex-M MPU version to include new API functions.
2013-07-13 19:37:35 +00:00
Richard Barry
e5d9640863
Update RX ports to only include additional check on the existing IPL (so it is not lowered) if configASSERT() is defined.
2013-07-13 11:31:35 +00:00
Richard Barry
4b964814de
Implement portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for PIC32.
2013-07-12 19:25:21 +00:00
Richard Barry
ad8fa53043
Kernel optimisations.
2013-07-12 11:11:19 +00:00
Richard Barry
5d902f2b9c
Complete additions of portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for all RX compiler ports.
2013-07-11 10:05:06 +00:00
Richard Barry
65704174c9
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler.
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Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
2013-07-09 17:57:59 +00:00
Richard Barry
0f6b0d3a59
Enhance heap_4.c to prevent blocks accidentally being freed twice, or blocks that don't have a valid block link descriptor being freed.
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Update the Cortex-A9 port to include asserts if an ISR safe FreeRTOS function is called from an interrupt that has a higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY (or whatever the CA9 equivalent is called), and also assert if the binary point is not set correctly.
2013-07-09 12:49:49 +00:00
Richard Barry
c4eef61d39
Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports.
2013-07-04 11:20:28 +00:00
Richard Barry
0c0b54c175
Refine the default tickless idle implementation in the Cortex-M3 port layers.
2013-06-30 10:38:31 +00:00
Richard Barry
a7c47131fa
Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose.
2013-06-25 13:39:50 +00:00
Richard Barry
6cbbfd2eb5
Slight correction to coding standard in heap_2.c and heap_4.c.
2013-06-25 13:25:08 +00:00
Richard Barry
fb47260e80
Improve efficiency of memory allocation when the memory block is already aligned correctly.
2013-06-25 12:20:29 +00:00
Richard Barry
c3f9e3c5ff
Update RVDS port layer to match IAR port layer.
2013-06-20 14:56:40 +00:00
Richard Barry
5013baa2cd
RVDS ARM Cortex-A port layer.
2013-06-20 12:47:21 +00:00
Richard Barry
04dafed839
IAR ARM Cortex-A port layer.
2013-06-20 12:20:40 +00:00
Richard Barry
2fd431e971
Modify the GCC/AVR port to make use of the xTaskIncrementTick return value.
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Add pre-processor directives in the dsPIC and PIC24 port layers that allows both port files to be included in the same project.
2013-06-11 20:15:15 +00:00
Richard Barry
62c0ae0926
Update port layers to make better use of the xTaskIncrementTick() return value.
2013-06-08 18:36:25 +00:00
Richard Barry
59a834eb86
Update ports that have their tick configuration in an application callback to use xTaskIncrementTick() in place of vTaskIncrementTick().
2013-06-07 12:39:56 +00:00
