Need to add _zicsr for more recent Risc-V toolchains which don't add
this extension to the default set anymore.
Signed-off-by: Keith Packard <keithpac@amazon.com>
* Expand RV32E demo support, prevent 'ebreak' looping
The RegTest tests are modified in the Qemu and HiFive demos
to support RV32E and its limited set of registers.
'ebreak' call looping is removed in RegTest. This produces
a lot of noise when debugging.
* Correct whitespace
* Remove 'ebreak' instruction calls
The ebreak instruction sets and exception
which leads to jumping around the binary. This
can make debugging difficult.
* Fix whitespace formatting
* Simple blinky demo working. Not tried full demo yet.
* Get the full demo running.
* Add Eclipse project to build the RISC-V_RV32_QEMU_VIRT_GCC gcc makefile.
* Add regtest tasks to the RISC-V_RV32_QEMU_VIRT_GCC demo.
* Update priority of the timer task.
* Adjust timer frequency and optimisation level before committing prior to rearranging the Eclipse project.
* Reorganise Eclipse project slightly.
* Add note to the RISC-V-Qemu-virt_GCC readme file about the updated version in RISC-V_RV32_QEMU_VIRT_GCC.
* Update headers in newly added source files so they pass the automated header check.
* Update lexicon to pass automated spell check.
Co-authored-by: none <>
