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458 commits

Author SHA1 Message Date
Richard Barry
47f895cb34 Cortex-A5 IAR port: 
- Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.
 2014-08-03 19:15:30 +00:00
Richard Barry
b2e739495a Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.: 
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
 2014-08-03 18:37:58 +00:00
Richard Barry
3a3d061cc5 Continue working on the GIC-less Cortex-A5 port for IAR: 
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
 2014-07-29 21:31:04 +00:00
Richard Barry
e9b5deb34a Carry on working on SAMA5D3 demo: 
- Add full interrupt nesting tests.
- Add additional critical section/context switching tests.
- Set interrupt priorities so everything can run at once without any software watchdog errors.
- Re-enable interrupts in each IRQ handler.
- Add in run-time stats.
 2014-07-29 21:28:22 +00:00
Richard Barry
146b46df87 SAMA5D3 demo: Add CDC driver code and use CDC to create a simple command console. 2014-07-23 21:07:03 +00:00
Richard Barry
5fcd270398 Re-test Zynq demo now it is using the latest tools. 2014-07-14 14:01:07 +00:00
Richard Barry
bd9d37924d Add back Zynq demo - this time using SDK V14.2. 2014-07-14 13:00:18 +00:00
Richard Barry
96ceb9f537 Remove Zynq demo project ready to recreate the project using the 14.2 version of Xilinx's SDK. 2014-07-14 11:46:34 +00:00
Richard Barry
5b96cf6eea Add 'full' demo to the SAMA5 Xplained demo - but so far without interrupt nesting tests or CLI. 2014-07-12 20:40:33 +00:00
Richard Barry
8ad9b75810 Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit. 2014-07-12 20:39:22 +00:00
Richard Barry
29336e35b5 SAMA5D3 Xplained demo blinky running. 2014-07-12 19:25:18 +00:00
Richard Barry
f4a1a7d577 Add new port layer for Cortex-A devices without the means to mask interrupt priorities. 2014-07-12 19:21:04 +00:00
Richard Barry
5b96c12e92 Start of SAMA5D3 XPlained demo. 2014-07-09 21:19:01 +00:00
Richard Barry
8aa5fa3459 Make the parameters to vPortDefineHeapRegions() const. 
Add additional asserts to the Keil CM3 and CM4F ports (other CM3/4 ports already updated).
Add the additional yield necessitated by the mutex held count to the case when configUSE_QUEUE_SETS is 0.
 2014-07-04 13:17:21 +00:00
Richard Barry
4fe2abc792 Update the MSVC simulator demo to demonstrate heap_5 allocator and pdTICKS_TO_MS macro being used. 2014-07-03 16:49:29 +00:00
Richard Barry
d96dc2adb0 Simply some of the alignment calculations in heap_4.c to match those used in heap_5.c. 
Remove some apparently obsolete code from xTaskPriorityDisinherit() (a task cannot be both blocked and giving bac a mutex at the same time].
Update the new "mutex held count" increment and decrement functions to allow mutexes to be created before the scheduler is started.
 2014-07-03 14:44:37 +00:00
Richard Barry
b0ba273489 Check in the portable.h version required to use heap_5.c. 2014-07-02 10:20:35 +00:00
Richard Barry
4b26dc0614 Check in the new memory allocator that allows the heap to span multiple blocks. 2014-07-02 10:19:49 +00:00
Richard Barry
4ce4de750a Update timer demo in PIC32MZ demo to remove multiple extern definition created by adding in the macro that checks non ISR safe functions are not called from ISRs. 2014-06-16 13:07:01 +00:00
Richard Barry
42b1688a30 Implementation of mutex held counting in tasks.c - needs optimisation before release. 2014-06-16 12:55:50 +00:00
Richard Barry
583b144bc3 Default the definition of portASSERT_IF_IN_ISR() to nothing if it is not defined. 
Helper updates to allow a count of the number of mutexes held to be added.
Updates to the CCS Cortex-R4 implementation necessitated by a change in compiler semantics.
Update PIC32MX and MZ ports to assert if a non ISR safe function is called from an ISR.
 2014-06-16 12:51:35 +00:00
Richard Barry
b4659d8872 Add code to assert() if non ISR safe API function is called from ISR in Tasking CM4F ports - plus fix bug where the max syscall interrupt priority was used incorrectly in the Tasking CM4F port. 2014-06-15 09:24:08 +00:00
Richard Barry
113220628f Add code to assert() if non ISR safe API function is called from ISR in IAR and GCC CM3 and CM4F ports - Keil and tasking to follow. 2014-06-14 13:56:25 +00:00
Richard Barry
4723209074 Simplify the assert that checks if a non-ISR safe function is called from an ISR in the GCC Cortex-A9 port. 2014-06-13 14:08:28 +00:00
Richard Barry
d45f18cc8d Add additional comments to the Zynq lwIP demo. 2014-06-13 14:06:43 +00:00
Richard Barry
8426eba8e7 Added portASSERT_IF_IN_INTERRUPT() macro to the GCC Cortex A9 port layer. 2014-06-12 16:28:56 +00:00
Richard Barry
de7df3cfda Zynq demo: Fix Xilinx network driver by deferring the function that allocated memory from the interrupt into a task. Add DHCP option. 2014-06-12 16:27:35 +00:00
Richard Barry
f1a0534a56 Remove some of the lwip asserts to allow use with 64-bit alignment. 2014-06-10 16:29:32 +00:00
Richard Barry
7fa64efeeb Switch to using the private watchdog as the run time stats timer in the Zynq demo. 2014-06-10 16:25:46 +00:00
Richard Barry
2f6cb8a86c Reorganise Zynq project after spitting lwIP example into a separate configuration. 2014-06-09 20:20:23 +00:00
Richard Barry
e92795bcc8 Move the Zynq's lwIP example from the Full demo into its own configuration as having the lwIP tasks at a high priority made the self checking test tasks report failures, while having the lwIP tasks at a low priority slugged the throughput. 2014-06-09 19:35:08 +00:00
Richard Barry
be8b0ed21d Update lwIP byte alignment to make Zynq pings more reliable. 2014-06-09 12:43:18 +00:00
Richard Barry
16ff69e873 Update RL78 GCC demo application after testing with fixed compiler. 2014-06-05 12:44:38 +00:00
Richard Barry
9efb5c8b2f Check in RL78 GCC port layer now it has been verified with the fixed compiler. 2014-06-05 12:42:49 +00:00
Richard Barry
5cbab67186 Complete RX64M GCC demo. 2014-06-04 09:19:16 +00:00
Richard Barry
1130a53ec8 Reverse order of projdefs.h and FreeRTOSConfig.h includes in FreeRTOS.h to allow addition of pdMS_TO_TICKS() macro. 
Update RXv2 GCC port to match RXv2 Renesas port.
 2014-06-04 09:17:14 +00:00
Richard Barry
5cd0b1e5ef Add -nomessage command line option to RX64M demo to suppress warning about the yield function being defined when it is not called directly. 2014-05-29 13:56:16 +00:00
Richard Barry
f46070dc79 Ensure demo app files are using FreeRTOS V8 names - a few were missed previously. 2014-05-29 13:54:15 +00:00
Richard Barry
ef254df85f A few additional casts to keep the Renesas RX compiler happy. 2014-05-29 13:39:48 +00:00
Richard Barry
74ffdb0b89 Add lwIP driver into Zynq demo - not yet fully functional. 2014-05-23 16:38:18 +00:00
Richard Barry
09a89763ee Add brackets in lwIP assert statement to prevent compiler warnings. 2014-05-23 16:36:49 +00:00
Richard Barry
b215310e63 Add some missing volatiles to __asm statements in the CA9 GCC port. 2014-05-19 13:14:02 +00:00
Richard Barry
0bb794301a Update version number ready for release. 2014-04-24 14:26:36 +00:00
Richard Barry
911e82a909 Add xQueueGetMutexHolder() to MPU functions. 2014-04-24 12:29:40 +00:00
Richard Barry
f25503977e Event Groups: Convert the 'clear bits from ISR' function into a pended function to fix reentrancy issue. 
Event Groups: Ensure the 'wait bits' and 'sync' functions don't return values that still contain some internal control bits.
 2014-04-23 15:23:54 +00:00
Richard Barry
fa7222ab4a Update demos that use FreeRTOS+FAT SL to have correct version numbers after the update of FreeRTOS+FAT SL itself. 2014-04-23 14:34:49 +00:00
Richard Barry
03c95b5950 Update IAR XMC4200 project to fix link error that resulted from updating the IAR version to 7.x. 2014-04-23 13:59:56 +00:00
Richard Barry
6af9b013eb Ensure xNewLib_reent is reclaimed when a task is deleted. 2014-04-09 09:07:19 +00:00
Richard Barry
82207ebffa Add test and correct code for the unusual case of a task using an event group to synchronise only with itself. 
Add critical sections around call to prvResetNextTaskUnblockTime() that can occur from within a task.
 2014-03-31 02:12:17 +00:00
Richard Barry
ef7f3c5320 Add the pcTimerGetTimerName() API function. 2014-03-28 14:41:15 +00:00