David Chalco
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07f3cbafee
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[AUTO][RELEASE]: Bump file header version to "202011.00"
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2020-11-10 14:45:34 -08:00 |
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David Chalco
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0573fea3ee
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Update (.s, .S) kernel version numbers to 10.4.1 (#283)
* version bump to 10.4.1
* update .s file version numbers
* Update FreeRTOS/History.txt
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2020-09-18 10:55:01 -07:00 |
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Cobus van Eeden
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d5862dbe01
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Sync back V10.4.1 (#282)
* Move Kernel submodule pointer to 10.4.1
* Update version number to V10.4.1 (#281)
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2020-09-17 17:16:33 -07:00 |
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David Chalco
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89d475e9b1
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Update Version number to 10.4.0 (#237)
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2020-09-10 19:40:24 -07:00 |
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Cobus van Eeden
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989924f6cb
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Adding some url files and moving the kernel pointer along (#260)
* Added some URL files and move submodule pointer along
* Add SiFive_HiFive1_RTOS_demo.url
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2020-09-10 18:37:20 -07:00 |
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Yuhui Zheng
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fa74f7dccf
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Removing writes to read-only PLIC interrupt pending registers.
Signed-off-by: Yuhui Zheng <10982575+yuhui-zheng@users.noreply.github.com>
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2020-04-07 10:09:20 -07:00 |
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David Chalco
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1cd2d38d96
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unix separators for path and remove .exe suffix from risc compiler (works on windows/mac)
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2020-03-22 20:23:03 -07:00 |
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Carl Lundin
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52c82076b3
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use relative path to point to bundled toolchain instead (#25)
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2020-03-05 09:16:31 -08:00 |
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Yuhui.Zheng
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589dd9f149
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Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.
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2020-02-07 20:14:50 +00:00 |
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Richard Barry
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d2914041f8
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Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant.
Update the IAR RISC-V HiFive demo to use the latest IAR Embedded Workbench version.
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2020-01-09 02:28:45 +00:00 |
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Richard Barry
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dfc1bf8ec3
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Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware.
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2020-01-01 22:05:35 +00:00 |
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