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Author SHA1 Message Date
Kody Stribrny
54d4eeaa26
Add Vectored Interrupt Support To SiFive RISC-V Demo (#871) 
Update SiFive IAR demo to support vectored interrupts. This is a near copy of https://github.com/FreeRTOS/FreeRTOS/pull/797.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
 2022-11-09 10:34:04 -08:00