len0rd/FreeRTOS-Kernel
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2484 commits 2 branches 99 tags 168 MiB
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4 commits

Author SHA1 Message Date
Gaurav Aggarwal 56dc0dd9b4 Merge bug fixes from Cadence 2018-08-07 07:21:07 +00:00
Richard Barry 483f4a8c4b Small change to the directory name in which the RISC-V port is stored. 2018-06-20 21:15:04 +00:00
Richard Barry 3d8d2f3cc8 Add RISCV port layer. 2018-06-20 19:21:18 +00:00
Gaurav Aggarwal c4b1afc4ef Add Xtensa port 
The project file is for Xtensa Xplorer simulator.
Also add tests for one size stream buffer.
 2018-06-14 19:43:17 +00:00