* Introduce portHAS_NESTED_INTERRUPTS to identify if port has nested interrupt or not.
* Update atomic.h to use portHAS_NESTED_INTERRUPTS instead of portSET_INTERRUPT_MASK_FROM_ISR definition.
---------
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: ActoryOu <jay2002824@gmail.com>
* Support configurable RISC-V chip extension
Added the FREERTOS_RISCV_EXTENSION option to allow the user
to select which chip extension they want included. Removed the
port for pulpino to instead use the new option.
* Add port GCC_RISC_V_GENERIC and IAR_RISC_V_GENERIC
* Add two rics-v generic ports to support FREERTOS_RISCV_EXTENSION
config
---------
Co-authored-by: Joe Benczarski <jbenczarski@trijicon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Add trace hook macro for most ports
In pull request #659 we introduced better support for tracing
tools like systemview. This patchset adds support for more
ports as requested in the original pull request.
* Use new version of CI-CD Actions
* Use cSpell spell check, and use ubuntu-20.04 for formatting check
* Format and spell check all files in the portable directory
* Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /*
* Use checkout@v3 instead of checkout@v2 on all jobs
---------
Adds RV32E support to the IAR port. This is done by
reducing our register usage to the first 16 registers
only.
Influenced by changes in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/543
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
* Change vPortSetupTimerInterrupt in order to have 64bits access on rv64
* Support RV32E - RISC-V architecture (GCC)
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
* Support FPU - RISC-V architecture (GCC)
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
* Fix interrupt managment and FPU initialization
* Style: make freertos.org = FreeRTOS.org also add https
* Style: Fix freertos into FreeRTOS
* Style: Fix freertos into FreeRTOS
Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
* Style: Change FreeRTOS websites in comments
* Style: Change freertos to FreeRTOS in comments
* Style: Remove broken link
Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
* fix: CLEAR MIE BIT IN INITIAL RISC-V MSTATUS VALUE
The MIE bit in the RISC-V MSTATUS register is used to globally enable
or disable interrupts. It is copied into the MPIE bit and cleared
on entry to an interrupt, and then copied back from the MPIE bit on
exit from an interrupt.
When a task is created it is given an initial MSTATUS value that is
derived from the current MSTATUS value with the MPIE bit force to 1,
but the MIE bit is not forced into any state. This change forces
the MIE bit to 0 (interrupts disabled).
Why:
If a task is created before the scheduler is started the MIE bit
will happen to be 0 (interrupts disabled), which is fine. If a
task is created after the scheduler has been started the MIE bit
is set (interrupts enabled), causing interrupts to unintentionally
become enabled inside the interrupt in which the task is first
moved to the running state - effectively breaking a critical
section which in turn could cause a crash if enabling interrupts
causes interrupts to nest. It is only an issue when starting a
newly created task that was created after the scheduler was started.
Related Issues:
https://forums.freertos.org/t/risc-v-port-pxportinitialisestack-issue-about-mstatus-value-onto-the-stack/9622
Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>
