5 commits

Author	SHA1	Message	Date
Richard Barry	11c391dfb3	Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo.	2019-10-22 02:15:28 +00:00
Richard Barry	b51529a284	Update version number ready for next release.	2019-05-11 01:47:37 +00:00
Richard Barry	58ba10eee8	Update version number in readiness for V10.2.0 release.	2019-02-17 22:36:16 +00:00
Richard Barry	fb73829148	Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). ... Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task. Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.	2019-02-08 01:18:08 +00:00
Richard Barry	80f6f3e59b	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	2018-12-24 17:48:10 +00:00