5 commits

Author	SHA1	Message	Date
Yuhui.Zheng	589dd9f149	Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.	2020-02-07 20:14:50 +00:00
Richard Barry	7bea399061	Update libraries and sundry check-ins ready for the V10.3.0 kernel release.	2020-02-06 18:52:35 +00:00
Richard Barry	066e2bc7d2	Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.	2020-01-09 02:23:51 +00:00
Richard Barry	da3d370ff7	RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.	2019-09-04 15:46:45 +00:00
Richard Barry	ab41d89285	Add IAR RISC-V port to SVN - a work in progress.	2019-09-03 01:39:29 +00:00