4 commits

Author	SHA1	Message	Date
Richard Barry	066e2bc7d2	Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.	2020-01-09 02:23:51 +00:00
Richard Barry	16639d2d63	Update to the latest atomic.h. ... Improve commenting in RISC-V GCC port. Fix IAR RISC-V port so the first task starts with interrupts enabled. Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced. Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section. Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.	2019-11-18 16:28:03 +00:00
Richard Barry	80c1cb5de1	Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR. ... Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).	2019-09-24 16:06:21 +00:00
Richard Barry	ab41d89285	Add IAR RISC-V port to SVN - a work in progress.	2019-09-03 01:39:29 +00:00