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19 commits

Author SHA1 Message Date
Richard Barry 7d6758ee1a Minor updates and change version number for V7.5.0 release. 2013-07-17 18:32:57 +00:00
Richard Barry 65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler. 
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
 2013-07-09 17:57:59 +00:00
Richard Barry c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 2013-07-04 11:20:28 +00:00
Richard Barry a7c47131fa Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose. 2013-06-25 13:39:50 +00:00
Richard Barry a03b171992 Fix compiler warning in psp_test.c when compiled with ARM compiler. 
Add portYIELD_FROM_ISR() macros to Cortex-M ports.  The new macro just calls the exiting portEND_SWITCHING_ISR() macro.
Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
 2013-05-19 09:43:00 +00:00
Richard Barry 96ceae8edd Update version number ready to release the FAT file system demo. 2013-04-30 21:42:41 +00:00
Richard Barry f9918345e1 Update version numbers to V7.4.1. 2013-04-18 12:58:17 +00:00
Richard Barry 0527099b51 Add barrier instructions to the GCC CM3 ports. 2013-04-16 14:16:30 +00:00
Richard Barry a5d0e3f0c1 Prepare for V7.4.0 release. 2013-02-19 18:36:58 +00:00
Richard Barry ba686260ca Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source. 2012-10-29 15:56:26 +00:00
Richard Barry f5c52bdb1d Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used. 2012-10-22 16:40:45 +00:00
Richard Barry f06a945444 Prepare for V7.3.0 release. 2012-10-16 12:17:47 +00:00
Richard Barry e03ab659f3 Add tickless idle support in Cortex-M ports. 
Change CCS R4 directory name.
 2012-10-16 07:55:40 +00:00
Richard Barry c403e974ee Update PIC32 port to make use of configUSE_PORT_OPTIMISED_TASK_SELECTION. 
Make small modification in GCC CM3 port when configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 to remove compiler warning.
 2012-09-25 18:18:37 +00:00
Richard Barry 87f663a461 Correct #if( configMAX_PRIORITIES >= 32 ) check performed when configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 to instead be #if( configMAX_PRIORITIES > 32 ). 2012-09-24 12:10:08 +00:00
Richard Barry 92f1699055 Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers. 
Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
 2012-09-24 11:01:17 +00:00
Richard Barry 0c7af1c2d3 Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR. 2012-08-14 13:04:22 +00:00
Richard Barry e0bab5981a Prepare for V7.2.0 release. 2012-08-14 12:14:48 +00:00
Richard Barry f508a5f653 Add FreeRTOS-Plus directory. 2012-08-11 21:34:11 +00:00
Renamed from Source/portable/GCC/ARM_CM4F/portmacro.h (Browse further)